CN104572558B - A kind of read-write operation change-over circuit of isa bus to Multibus buses - Google Patents
A kind of read-write operation change-over circuit of isa bus to Multibus buses Download PDFInfo
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- CN104572558B CN104572558B CN201510010280.9A CN201510010280A CN104572558B CN 104572558 B CN104572558 B CN 104572558B CN 201510010280 A CN201510010280 A CN 201510010280A CN 104572558 B CN104572558 B CN 104572558B
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
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Abstract
The invention discloses a kind of read-write operation change-over circuit of isa bus to Multibus buses.The isa bus operates the asynchronous read and write that the synchronous read-write operation of isa bus is converted to Multibus buses to the read-write operation change-over circuit of Multibus buses, realizes read-write operation of the isa bus main equipment to Multibus bus slaves.The present invention is simple in construction, supports 8 and 16 bit data widths, address wire can need to be extended according to user, available for trunk mixed Computer System Design.The present invention solves the mixed insertion and compatibling problem that Multibus bus slaves are configured on isa bus cabinet, is widely used in fields such as the design of trunk mixed ruggedized computer, computer bus board testing and diagnosings.
Description
Technical field
The invention belongs to ruggedized computer design field, the read-write of particularly a kind of isa bus to Multibus buses is grasped
Make change-over circuit.
Background technology
PCI/CPCI, Multibus, ISA are ruggedized computer main flow device bus, and general computer system is using single
Computer bus, forms Series Design, such as pci bus computer, cpci bus computer, Multibus bus computers, ISA
Bus computer, configuration module generally comprise computer primary module, A/D module and 232 serial port modules, special functional module etc. from
Equipment.In ruggedized computer design, to improve system reliability as far as possible, it is desirable to used in new system and identified mature modules
Or equipment, such as in isa bus computer using identified Multibus buses slave module (A/D module, 232 serial port modules,
Special functional module etc.), form trunk mixed computer system.But, it there is no the isa bus of maturation to arrive in the prior art
The read-write operation conversion circuit module of Multibus buses, it is impossible to solve to configure Multibus buses on isa bus cabinet from setting
Standby mixed insertion and compatibling problem.
The content of the invention
It is an object of the invention to provide a kind of read-write operation change-over circuit of isa bus to Multibus buses.
The technical solution for realizing the object of the invention is：A kind of isa bus turns to the read-write operation of Multibus buses
Change circuit, including state carry circuit, sequential processing circuit, reset circuit, interrupt circuit；The core ISA tri- of isa bus
Bus (controlling bus, address bus, data/address bus) is connected with state carry circuit and sequential processing circuit, and isa bus resets
Signal is connected with reset circuit, and isa bus interrupt signal is connected with interrupt circuit, state carry circuit output timing control signal
To sequential process circuit；The buses of core Multibus tri- of Multibus buses and state carry circuit and sequential processing electricity
Road is connected, and Multibus bus reset signals are connected with reset circuit, and Multibus bus interrupt signals are connected with interrupt circuit,
Reset circuit exports general reset signal to state carry circuit and sequential processing circuit, and reset circuit is also connected with system reset
Connect.
State carry circuit is using work clock of the isa bus clock as state machine, according to isa bus and Multibus
The control signal of bus input, state transfer processing, output timing control signal to sequential are carried out by synchronous finite state-machine
Process circuit.
The timing control signal that sequential processing circuit is provided according to state carry circuit is carried out at sequential to the buses of ISA tri-
Reason, realizes the buses of ISA tri- to the timing conversion of the read-write operation of the buses of Multibus tri-.
Interrupt circuit receives Multibus bus interrupt signals from Multibus buses, and output isa bus interrupt signal is extremely
Isa bus, realizes the transfer processing of interrupt signal.
Reset circuit realizes isa bus reset signal to the conversion of Multibus bus reset signals, and provides state turn
The general reset signal that shift circuit and sequential processing circuit are used.
Multibus buses abbreviation M buses in the present invention.
Compared with prior art, its remarkable advantage is the present invention：1) circuit structure of the invention is simple, supports 8 and 16
Bit data width, address wire can be extended as needed；2) circuit conversion efficiency is high, and frequency adaptability is strong, Ke Yiyong
In 7MHz~10MHz isa bus clock ranges；3) the circuit highly versatile, can be in general CPLD/FPGA logic chips
Upper to realize, occupancy resource is few, low in energy consumption；4) circuit is changed by the read-write sequence of isa bus to Multibus buses, is realized
Configured on isa bus cabinet the mixed insertions of Multibus bus slaves with it is compatible；5) in testing field, based on isa bus
Test system, except directly test isa bus module in addition to, if use circuit of the present invention, can extend test Multibus it is total
Line slave module, and then improve system testing ability.
The present invention is described in further detail below in conjunction with the accompanying drawings.
Brief description of the drawings
Fig. 1 is the composition frame chart of isa bus of the invention to the read-write operation change-over circuit of Multibus buses.
Fig. 2 is the external signal connection figure of the state carry circuit of the present invention.
External signal connections and composition frame chart of the Fig. 3 for the sequential processing circuit of the present invention.
Fig. 4 is the circuit block diagram of the state carry circuit of the present invention.
Fig. 5 is the state transition diagram of the state machine of the present invention.
Fig. 6 is the circuit block diagram of the address conversion circuit of the present invention.
Fig. 7 is the circuit block diagram of the read write command change-over circuit of the present invention.
Fig. 8 writes the circuit block diagram of change-over circuit for the data of the present invention.
Fig. 9 reads the circuit block diagram of change-over circuit for the data of the present invention.
Figure 10 is the circuit block diagram of the feedback circuit of the present invention.
Figure 11 is the circuit block diagram of the reset circuit of the present invention.
Embodiment
The invention discloses a kind of read-write operation change-over circuit of isa bus to Multibus buses, the same of isa bus
Step read-write operation be converted to Multibus buses asynchronous read and write operation, realize isa bus main equipment to Multibus buses from
The read-write operation of equipment, solves the mixed insertion and compatibling problem that Multibus bus slaves are configured on isa bus cabinet, mixed
The fields such as the design of bus ruggedized computer, computer bus board testing and diagnosing are closed to be widely used.
With reference to accompanying drawing 1, illustrate the isa bus of the present invention to the composition of the read-write operation change-over circuit of Multibus buses.
A kind of isa bus is to the read-write operation change-over circuit of Multibus buses, including state carry circuit, sequential processing
Circuit, reset circuit, interrupt circuit；The buses of core ISA tri- (controlling bus, address bus, data/address bus) of isa bus
It is connected with state carry circuit and sequential processing circuit, isa bus reset signal is connected with reset circuit, isa bus interrupts letter
Number it is connected with interrupt circuit, state carry circuit output timing control signal to sequential process circuit；The core of Multibus buses
The center portion point buses of Multibus tri- are connected with state carry circuit and sequential processing circuit, and Multibus bus reset signals are with answering
Position circuit is connected, and Multibus bus interrupt signals are connected with interrupt circuit, and reset circuit exports general reset signal and turned to state
Shift circuit and sequential processing circuit, and Mulitbus bus reset signals are exported to Multibus buses；Reset circuit is also with being
System reset is connected.
State carry circuit is using work clock of the isa bus clock as state machine, according to isa bus and Multibus
The control signal of bus input, state transfer processing, output timing control signal to sequential are carried out by synchronous finite state-machine
Process circuit.
The timing control signal that sequential processing circuit is provided according to state carry circuit is carried out at sequential to the buses of ISA tri-
Reason, realizes the buses of ISA tri- to the timing conversion of the read-write operation of the buses of Multibus tri-.
Interrupt circuit receives Multibus bus interrupt signals from Multibus buses, and output isa bus interrupt signal is extremely
Isa bus, realizes the transfer processing of interrupt signal.
Reset circuit realizes isa bus reset signal to the conversion of Multibus bus reset signals, and provides state turn
The general reset signal that shift circuit and sequential processing circuit are used.
In the present invention, the signal identification of same names represents same electrical connection, Multibus bus abbreviation M buses.
With reference to accompanying drawing 1, accompanying drawing 2, accompanying drawing 4 and accompanying drawing 5, illustrate that external connection, composition and the work of state carry circuit are former
Reason.
The signal that state carry circuit is connected with the buses of ISA tri- includes isa bus clock (isa_bclk), isa bus and deposited
Reservoir reads (isa_memr, low effectively), isa bus memory and writes (isa_memw, low effectively), isa bus I/O readings (isa_
It is ior, low effectively), isa bus I/O write (isa_iow, effectively low)；The letter that state carry circuit is connected with the buses of Multibus tri-
Number confirm (m_xack, effectively low) for M bus transfers, state carry circuit is output to the timing control signal of sequential processing circuit
Including：Isa bus reads (isa_rd, high effectively), isa bus and writes (isa_wt, high effectively), isa bus read/write (isa_rd_
It is wt, high effectively), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END (high effectively)；State transfer electricity
The reset signal on road is to carry out the general reset of self-resetting circuit (rst, high effectively)；
State carry circuit is equal to equal to comparator [E02], the 3rd equal to comparator [E01], second including first and compared
Device [E03], the 4th are equal to comparator [E04], the 5th equal to comparator [E05], the first OR gate [OR01], the second OR gate
[OR02], the 3rd OR gate [OR03], the first multiplexer [M01], the second multiplexer [M02], the first d type flip flop
[D01], first state machine module [U01]；
High level, unequal output low level are exported during above-mentioned A inputs and equal B inputs equal to comparator.On
The first multiplexer [M01] is stated for alternative multiplexer, the second multiplexer [M02] selects a multiplexer for four；Alternative
D0 inputs are connected with Q output when the S selections end of multiplexer is low level, and the S selections end of alternative multiplexer is high level
When D1 inputs be connected with Q output；Four select [S1, the S2] of multiplexer D0 inputs and Q output when to select end be 2 ' b00
Connection, D1 inputs are connected with Q output when [S1, S2] selection end is 2 ' b01, and D2 is inputted when [S1, S2] selection end is 2 ' b10
End is connected with Q output, and D3 inputs are connected with Q output when [S1, S2] selection end is 2 ' b11；First is equal to comparator
[E01], second be equal to comparator [E02], the 3rd be equal to comparator [E03], the 4th be equal to comparator [E04], the 5th be equal to than
Input compared with device [E05] is 4 bit widths, data terminal, the second multiplexer [M02] of the first multiplexer [M01]
Data terminal, the data terminal of the first d type flip flop [D01], the 5th be equal to comparator [E05] input be 2 bit widths, first
OR gate [OR01], the second OR gate [OR02], the external interface of the 3rd OR gate [OR03] and first state machine module [U01] are
1 bit width；
First is equal to equal to comparator [E01], second equal to comparator [E02], the 3rd equal to comparator [E03], the 4th
The A inputs of comparator [E04] are connected, and isa bus I/O is consecutively connected to from a high position to low level writes isa_iow, isa bus to deposit
Reservoir writes isa_memw, isa bus I/O and reads isa_ior, isa bus memory reading isa_memr；First is equal to comparator
The B inputs of [E01] are connected to level state 4 ' hE from a high position to low level, and second is equal to the B inputs of comparator [E02] from height
Position is connected to the hD of level state 4 ' to low level, and the 3rd B inputs for being equal to comparator [E03] are connected to level from a high position to low level
The hB of state 4 ', the 4th B inputs for being equal to comparator [E04] are connected to the h7 of level state 4 ' from a high position to low level；First is equal to
The OUT output ends of comparator [E01] are connected to the first OR gate [OR01] input 1, and second is defeated equal to the OUT of comparator [E02]
Go out end and be connected to the first OR gate [OR01] input 2, the output end signal of the first OR gate [OR01] read for isa bus (isa_rd,
It is connected to the input 1 of the 3rd OR gate [OR03] and is output to sequential processing circuit, the 3rd is defeated equal to the OUT of comparator [E03]
Go out end and be connected to the second OR gate [OR02] input 1, the 4th OUT output ends for being equal to comparator [E04] are connected to the second OR gate
[OR02] input 2, the output end signal of the second OR gate [OR02] writes (isa_wt) for isa bus, is connected to the 3rd OR gate
The input 2 of [OR03] is simultaneously output to sequential processing circuit, and the output end signal of the 3rd OR gate [OR03] is isa bus read/write
(isa_rd_wt) the T1 inputs of first state machine module [U01], are connected to and sequential processing single channel is output to；
The D1 inputs of first multiplexer [M01] are connected to the b11 of level state 2 ', the first multiplexing from high to low
The anti-phase S selections end of device [M01] is connected to external signal M bus transfers and confirms m_xack, the Q of the first multiplexer [M01]
Output end is connected to the D2 inputs of the second multiplexer [M02], and the D0 inputs of the second multiplexer [M02] are from a high position
The b01 of level state 2 ' is connected to low level, the D1 inputs of the second multiplexer [M02] are connected to level from a high position to low level
The b10 of state 2 ', the D3 inputs of the second multiplexer [M02] are connected to the b00 of level state 2 ' from a high position to low level, more than second
The Q output of path multiplexer [M02] is connected to the D inputs of the first d type flip flop [D01], the clock of the first d type flip flop [D01]
End is connected to isa bus clock isa_bclk, and the EN Enable Pins of the first d type flip flop [D01] are connected to status signal RD_WT, the
The CLR reset terminals of one d type flip flop [D01] are connected to general reset rst, and the Q output of the first d type flip flop [D01] is count signal
Isa_ws_cnt, [S1, S2] selection of D0 inputs, the second multiplexer [M02] with the first multiplexer [M01]
End, the 5th A inputs for being equal to comparator [E05] are connected, and are output to sequential processing circuit, and the 5th is equal to comparator [E05]
B inputs level state 2 ' b11 is connected to from a high position to low level, the 5th OUT output ends for being equal to comparator [E05] are connected to
The T2 inputs of first state machine module [U01]；The CLK clocks end of first state machine module [U01] is connected to isa bus clock
Isa_bclk, the CLR reset terminals of first state machine module [U01] are connected to general reset rst, first state machine module [U01]
State output end signals include status signal IDLE, RD_WT, BT_END, are respectively outputted to sequential processing circuit.
The first state machine module [U01] is used as state machine work clock, first using isa bus clock isa_bclk
The state jump condition of state machine module [U01] includes T1 and T2, and effective status includes state1, state2, state3, respectively
Corresponding states signal IDLE, RD_WT, BT_END (being that high level is effective), system is in state1 shapes when general reset rst is effective
State, status signal IDLE is effective, under the normal running conditions that general reset rst is cancelled, (T1=0), state machine when T1 is invalid
In state1 states, when T1 is effective (T1=1), state machine is transferred to state2 states, and status signal RD_WT is effective, when
When T2 is invalid, state machine is in state2 states, when T2 is effective (T2=1), and state machine is transferred to state3 states, state letter
Effectively, state3 states are stopped after an isa bus clock (isa_clk), are transferred to state1 states by number BT_END, are completed
The state transfer operation of state machine.
The state transfer control of the main completion status machine of state carry circuit, when carrying out isa bus memory read operation,
B1110=4 ' the hE of [isa_iow, isa_memw, isa_ior, isa_memr]=4 ', when carrying out isa bus I/O read operations,
B1101=4 ' the hD of [isa_iow, isa_memw, isa_ior, isa_memr]=4 ', when progress isa bus memory write operation
When, the b1011=4 ' hB of [isa_iow, isa_memw, isa_ior, isa_memr]=4 ', when progress isa bus I/O write operations
When, the b0111=4 ' h7 of [isa_iow, isa_memw, isa_ior, isa_memr]=4 '；Therefore, the first OR gate [OR01] is defeated
It is that isa bus reads isa_rd to go out end signal, and the output end signal of the second OR gate [OR02] is that isa bus writes isa_wt, the
The output end signal (namely state jump condition T1 of first state machine module [U01]) of three OR gates [OR03] be isa bus read/
Write isa_rd_wt；When there is effective isa bus read command, isa_rd is effective, when the effective isa bus write order of appearance
When, effectively, when the effective isa bus of appearance reads or writes order, effectively, i.e., T1 is effective by isa_rd_wt by isa_wt；
When general reset rst is effective, the Q output signal of the first d type flip flop [D01] is that count signal isa_ws_cnt is
2 ' b00, under state2 states, status signal RD_WT is effective, the first d type flip flop [D01] and the second multiplexer [M02]
A controlled counter is constituted, count signal isa_ws_cnt is added since 2 ' b00 according to isa bus clock isa_bclk
1 counts；When isa_ws_cnt is 2 ' b10, if M bus transfers confirm m_xack effectively (low level), isa_ws_cnt is just
Often Jia 1 is changed into 2 ' b11, if M bus transfers confirm that m_xack is invalid (high level), isa_ws_cnt remains 2 ' b10 states,
Until M bus transfers confirm that m_xack effectively (low level) Jia 1 again and is changed into 2 ' b11, isa_ws_cnt is changed into after 2 ' b11, under
One isa bus clock isa_bclk adds 1 again and resets to 2 ' b00, when count signal isa_ws_cnt is 2 ' b11, the first shape
The state jump condition T2 of state machine module [U01] is effective；
The isa bus operation cycle (no insertion latent period) of standard is six isa bus clock cycle, possible insertion
Latent period was located between the 5th isa bus operation cycle and the 6th isa bus operation cycle, even if insertion occur waits week
Phase, this isa bus operation cycle after insertion latent period was still called for the 6th isa bus operation cycle herein；
Isa_ws_cnt is 2 ' b10 the 5th isa bus operation cycles of correspondence and possible insertion latent period, and isa_ws_cnt is 2 '
B11 the 6th isa bus operation cycles of correspondence；
State1 states correspondence reset state, bus idle state and the first, second isa bus operation week of state machine
Phase, state2 states the 3rd to the 5th isa bus operation cycle of correspondence of state machine, possible insertion latent period and the 6th
Isa bus operation cycle, state3 states last extra isa bus cycle of correspondence of state machine；
Under reset or bus idle state, state machine is in state1 states, and status signal IDLE effectively, works as appearance
During isa bus read or write order, state machine is transferred to state2 states, and status signal RD_WT is effective, in state2 states
Under, it count down to for the 5th isa bus operation cycle from the 3rd isa bus operation cycle, the 5th isa bus operation cycle, sentences
Whether effectively disconnected M bus transfers confirm m_xack (whether the read-write of M bus datas completes), if m_xack is invalid, into etc.
The cycle is treated, if m_xack is effectively, in the 6th isa bus operation cycle, state machine is transferred to state3 shapes from state2 states
State, status signal BT_END effectively, takes an extra isa bus cycle (total for Multibus under state3 states
Line address, data are kept), state1 states are jumped directly to, terminate the transfer operation of this next state.
Illustrate external connection, comprising modules and the major function of the circuit of sequential processing circuit with reference to accompanying drawing 1, accompanying drawing 3.
The signal that sequential processing circuit is connected with the buses of ISA tri- include isa bus memory read (isa_memr, it is low to have
Effect), isa bus memory writes (isa_memw, effectively low), isa bus I/O and reads (isa_ior, low effectively), isa bus I/O
Write (isa_iow, low effectively), isa bus address (isa_addr), isa bus data (isa_dat), isa bus slave unit just
Thread (isa_chrdy, high effectively), the output signal for the state carry circuit that sequential processing circuit is received is read including isa bus
(isa_rd, high effective), isa bus write (isa_wt, high effectively), isa bus read/write (isa_rd_wt, high effectively), counting
Signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END (being high effectively), sequential processing circuit and Multibus
The signal of three buses connection include M bus drivers read (m_mrdc, effectively low), M bus drivers write (m_mwtc, it is low to have
Effect), M buses I/O reads (m_iorc, effectively low), M buses I/O to write (m_iowc, low effectively), M bus address (m_addr), M total
Line number confirms (m_xack, low effectively) according to (m_dat), M bus transfers, and the reset signal of sequential processing circuit carrys out self-resetting circuit
General reset (rst, effectively high)；
Sequential processing circuit includes address conversion circuit, read write command change-over circuit, data and writes change-over circuit, data reading turn
Change circuit, feedback circuit.Address conversion circuit, read write command change-over circuit, data write change-over circuit, data read change-over circuit,
As work clock, reset signal is used as using general reset (rst) using isa bus clock (isa_bclk) for feedback circuit.
When address conversion circuit is used to realize that isa bus address (isa_addr) arrives the read-write of M bus address (m_addr)
Sequence is changed, and the timing control signal of input includes isa bus read/write (isa_rd_wt), status signal IDLE, RD_WT, BT_
END；
Read write command change-over circuit be used for realize the order of isa bus read-write operation (isa bus memory read isa_memr,
Isa bus memory writes isa_memw, isa bus I/O reading isa_ior, I/O bus I/O and writes isa_iow) read and write behaviour to M buses
Order (M bus drivers read m_mrdc, M bus driver write m_mwtc, M bus I/O read m_iorc, M bus I/O write m_
Iowc read-write sequence conversion), the timing control signal of input includes count signal (isa_ws_cnt), status signal RD_WT；
Data, which write change-over circuit, is used for the write operation for realizing that isa bus data (isa_dat) arrive M bus datas (m_dat)
Timing conversion, the timing control signal of input includes isa bus reading (isa_rd), isa bus and writes (isa_wt), status signal
IDLE、RD_WT、BT_END；
Data, which read change-over circuit, is used to realize that the M bus datas (m_dat) of read operation to arrive isa bus data (isa_dat)
Read operation timing conversion, the timing control signal of input, which includes isa bus, to be read (isa_rd), isa bus and writes (isa_wt), meter
Number signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END, the feedback signal of input confirm (m_ for M bus transfers
xack)；
Feedback circuit is used to realize that M bus transfers confirm (m_xack) to isa bus slave unit ready (isa_chrdy)
The timing conversion of feedback signal, the timing control signal of input includes count signal (isa_ws_cnt), status signal RD_WT.
With reference to accompanying drawing 6, illustrate the composition and operation principle of address conversion circuit.
The address conversion circuit includes first selector [S01], the second d type flip flop [D02], 3d flip-flop
[D03], the first triple gate [T01]；First selector [S01] is No. three selectors, when only S0 selections end is high level, D0
Input is connected with OUT output ends, and when only S1 selections end is high level, D1 inputs are connected with OUT output ends, when only
When S2 selections end is high level, D2 inputs are gated with OUT output ends；First selector [S01], the second d type flip flop [D02]
Data terminal is 1 bit width, 3d flip-flop [D03], the data terminal corresponding address bus of the first triple gate [T01], data width
It can be adjusted according to practical application, be defaulted as 20 bit widths；
The D0 inputs of first selector [S01] are connected to high level, and the D1 inputs of first selector [S01] are connected to
Low level, the D2 inputs of first selector [S01] are connected to isa bus read/write isa_rd_wt, first selector [S01]
S0 selections end is connected to status signal BT_END, and the S1 selections end of first selector [S01] is connected to status signal RD_WT, the
The S2 selections end of one selector [S01] is connected to status signal IDLE, and OUT output ends and the 2nd D of first selector [S01] are touched
Send out the EN Enable Pins of device [D02], the EN Enable Pins of 3d flip-flop [D03] to be connected, the anti-phase D of the second d type flip flop [D02] is defeated
Enter end and be connected to status signal BT_END, the Q output of the second d type flip flop [D02] is connected to the first triple gate [T01] ENB
Enable Pin, the D inputs of 3d flip-flop [D03] are connected to isa bus address isa_addr, the Q of 3d flip-flop [D03]
Output end is connected to the first triple gate [T01] input, the second d type flip flop [D02], the clock end of 3d flip-flop [D03]
Isa bus clock isa_bclk is all connected to, the second d type flip flop [D02], the CLR reset terminals of 3d flip-flop [D03] connect
General reset rst is connected to, the output end of the first triple gate [T01] is connected to M bus address m_addr.
In state1 states, effectively, OUT output ends and the D2 inputs of first selector [S01] connect status signal IDLE
Logical, if there is isa bus read-write operation, isa_rd_wt is effective (high level), the second d type flip flop [D02], 3d flip-flop
[03] EN Enable Pins are high level, and the ENB Enable Pins of the first triple gate [T01] are high level, and the first triple gate [T01] is led
Logical, isa bus address isa_addr is output to M bus address m_addr；In state2 states, status signal RD_WT is effective, the
The OUT output ends of one selector [S01] are connected with D1 inputs as low level, the second d type flip flop [D02], 3d flip-flop
[03] close, M bus address m_addr is kept；In state3 states, status signal BT_END is effective, first selector [S01]
OUT output ends connected with D0 inputs as high level, the ENB Enable Pins of the first triple gate [T01] are low level, the first tri-state
Door [T01] is closed, and terminates the driving to M bus address m_addr, discharges M address bus.
Isa bus address isa_addr is with being output to M bus address m_addr, M bus in the second isa bus operation cycle
Location m_addr was remained to after the 6th isa bus operation cycle (correspondence M bus read write commands terminate), then kept an ISA total
The line cycle discharges.
With reference to accompanying drawing 7, illustrate the composition and operation principle of read write command change-over circuit.
The read write command change-over circuit includes the 3rd multiplexer [M03], four d flip-flop [D04]；3rd multichannel
Multiplexer [M03] selects a multiplexer for four, and the 3rd multiplexer [M03], four d flip-flop [D04] data terminal are 4 bit wides
Degree；
The D0 inputs of 3rd multiplexer [M03] be sequentially connected from a high position to low level isa bus I/O write isa_iow,
Isa bus memory writes isa_memw, isa bus I/O and reads isa_ior, isa bus memory reading isa_memr, the 3rd multichannel
The D1 inputs position corresponding with D2 inputs of multiplexer [M03] is connected, and position corresponding with the Q output of four d flip-flop [D04]
Connection, the D3 inputs of the 3rd multiplexer [M03] are connected to the hF of level state 4 ', the 3rd multiplexing from a high position to low level
[S1, S2] selection end of device [M03] is connected to count signal isa_ws_cnt, and the Q output of the 3rd multiplexer [M03] connects
The D inputs of four d flip-flop [D04] are connected to, the clock end of four d flip-flop [D04] is connected to isa bus clock isa_
Bclk, the EN Enable Pins of four d flip-flop [D04] are connected to status signal RD_WT, the SET set of four d flip-flop [D04]
End is connected to general reset rst, and the Q output of four d flip-flop [D04] is consecutively connected to M buses I/O from a high position to low level and writes m_
Iowc, M bus driver write m_mwtc, M bus I/O and read m_iorc, M bus driver reading m_mrdc.
In state2 states, effectively, count signal isa_ws_cnt is started counting up status signal RD_WT from 2 ' b00, isa_
When ws_cnt is 2 ' b00, isa bus read write command (isa_iow, isa_memw, isa_ior, isa_memr) is output to M buses
Read write command end (m_iowc, m_mwtc, m_iorc, m_mrdc), when isa_ws_cnt is 2 ' b01 and 2 ' b10, the read-write of M buses
(m_iowc, m_mwtc, m_iorc, m_mrdc) is ordered to keep constant, when isa_ws_cnt is 2 ' b11, M bus read write commands
(m_iowc, m_mwtc, m_iorc, m_mrdc) terminates (being all changed into high level)；
Isa bus read write command is output to M bus read write commands end, M buses read-write life in the 3rd isa bus operation cycle
Order remained to for the 6th isa bus operation cycle and terminates that (M bus read write commands terminate to terminate corresponding one with isa bus read write command
Cause).
With reference to accompanying drawing 8, accompanying drawing 9, illustrate that data write composition and operation principle that change-over circuit, data read change-over circuit.
The data, which write change-over circuit, includes the 4th multiplexer [M04], the 5th multiplexer [M05], more than the 6th
Path multiplexer [M06], second selector [S02], the 5th d type flip flop [D05], the 6th d type flip flop [D06], the second triple gate
[T02]；4th multiplexer [M04], the 5th multiplexer [M05], the 6th multiplexer [M06] are that alternative is answered
With device, second selector [S02] is No. 3 selectors, the 4th multiplexer [M04], the 5th multiplexer [M05], second
Selector [S02], the data terminal of the 5th d type flip flop [D05] are 1 bit width, the 6th multiplexer [M06], the 6th D triggerings
The data terminal corresponding data bus of device [D06], the second triple gate [T02], data width is 8 or 16, can be according to reality
Using adjustment；
The D0 inputs of 4th multiplexer [M04] and D1 inputs, the 5th d type flip flop of second selector [S02]
The Q output of [D05], the ENB Enable Pins of the second triple gate [T02] are connected, and the D1 inputs of the 4th multiplexer [M04] connect
High level is connected to, the S selections end of the 4th multiplexer [M04] is connected to isa bus and writes isa_wt, the 4th multiplexer
The Q output of [M04] is connected to the D0 inputs of the 5th multiplexer [M05], the D1 inputs of the 5th multiplexer [M05]
End is connected to low level, and the S selections end of the 5th multiplexer [M05] is connected to isa bus and reads isa_rd, the 5th multiplexing
The Q output of device [M05] is connected to the D2 inputs of second selector [S02], the D0 inputs connection of second selector [S02]
To low level, the S0 selections end of second selector [S02] is connected to status signal BT_END, the S1 choosings of second selector [S02]
Select end and be connected to status signal RD_WT, the S2 selections end of second selector [S02] is connected to status signal IDLE, the second selection
The OUT output ends of device [S02] are connected to the D inputs of the 5th d type flip flop [D05], the clock end of the 5th d type flip flop [D05] connects
Isa bus clock isa_bclk is connected to, the CLR reset terminals of the 5th d type flip flop [D05] are connected to general reset rst；
The D0 inputs of 6th multiplexer [M06] and Q output, the second triple gate of the 6th d type flip flop [D06]
The input of [T02] is connected, and the D1 inputs of the 6th multiplexer [M06] are connected to isa bus data isa_dat, the 6th
The S selections end of multiplexer [M06] is connected to isa bus and writes isa_wt, and the Q output of the 6th multiplexer [M06] connects
The D inputs of the 6th d type flip flop [D06] are connected to, the clock end of the 6th d type flip flop [D06] is connected to isa bus clock isa_
Bclk, the EN Enable Pins of the 6th d type flip flop [D06] are connected to status signal IDLE, the CLR reset terminals of the 6th d type flip flop [D06]
General reset rst is connected to, the output end of the second triple gate [T02] is connected to M bus datas m_dat.
The data, which read change-over circuit, includes the 7th multiplexer [M07], the 8th multiplexer [M08], more than the 9th
Path multiplexer [M09], the tenth multiplexer [M10], the 11st multiplexer [M11], third selector [S03], the 6th
Equal to comparator [E06], the 7th d type flip flop [D07], the 8th d type flip flop [D08], the 3rd triple gate [T03]；7th multichannel is answered
Data terminal with device [M07], the 8th multiplexer [M08], third selector [S03], the 7th d type flip flop [D07] is 1
Width, the 6th input for being equal to comparator [E06] is 2 bit widths, the 9th multiplexer [M09], the tenth multiplexer
[M10], the 11st multiplexer [M11], the 8th d type flip flop [D08], the data terminal corresponding data of the 3rd triple gate [T03]
Bus, data width is 8 or 16, can be adjusted according to practical application；
The D0 inputs of 7th multiplexer [M07] and D1 inputs, the 7th d type flip flop of third selector [S03]
The Q output of [D07], the ENB Enable Pins of the 3rd triple gate [T03] are connected, and the D1 inputs of the 7th multiplexer [M07] connect
Low level is connected to, the S selections end of the 7th multiplexer [M07] is connected to isa bus and writes isa_wt, the 7th multiplexer
The Q output of [M07] is connected to the D0 inputs of the 8th multiplexer [M08], the D1 inputs of the 8th multiplexer [M08]
End is connected to high level, and the S selections end of the 8th multiplexer [M08] is connected to isa bus and reads isa_rd, the 8th multiplexing
The Q output of device [M08] is connected to the D2 inputs of third selector [S03], the D0 inputs connection of third selector [S03]
To low level, the S0 selections end of third selector [S03] is connected to status signal BT_END, the S1 choosings of third selector [S03]
Select end and be connected to status signal RD_WT, the S2 selections end of third selector [S03] is connected to status signal IDLE, the 3rd selection
The OUT output ends of device [S03] are connected to the D inputs of the 7th d type flip flop [D07], and the clock end of the 7th d type flip flop [D07] connects
Isa bus clock isa_bclk is connected to, the CLR reset terminals of the 7th d type flip flop [D07] are connected to general reset rst；
The D0 inputs of 9th multiplexer [M09] and the D0 inputs of the tenth multiplexer [M10], more than the 11st
The D0 inputs of path multiplexer [M11], the Q output of the 8th d type flip flop [D08], the input phase of the 3rd triple gate [T03]
Even, the D1 inputs of the 9th multiplexer [M09] are connected to M bus data m_dat, the S choosings of the 9th multiplexer [M09]
Select end and be connected to isa bus reading isa_rd, the Q output of the 9th multiplexer [M09] is connected to the tenth multiplexer
The D1 inputs of [M10], the anti-phase S selections end of the tenth multiplexer [M10] is connected to M bus transfers and confirms m_xack, the
The Q output of ten multiplexers [M10] is connected to the D1 inputs of the 11st multiplexer [M11], and the 6th is equal to and compares
The A inputs of device [E06] are connected to count signal isa_ws_cnt, and the 6th is equal to the B inputs of comparator [E06] from high to low
The b10 of level state 2 ' is connected to, the 6th OUT output ends for being equal to comparator [E06] are connected to the 11st multiplexer [M11]
S selections end, the Q output of the 11st multiplexer [M11] is connected to the D inputs of the 8th d type flip flop [D08], the 8th D
The clock end of trigger [D08] is connected to isa bus clock isa_bclk, the EN Enable Pins connection of the 8th d type flip flop [D08]
To status signal RD_WT, the CLR reset terminals of the 8th d type flip flop [D08] are connected to general reset rst, the 3rd triple gate [T03]
Output end is connected to isa bus data isa_dat.
For data write operation, isa bus writes isa_wt for high level, and it is low level that isa bus, which reads isa_rd,
Under tri- states of state1, state2, state3, effectively, the 3rd selects by corresponding states signal IDLE, RD_WT, BT_END respectively
The output of device [S03] be low level, the ENB Enable Pins of the 3rd triple gate [T03] be low level, the 3rd triple gate [T03] close
Close, it is unidirectional input to make isa bus data isa_dat, in state1 states, and status signal IDLE is effective, second selector
[S02] is output as high level, the Enable Pin of the second triple gate [T02] is high level, the second triple gate [T02] conducting, M buses
The unidirectional output of data m_dat correspondences, isa bus data isa_dat is output to M bus data m_dat, in state2 states, shape
Effectively, the Enable Pin of the second triple gate [T02] remains high level to state signal RD_WT, and M bus datas m_dat is kept,
State3 states, effectively, the Enable Pin of the second triple gate [T02] is changed into low level, the second triple gate to status signal BT_END
[T02] is closed, M bus datas m_dat releases；
For data write operation, isa bus data are output to M bus datas m_dat, M in the second isa bus operation cycle
Next ISA that bus data m_dat was remained to after the 6th isa bus operation cycle (correspondence M bus read write commands terminate) is total
The line cycle discharges；
For data reading operation, isa bus write isa_wt be low level, isa bus read isa_rd be high level,
Under tri- states of state1, state2, state3, effectively, second selects by corresponding states signal IDLE, RD_WT, BT_END respectively
The output of device [S02] be low level, the ENB Enable Pins of the second triple gate [T02] be low level, the second triple gate [T02] close
Close, it is unidirectional input to make M bus datas m_dat；Under state1, state2 state, difference corresponding states signal IDLE, RD_
Effectively, third selector [S03] is output as high level to WT, the ENB Enable Pins of the 3rd triple gate [T03] are high level, the 3rd
Triple gate [T03] is turned on, under state2 states, and status signal RD_WT is 2 ' b10 in count signal isa_ws_cnt effectively
And when M bus transfers confirm m_xack for low level, M bus datas m_dat is sent to isa bus data terminal isa_dat,
Under state3 states, effectively, the Enable Pin of the 3rd triple gate [T03] is changed into low level, the 3rd triple gate to status signal BT_END
[T03] is closed, isa bus data isa_dat releases；
For data reading operation, since the 5th isa bus operation cycle, after waiting M bus datas m_dat effective, by M
Bus data m_dat is output to isa bus data terminal isa_dat, and isa bus data isa_dat remains to the 6th isa bus behaviour
Make the release of next isa bus cycle after the cycle (correspondence M bus read write commands terminate).
With reference to accompanying drawing 10, illustrate the composition and operation principle of feedback circuit.
The feedback circuit includes the 12nd multiplexer [M12], the 13rd multiplexer [M13], the 9th D triggerings
Device [D09]；12nd multiplexer [M12] selects a multiplexer for four, and the 13rd multiplexer [M13] is that alternative is multiplexed
Device, the 12nd multiplexer [M12], the 13rd multiplexer [M13], the data terminal of the 9th d type flip flop [D09] are 1
Bit width；
The D0 inputs of 12nd multiplexer [M12] and the D2 inputs of the 12nd multiplexer [M12], the 9th
The Q output of d type flip flop [D09], the S selections end of the 13rd multiplexer [M13] are connected, the 12nd multiplexer
The D1 inputs of [M12] are connected to high level, and the D3 inputs of the 12nd multiplexer [M12] are connected to low level, the tenth
[S1, S2] selection end of two multiplexers [M12] is connected to count signal isa_ws_cnt, the 12nd multiplexer
The Q output of [M12] is connected to the D inputs of the 9th d type flip flop [D09], and the clock end of the 9th d type flip flop [D09] is connected to
Isa bus clock isa_bclk, the EN Enable Pins of the 9th d type flip flop [D09] are connected to status signal RD_WT, the 9th d type flip flop
The CLR reset terminals of [D09] are connected to general reset rst, and the D0 inputs of the 13rd multiplexer [M13] are connected to high level,
The anti-phase D1 inputs of 13rd multiplexer [M13] are connected to M bus transfers and confirm m_xack, the 13rd multiplexer
The Q output of [M13] is connected to the ready isa_chrdy of isa bus slave unit.
Under the effective reset states of general reset rst, the Q output of the 9th d type flip flop [D09] is low level, isa bus
The ready isa_chrdy of slave unit is high level, under state1 states, and status signal IDLE is effective, the 9th d type flip flop [D09]
EN Enable Pins it is invalid, the ready isa_chrdy of isa bus slave unit remains high level, under state2 states, status signal
Effectively, when count signal isa_ws_cnt is 2 ' b00, the ready isa_chrdy of isa bus slave unit is still high level to RD_WT,
When isa_ws_cnt is 2 ' b01 and 2 ' b10, the ready isa_chrdy of isa bus slave unit is that M bus transfers confirm m_xack
Negate, when isa_ws_cnt be 2 ' b11 when, the ready isa_chrdy of isa bus slave unit be high level, in state3 states
Under, effectively, the EN Enable Pins of the 9th d type flip flop [D09] are invalid, the ready isa_ of isa bus slave unit by status signal BT_END
Chrdy remains high level；
M bus transfers confirm that m_xack is that low level is effective, represent that M buses write data and complete or read data ready, ISA is total
Line read-write operation can be ready in the 5th isa bus operation cycle and possible insertion latent period sampled I SA bus slaves
Isa_chrdy, to judge that it is whether ready that isa bus reads data, therefore the ready isa_chrdy of isa bus slave unit is the 4th to the
In six isa bus operation cycles, value be M bus transfers confirm m_xack inverse value, it is other in the case of be fixed as high level,
Its feedback function can be achieved.
With reference to accompanying drawing 11, illustrate the composition and operation principle of reset circuit.
Reset circuit receive isa bus reset (isa_resetdrv, effectively high) and system reset (sys_rst, it is low to have
Effect), M bus resets (m_init, low effectively) are exported, and export general reset (rst, high effectively) and arrive state carry circuit and sequential
Process circuit；
Reset circuit includes the 4th OR gate [OR04], the first NOT gate [N01]；4th OR gate [OR04], the first NOT gate [N01]
Port is 1 bit width, and the inverting input 1 of the 4th OR gate [OR04] is connected to system reset sys_rst, the 4th OR gate
The input of the NOT gate [N01] of input 2 and first of [OR04] is connected to isa bus and resets isa_resetdrv, the 4th OR gate
The output end of [OR04] is connected to general reset rst, and the output end of the first NOT gate [N01] is connected to M bus resets m_init.
Isa bus resets that isa_resetdrv is high effectively, and M bus resets m_init is low effectively, thus the two pass through it is non-
Door conversion, and the general reset rst that state carry circuit and sequential processing circuit are used is system reset sys_rst and ISA
Bus reset isa_resetdrv combination, system reset sys_rst resets isa_resetdrv with isa bus has one effectively
When, general reset rst is effective.Multibus bus abbreviation M buses.
From the foregoing, it will be observed that the circuit structure of the present invention is simple, 8 and 16 bit data widths are supported, address wire can be according to need
It is extended；The circuit conversion efficiency is high, and frequency adaptability is strong, can be used for 7MHz~10MHz isa bus clock model
Enclose；The circuit highly versatile, can be realized on general CPLD/FPGA logic chips, and occupancy resource is few, low in energy consumption；The electricity
Road is changed by the read-write sequence of isa bus to Multibus buses, realizes the configuration Multibus on isa bus cabinet total
The mixed insertion of line slave unit with it is compatible；In testing field, the test system based on isa bus, except directly testing isa bus module
Outside, if using circuit of the present invention, test Multibus bus slave modules can be extended, and then improve system testing ability.
Claims (4)
1. a kind of isa bus is to the read-write operation change-over circuit of Multibus buses, it is characterised in that：Electricity is shifted including state
Road, sequential processing circuit, reset circuit, interrupt circuit；Wherein the buses of core ISA tri- of isa bus shift electricity with state
Road is connected with sequential processing circuit, and the buses of core ISA tri- of isa bus are total including controlling bus, address bus, data
Line, isa bus interrupt signal is connected with interrupt circuit, state carry circuit output timing control signal to sequential process circuit；
The buses of core Multibus tri- of Multibus buses are connected with state carry circuit and sequential processing circuit, Multibus
Bus interrupt signal is connected with interrupt circuit, and reset circuit receives isa bus reset signal and systematic reset signal, and output is total multiple
Position signal exports Mulitbus bus reset signals to Multibus buses to state carry circuit and sequential processing circuit；
State carry circuit, as the work clock of state machine, shape is carried out by synchronous finite state-machine using isa bus clock
State transfer processing, output timing control signal to sequential process circuit；
The timing control signal that sequential processing circuit is provided according to state carry circuit carries out sequential processing to the buses of ISA tri-, real
Timing conversion of the existing buses of ISA tri- to the read-write operation of the buses of Multibus tri-；
Interrupt circuit receives Multibus bus interrupt signals from Multibus buses, and output isa bus interrupt signal is total to ISA
Line, realizes the transfer processing of interrupt signal；
Reset circuit realizes isa bus reset signal to the conversion of Multibus bus reset signals, and provides state transfer electricity
The general reset signal that road and sequential processing circuit are used.
2. isa bus according to claim 1 is to the read-write operation change-over circuit of Multibus buses, it is characterised in that：
The signal that state carry circuit is connected with the buses of ISA tri- includes isa bus clock isa_bclk, isa bus memory and reads isa_
Memr, isa bus memory write isa_memw, isa bus I/O reading isa_ior, isa bus I/O and write isa_iow；State is shifted
The signal that circuit is connected with the buses of Multibus tri- is that M bus transfers confirm m_xack, and state carry circuit is output at sequential
The timing control signal of reason circuit includes：Isa bus reads isa_rd, isa bus and writes isa_wt, isa bus read/write isa_rd_
Wt, count signal isa_ws_cnt, status signal IDLE, RD_WT, BT_END；The reset signal of state carry circuit be from
The general reset rst of reset circuit；
State carry circuit includes first and is equal to comparator [E01], second equal to comparator [E02], the 3rd equal to comparator
[E03], the 4th be equal to comparator [E04], the 5th be equal to comparator [E05], the first OR gate [OR01], the second OR gate [OR02],
3rd OR gate [OR03], the first multiplexer [M01], the second multiplexer [M02], the first d type flip flop [D01], first
State machine module [U01]；
High level, unequal output low level, above-mentioned are exported during above-mentioned A inputs and equal B inputs equal to comparator
One multiplexer [M01] is alternative multiplexer, and the second multiplexer [M02] selects a multiplexer for four；Alternative is multiplexed
D0 inputs are connected with Q output when the S selections end of device is low level, D1 when the S selections end of alternative multiplexer is high level
Input is connected with Q output；Four select [S1, the S2] of a multiplexer when to select end be 2 ' b00, and D0 inputs and Q output connect
Logical, D1 inputs are connected with Q output when [S1, S2] selection end is 2 ' b01, D2 inputs when [S1, S2] selection end is 2 ' b10
Connected with Q output, D3 inputs are connected with Q output when [S1, S2] selection end is 2 ' b11；First is equal to comparator
[E01], second be equal to comparator [E02], the 3rd be equal to comparator [E03], the 4th be equal to comparator [E04], the 5th be equal to than
Input compared with device [E05] is 4 bit widths, data terminal, the second multiplexer [M02] of the first multiplexer [M01]
Data terminal, the data terminal of the first d type flip flop [D01], the 5th be equal to comparator [E05] input be 2 bit widths, first
OR gate [OR01], the second OR gate [OR02], the external interface of the 3rd OR gate [OR03] and first state machine module [U01] are
1 bit width；
First be equal to comparator [E01], second be equal to comparator [E02], the 3rd be equal to comparator [E03], the 4th be equal to compare
The A inputs of device [E04] are connected, and isa bus I/O is consecutively connected to from a high position to low level and writes isa_iow, isa bus memory
Write isa_memw, isa bus I/O and read isa_ior, isa bus memory reading isa_memr；First is equal to the B of comparator [E01]
Input is connected to the hE of level state 4 ' from a high position to low level, and second is equal to the B inputs of comparator [E02] from a high position to low level
The hD of level state 4 ' is connected to, the 3rd B inputs for being equal to comparator [E03] are connected to level state 4 ' from a high position to low level
HB, the 4th B inputs for being equal to comparator [E04] are connected to the h7 of level state 4 ' from a high position to low level；First is equal to comparator
The OUT output ends of [E01] are connected to the first OR gate [OR01] input 1, and the second OUT output ends for being equal to comparator [E02] connect
The first OR gate [OR01] input 2 is connected to, the output end signal of the first OR gate [OR01] is read isa_rd for isa bus, is connected to
The input 1 of 3rd OR gate [OR03] is simultaneously output to sequential processing circuit, and the 3rd OUT output ends for being equal to comparator [E03] connect
The second OR gate [OR02] input 1 is connected to, the 4th OUT output ends for being equal to comparator [E04] are connected to the second OR gate [OR02]
Input 2, the output end signal of the second OR gate [OR02] writes isa_wt for isa bus, is connected to the defeated of the 3rd OR gate [OR03]
Enter end 2 and be output to sequential processing circuit, the output end signal of the 3rd OR gate [OR03] is isa bus read/write isa_rd_wt,
It is connected to the T1 inputs of first state machine module [U01] and is output to sequential processing single channel；
The D1 inputs of first multiplexer [M01] are connected to the b11 of level state 2 ', the first multiplexer from high to low
The anti-phase S selections end of [M01] is connected to external signal M bus transfers and confirms m_xack, and the Q of the first multiplexer [M01] is defeated
Go out the D2 inputs that end is connected to the second multiplexer [M02], the D0 inputs of the second multiplexer [M02] from a high position to
Low level is connected to the b01 of level state 2 ', and the D1 inputs of the second multiplexer [M02] are connected to level shape from a high position to low level
The b10 of state 2 ', the D3 inputs of the second multiplexer [M02] are connected to the b00 of level state 2 ', the second multichannel from a high position to low level
The Q output of multiplexer [M02] is connected to the D inputs of the first d type flip flop [D01], the clock end of the first d type flip flop [D01]
Isa bus clock isa_bclk is connected to, the EN Enable Pins of the first d type flip flop [D01] are connected to status signal RD_WT, the first D
The CLR reset terminals of trigger [D01] are connected to general reset rst, and the Q output of the first d type flip flop [D01] is count signal isa_
Ws_cnt, [S1, S2] selection end of D0 inputs, the second multiplexer [M02] with the first multiplexer [M01], the
The five A inputs for being equal to comparator [E05] are connected, and are output to sequential processing circuit, and the 5th is defeated equal to the B of comparator [E05]
Enter end and the b11 of level state 2 ' is connected to from a high position to low level, the 5th OUT output ends for being equal to comparator [E05] are connected to first
The T2 inputs of state machine module [U01]；The CLK clocks end of first state machine module [U01] is connected to isa bus clock isa_
Bclk, the CLR reset terminals of first state machine module [U01] are connected to general reset rst, the state of first state machine module [U01]
Output end signal includes status signal IDLE, RD_WT, BT_END, is respectively outputted to sequential processing circuit；
The first state machine module [U01] is used as state machine work clock, first state using isa bus clock isa_bclk
The state jump condition of machine module [U01] includes T1 and T2, and effective status includes state1, state2, state3, corresponded to respectively
Status signal IDLE, RD_WT, BT_END, system is in state1 states when general reset rst is effective, and status signal IDLE is effective,
Under the normal running conditions that general reset rst is cancelled, when T1 is invalid, state machine is in state1 states, when T1 is effective, shape
State machine is transferred to state2 states, and effectively, when T2 is invalid, state machine is in state2 states to status signal RD_WT, when T2 has
During effect, state machine is transferred to state3 states, and effectively, state3 states stop an isa bus clock to status signal BT_END
Afterwards, state1 states are transferred to, the state transfer operation of a state machine is completed.
3. isa bus according to claim 1 is to the read-write operation change-over circuit of Multibus buses, it is characterised in that：
The signal that sequential processing circuit is connected with the buses of ISA tri- includes isa bus memory reading isa_memr, isa bus memory and write
Isa_memw, isa bus I/O read isa_ior, isa bus I/O and write isa_iow, isa bus address isa_addr, isa bus
Data isa_dat, the ready isa_chrdy of isa bus slave unit, the output letter for the state carry circuit that sequential processing circuit is received
Number include isa bus and read isa_rd, isa bus writing isa_wt, isa bus read/write isa_rd_wt, count signal isa_ws_
Cnt, status signal IDLE, RD_WT, BT_END, the signal that sequential processing circuit is connected with the buses of Multibus tri- include M buses
Memory reads m_mrdc, and low effectively, M bus drivers write m_mwtc, M bus I/O readings m_iorc, M bus I/O and write m_iowc, M
Bus address m_addr, M bus data m_dat, M bus transfer confirm m_xack, and the reset signal of sequential processing circuit comes from
The general reset rst of reset circuit；
Sequential processing circuit includes address conversion circuit, read write command change-over circuit, data and writes change-over circuit, data reading conversion electricity
Road, feedback circuit；Address conversion circuit, read write command change-over circuit, data write change-over circuit, data and read change-over circuit, feedback
Circuit, as work clock, reset signal is used as using general reset rst using isa bus clock isa_bclk；
Address conversion circuit is used for the read-write sequence conversion for realizing isa bus address isa_addr to M bus address m_addr, defeated
The timing control signal entered includes isa bus read/write isa_rd_wt, status signal IDLE, RD_WT, BT_END；
Read write command change-over circuit is used to realize the order of isa bus read-write operation to the read-write sequence of M bus read-write operation orders
Conversion, the wherein order of isa bus read-write operation include isa bus memory reading isa_memr, isa bus memory and write isa_
Memw, isa bus I/O read isa_ior, I/O bus I/O and write isa_iow, and the order of M bus read-write operations includes M bus drivers
Reading m_mrdc, M bus driver writes m_mwtc, M bus I/O readings m_iorc, M bus I/O and writes m_iowc, the SECO of input
Signal includes count signal isa_ws_cnt, status signal RD_WT；
Data write the write operation timing conversion that change-over circuit is used to realize isa bus data isa_dat to M bus datas m_dat,
The timing control signal of input includes isa bus reading isa_rd, isa bus and writes isa_wt, status signal IDLE, RD_WT, BT_
END；
Data, which read change-over circuit, to be used to realize M bus datas m_dat to isa bus data isa_dat read operation timing conversion,
The timing control signal of input includes isa bus reading isa_rd, isa bus and writes isa_wt, count signal isa_ws_cnt, state
Signal IDLE, RD_WT, BT_END, the feedback signal of input confirm m_xack for M bus transfers；
Feedback circuit is used for the feedback signal for realizing that M bus transfers confirm m_xack to the ready isa_chrdy of isa bus slave unit
Timing conversion, the timing control signal of input includes count signal isa_ws_cnt, status signal RD_WT；
The address conversion circuit includes first selector [S01], the second d type flip flop [D02], 3d flip-flop [D03], the
One triple gate [T01]；First selector [S01] be No. three selectors, when only S0 selection end be high level when, D0 inputs with
OUT output ends are connected, and when only S1 selections end is high level, D1 inputs are connected with OUT output ends, when only S2 selects end
During for high level, D2 inputs are gated with OUT output ends；First selector [S01], the data terminal of the second d type flip flop [D02] are
1 bit width, 3d flip-flop [D03], the data terminal corresponding address bus of the first triple gate [T01], data width can be according to reality
Border application adjustment, is defaulted as 20 bit widths；
The D0 inputs of first selector [S01] are connected to high level, and the D1 inputs of first selector [S01] are connected to low electricity
Flat, the D2 inputs of first selector [S01] are connected to isa bus read/write isa_rd_wt, the S0 choosings of first selector [S01]
Select end and be connected to status signal BT_END, the S1 selections end of first selector [S01] is connected to status signal RD_WT, the first choosing
The S2 selections end for selecting device [S01] is connected to status signal IDLE, OUT output ends and the second d type flip flop of first selector [S01]
The EN Enable Pins of [D02], the EN Enable Pins of 3d flip-flop [D03] are connected, the anti-phase D inputs of the second d type flip flop [D02]
Status signal BT_END is connected to, the Q output of the second d type flip flop [D02] is connected to the ENB enables of the first triple gate [T01]
End, the D inputs of 3d flip-flop [D03] are connected to isa bus address isa_addr, the Q outputs of 3d flip-flop [D03]
End is connected to the first triple gate [T01] input, and the second d type flip flop [D02], the clock end of 3d flip-flop [D03] connect
Isa bus clock isa_bclk is connected to, the second d type flip flop [D02], the CLR reset terminals of 3d flip-flop [D03] are all connected to
General reset rst, the output end of the first triple gate [T01] is connected to M bus address m_addr；
The read write command change-over circuit includes the 3rd multiplexer [M03], four d flip-flop [D04]；3rd multiplexing
Device [M03] selects a multiplexer for four, and the 3rd multiplexer [M03], four d flip-flop [D04] data terminal are 4 bit widths；
The D0 inputs of 3rd multiplexer [M03] are sequentially connected isa bus I/O from a high position to low level and write isa_iow, ISA
Bus driver writes isa_memw, isa bus I/O and reads isa_ior, isa bus memory reading isa_memr, the 3rd multiplexing
The D1 inputs position corresponding with D2 inputs of device [M03] is connected, and position corresponding with the Q output of four d flip-flop [D04] connects
Connect, the D3 inputs of the 3rd multiplexer [M03] are connected to the hF of level state 4 ', the 3rd multiplexer from a high position to low level
[S1, S2] selection end of [M03] is connected to count signal isa_ws_cnt, the Q output connection of the 3rd multiplexer [M03]
To the D inputs of four d flip-flop [D04], the clock end of four d flip-flop [D04] is connected to isa bus clock isa_
Bclk, the EN Enable Pins of four d flip-flop [D04] are connected to status signal RD_WT, the SET set of four d flip-flop [D04]
End is connected to general reset rst, and the Q output of four d flip-flop [D04] is consecutively connected to M buses I/O from a high position to low level and writes m_
Iowc, M bus driver write m_mwtc, M bus I/O and read m_iorc, M bus driver reading m_mrdc；
The data are write change-over circuit and answered including the 4th multiplexer [M04], the 5th multiplexer [M05], the 6th multichannel
With device [M06], second selector [S02], the 5th d type flip flop [D05], the 6th d type flip flop [D06], the second triple gate [T02]；
4th multiplexer [M04], the 5th multiplexer [M05], the 6th multiplexer [M06] are alternative multiplexer,
Second selector [S02] is No. three selectors, the 4th multiplexer [M04], the 5th multiplexer [M05], the second selection
Device [S02], the data terminal of the 5th d type flip flop [D05] are 1 bit width, the 6th multiplexer [M06], the 6th d type flip flop
The data terminal corresponding data bus of [D06], the second triple gate [T02], data width is 8 or 16, can be answered according to actual
With adjustment；
The D0 inputs of 4th multiplexer [M04] and the D1 inputs of second selector [S02], the 5th d type flip flop [D05]
Q output, the second triple gate [T02] ENB Enable Pins be connected, the D1 inputs of the 4th multiplexer [M04] are connected to
High level, the S selections end of the 4th multiplexer [M04] is connected to isa bus and writes isa_wt, the 4th multiplexer [M04]
Q output be connected to the D0 inputs of the 5th multiplexer [M05], the D1 inputs of the 5th multiplexer [M05] connect
Low level is connected to, the S selections end of the 5th multiplexer [M05] is connected to isa bus and reads isa_rd, the 5th multiplexer
The Q output of [M05] is connected to the D2 inputs of second selector [S02], and the D0 inputs of second selector [S02] are connected to
Low level, the S0 selections end of second selector [S02] is connected to status signal BT_END, the S1 selections of second selector [S02]
End is connected to status signal RD_WT, and the S2 selections end of second selector [S02] is connected to status signal IDLE, second selector
The OUT output ends of [S02] are connected to the clock end connection of the D inputs of the 5th d type flip flop [D05], the 5th d type flip flop [D05]
To isa bus clock isa_bclk, the CLR reset terminals of the 5th d type flip flop [D05] are connected to general reset rst；
The D0 inputs of 6th multiplexer [M06] and Q output, the second triple gate [T02] of the 6th d type flip flop [D06]
Input be connected, the D1 inputs of the 6th multiplexer [M06] are connected to isa bus data isa_dat, and the 6th multichannel is answered
Isa bus is connected to the S of device [M06] selection end and writes isa_wt, the Q output of the 6th multiplexer [M06] is connected to the
The D inputs of six d type flip flops [D06], the clock end of the 6th d type flip flop [D06] is connected to isa bus clock isa_bclk, the
The EN Enable Pins of six d type flip flops [D06] are connected to status signal IDLE, and the CLR reset terminals of the 6th d type flip flop [D06] are connected to
General reset rst, the output end of the second triple gate [T02] is connected to M bus datas m_dat；
The data are read change-over circuit and answered including the 7th multiplexer [M07], the 8th multiplexer [M08], the 9th multichannel
It is equal to device [M09], the tenth multiplexer [M10], the 11st multiplexer [M11], third selector [S03], the 6th
Comparator [E06], the 7th d type flip flop [D07], the 8th d type flip flop [D08], the 3rd triple gate [T03]；7th multiplexer
[M07], the 8th multiplexer [M08], third selector [S03], the data terminal of the 7th d type flip flop [D07] are 1 bit wide
Degree, the 6th input for being equal to comparator [E06] is 2 bit widths, the 9th multiplexer [M09], the tenth multiplexer
[M10], the 11st multiplexer [M11], the 8th d type flip flop [D08], the data terminal corresponding data of the 3rd triple gate [T03]
Bus, data width is 8 or 16, can be adjusted according to practical application；
The D0 inputs of 7th multiplexer [M07] and the D1 inputs of third selector [S03], the 7th d type flip flop [D07]
Q output, the 3rd triple gate [T03] ENB Enable Pins be connected, the D1 inputs of the 7th multiplexer [M07] are connected to
Low level, the S selections end of the 7th multiplexer [M07] is connected to isa bus and writes isa_wt, the 7th multiplexer [M07]
Q output be connected to the D0 inputs of the 8th multiplexer [M08], the D1 inputs of the 8th multiplexer [M08] connect
High level is connected to, the S selections end of the 8th multiplexer [M08] is connected to isa bus and reads isa_rd, the 8th multiplexer
The Q output of [M08] is connected to the D2 inputs of third selector [S03], and the D0 inputs of third selector [S03] are connected to
Low level, the S0 selections end of third selector [S03] is connected to status signal BT_END, the S1 selections of third selector [S03]
End is connected to status signal RD_WT, and the S2 selections end of third selector [S03] is connected to status signal IDLE, third selector
The OUT output ends of [S03] are connected to the D inputs of the 7th d type flip flop [D07], the clock end connection of the 7th d type flip flop [D07]
To isa bus clock isa_bclk, the CLR reset terminals of the 7th d type flip flop [D07] are connected to general reset rst；
The D0 inputs of 9th multiplexer [M09] and the D0 inputs of the tenth multiplexer [M10], the 11st multichannel are multiple
It is connected with the input of the D0 inputs of device [M11], the Q output of the 8th d type flip flop [D08], the 3rd triple gate [T03], the
The D1 inputs of nine multiplexers [M09] are connected to M bus datas m_dat, the S selections end of the 9th multiplexer [M09]
It is connected to isa bus and reads isa_rd, the Q output of the 9th multiplexer [M09] is connected to the tenth multiplexer [M10]
D1 inputs, the anti-phase S selections end of the tenth multiplexer [M10] is connected to M bus transfers and confirms m_xack, and the tenth multichannel is answered
The D1 inputs of the 11st multiplexer [M11] are connected to the Q output of device [M10], the 6th is equal to comparator [E06]
A inputs are connected to count signal isa_ws_cnt, and the 6th B inputs for being equal to comparator [E06] are connected to electricity from high to low
The b10 of level state 2 ', the 6th OUT output ends for being equal to comparator [E06] are connected to the S selections of the 11st multiplexer [M11]
End, the Q output of the 11st multiplexer [M11] is connected to the D inputs of the 8th d type flip flop [D08], the 8th d type flip flop
The clock end of [D08] is connected to isa bus clock isa_bclk, and the EN Enable Pins of the 8th d type flip flop [D08] are connected to state letter
Number RD_WT, the CLR reset terminals of the 8th d type flip flop [D08] are connected to general reset rst, and the output end of the 3rd triple gate [T03] connects
It is connected to isa bus data isa_dat；
The feedback circuit includes the 12nd multiplexer [M12], the 13rd multiplexer [M13], the 9th d type flip flop
[D09]；12nd multiplexer [M12] selects a multiplexer for four, and the 13rd multiplexer [M13] is that alternative is multiplexed
Device, the 12nd multiplexer [M12], the 13rd multiplexer [M13], the data terminal of the 9th d type flip flop [D09] are 1
Bit width；
The D0 inputs of 12nd multiplexer [M12] and the D2 inputs of the 12nd multiplexer [M12], the 9th D are touched
The Q output of device [D09], the S selections end of the 13rd multiplexer [M13] is sent out to be connected, the 12nd multiplexer [M12]
D1 inputs are connected to high level, and the D3 inputs of the 12nd multiplexer [M12] are connected to low level, and the 12nd multichannel is answered
Count signal isa_ws_cnt, the Q outputs of the 12nd multiplexer [M12] are connected to [S1, S2] selection end of device [M12]
End is connected to the D inputs of the 9th d type flip flop [D09], and the clock end of the 9th d type flip flop [D09] is connected to isa bus clock
Isa_bclk, the EN Enable Pins of the 9th d type flip flop [D09] are connected to status signal RD_WT, the CLR of the 9th d type flip flop [D09]
Reset terminal is connected to general reset rst, and the D0 inputs of the 13rd multiplexer [M13] are connected to high level, the 13rd multichannel
The anti-phase D1 inputs of multiplexer [M13] are connected to M bus transfers and confirm m_xack, and the Q of the 13rd multiplexer [M13] is defeated
Go out end and be connected to the ready isa_chrdy of isa bus slave unit.
4. isa bus according to claim 1 is to the read-write operation change-over circuit of Multibus buses, it is characterised in that：
Reset circuit receives isa bus and resets isa_resetdrv and system reset sys_rst, exports M bus reset m_init, and defeated
Go out general reset rst to state carry circuit and sequential processing circuit；
Reset circuit includes the 4th OR gate [OR04], the first NOT gate [N01]；4th OR gate [OR04], the first NOT gate [N01] port
It is 1 bit width, the inverting input 1 of the 4th OR gate [OR04] is connected to system reset sys_rst, the 4th OR gate [OR04]
The input of the NOT gate [N01] of input 2 and first is connected to isa bus and resets isa_resetdrv, the 4th OR gate [OR04]
Output end is connected to general reset rst, and the output end of the first NOT gate [N01] is connected to M bus resets m_init.
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| Multibus总线到ISA总线的接口设计;姚吉文;《情报指挥控制系统与仿真技术》;20011231(第12期);全文 * |
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Effective date of registration: 20171208 Address after: 222001 Jiangsu Province, Lianyungang city Sinpo District Lake Road No. 18 Co-patentee after: JIANGSU JARI TECHNOLOGY GROUP Co.,Ltd. Patentee after: 716TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. Address before: 222061 Jiangsu city of Lianyungang Province Lake Road No. 18 Patentee before: JIANGSU JARI TECHNOLOGY GROUP Co.,Ltd. |
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Address after: 222001 No. 18, Shenghu Road, Xinpu District, Lianyungang City, Jiangsu Province Patentee after: The 716th Research Institute of China Shipbuilding Corp. Patentee after: JIANGSU JARI TECHNOLOGY GROUP Co.,Ltd. Address before: 222001 No. 18, Shenghu Road, Xinpu District, Lianyungang City, Jiangsu Province Patentee before: 716TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. Patentee before: JIANGSU JARI TECHNOLOGY GROUP Co.,Ltd. |