CN104572558A - ISA bus-to-Multibus bus read-write operation switching circuit - Google Patents

Abstract

The invention discloses an ISA bus-to-Multibus bus read-write operation switching circuit. The ISA bus-to-Multibus bus read-write operation switching circuit switches the synchronous read-write operation of the ISA bus into the asynchronous read-write operation of the Multibus bus to realize the read-write operation of ISA bus main equipment for Multibus bus slave equipment. The ISA bus-to-Multibus bus read-write operation switching circuit is simple in structure and supports 8-bit and 16-bit data width, an address wire can be extended according to user requirements, and the address wire can be used for designing a hybrid bus computer system. The ISA bus-to-Multibus bus read-write operation switching circuit realizes mixed insertion and compatibility for configuring the Multibus bus slave equipment on an ISA bus case and has broad application in the hybrid bus reinforced computer design field, computer bus board card test diagnosis field and the like.

Description

A kind of isa bus is to the read-write operation change-over circuit of Multibus bus

Technical field

The invention belongs to ruggedized computer design field, particularly a kind of isa bus is to the read-write operation change-over circuit of Multibus bus.

Background technology

PCI/CPCI, Multibus, ISA are ruggedized computer main flow device bus, general computer system adopts single computer bus, form Series Design, as pci bus computer, cpci bus computer, Multibus bus computer, isa bus computer, configuration module generally comprises computer primary module, A/D module and 232 serial port module, special functional module etc. from equipment.In ruggedized computer design, for improving system reliability, wish to adopt in new system to have identified mature modules or equipment as far as possible, the Multibus bus identified as used in isa bus computer, from module (A/D module, 232 serial port module, special functional module etc.), forms trunk mixed computer system.But, there is no ripe isa bus in prior art to the read-write operation change-over circuit module of Multibus bus, the mixed insertion and compatibling problem that isa bus cabinet configure Multibus bus slave cannot be solved.

Summary of the invention

The object of the present invention is to provide a kind of isa bus to the read-write operation change-over circuit of Multibus bus.

The technical solution realizing the object of the invention is: a kind of isa bus, to the read-write operation change-over circuit of Multibus bus, comprises state transitions circuit, sequential processing circuit, reset circuit, interrupt circuit; Core ISA tri-bus (control bus, address bus, data/address bus) of isa bus is connected with sequential processing circuit with state transitions circuit, isa bus reset signal is connected with reset circuit, isa bus interrupt signal is connected with interrupt circuit, and state transitions circuit output timing control signal is to sequential treatment circuit; Core Multibus tri-bus of Multibus bus is connected with sequential processing circuit with state transitions circuit, Multibus bus reset signal is connected with reset circuit, Multibus bus interrupt signal is connected with interrupt circuit, reset circuit exports general reset signal to state transitions circuit and sequential processing circuit, and reset circuit is also connected with system reset.

State transitions circuit adopts isa bus clock as the work clock of state machine, and according to the control signal that isa bus and Multibus bus input, carry out state transitions process by synchronous finite state-machine, output timing control signal is to sequential treatment circuit.

The timing control signal that sequential processing circuit provides according to state transitions circuit carries out sequential processing to ISA tri-bus, realizes the timing conversion of ISA tri-bus to the read-write operation of Multibus tri-bus.

Interrupt circuit receives Multibus bus interrupt signal from Multibus bus, exports isa bus interrupt signal to isa bus, realizes the transfer process of interrupt signal.

Reset circuit realizes the conversion of isa bus reset signal to Multibus bus reset signal, and provides the general reset signal that state transitions circuit and sequential processing circuit use.

In the present invention, Multibus bus is called for short M bus.

Compared with prior art, its remarkable advantage is in the present invention: 1) circuit structure of the present invention is simple, and support 8 and 16 bit data width, address wire can be expanded as required; 2) this circuit conversion efficiency is high, and frequency adaptability is strong, may be used for the isa bus clock ranges of 7MHz ~ 10MHz; 3) this circuit highly versatile, can realize, take resource few on general CPLD/FPGA logic chip, low in energy consumption; 4) this circuit is changed by the read-write sequence of isa bus to Multibus bus, achieves on isa bus cabinet, configure Multibus bus slave mixed insertion and compatibility; 5) in field tests, based on the test macro of isa bus, except direct test I SA bus module, if adopt circuit of the present invention, can extend testing Multibus bus from module, and then improve system testing ability.

Below in conjunction with accompanying drawing, the present invention is described in further detail.

Accompanying drawing explanation

Fig. 1 is the composition frame chart of isa bus of the present invention to the read-write operation change-over circuit of Multibus bus.

Fig. 2 is the external signal connection layout of state transitions circuit of the present invention.

Fig. 3 is that the external signal of sequential processing circuit of the present invention connects and composition frame chart.

Fig. 4 is the circuit block diagram of state transitions circuit of the present invention.

Fig. 5 is the state transition diagram of state machine of the present invention.

Fig. 6 is the circuit block diagram of address conversion circuit of the present invention.

Fig. 7 is the circuit block diagram of read write command change-over circuit of the present invention.

Fig. 8 is the circuit block diagram that data of the present invention write change-over circuit.

Fig. 9 is the circuit block diagram that data of the present invention read change-over circuit.

Figure 10 is the circuit block diagram of feedback circuit of the present invention.

Figure 11 is the circuit block diagram of reset circuit of the present invention.

Embodiment

The invention discloses the read-write operation change-over circuit of a kind of isa bus to Multibus bus, the synchronous read-write operation of isa bus is converted to the asynchronous read and write operation of Multibus bus, realize the read-write operation of isa bus main equipment to Multibus bus slave, solve the mixed insertion and compatibling problem that isa bus cabinet configure Multibus bus slave, be widely used in fields such as trunk mixed ruggedized computer design, computer bus board testing and diagnosings.

By reference to the accompanying drawings 1, the composition of isa bus of the present invention to the read-write operation change-over circuit of Multibus bus is described.

Isa bus, to a read-write operation change-over circuit for Multibus bus, comprises state transitions circuit, sequential processing circuit, reset circuit, interrupt circuit; Core ISA tri-bus (control bus, address bus, data/address bus) of isa bus is connected with sequential processing circuit with state transitions circuit, isa bus reset signal is connected with reset circuit, isa bus interrupt signal is connected with interrupt circuit, and state transitions circuit output timing control signal is to sequential treatment circuit; Core Multibus tri-bus of Multibus bus is connected with sequential processing circuit with state transitions circuit, Multibus bus reset signal is connected with reset circuit, Multibus bus interrupt signal is connected with interrupt circuit, reset circuit exports general reset signal to state transitions circuit and sequential processing circuit, and exports Mulitbus bus reset signal to Multibus bus; Reset circuit is also connected with system reset.

State transitions circuit adopts isa bus clock as the work clock of state machine, and according to the control signal that isa bus and Multibus bus input, carry out state transitions process by synchronous finite state-machine, output timing control signal is to sequential treatment circuit.

The timing control signal that sequential processing circuit provides according to state transitions circuit carries out sequential processing to ISA tri-bus, realizes the timing conversion of ISA tri-bus to the read-write operation of Multibus tri-bus.

Interrupt circuit receives Multibus bus interrupt signal from Multibus bus, exports isa bus interrupt signal to isa bus, realizes the transfer process of interrupt signal.

Reset circuit realizes the conversion of isa bus reset signal to Multibus bus reset signal, and provides the general reset signal that state transitions circuit and sequential processing circuit use.

In the present invention, the signal identification of same names represents same electrical connection, and Multibus bus is called for short M bus.

By reference to the accompanying drawings 1, accompanying drawing 2, accompanying drawing 4 and accompanying drawing 5, the outside of description status carry circuit connects, composition and operation principle.

The signal that state transitions circuit is connected with ISA tri-bus comprises isa bus clock (isa_bclk), (isa_memr read by isa bus memory, low effectively), isa bus memory writes (isa_memw, low effectively), isa bus I/O reads (isa_ior, low effectively), isa bus I/O writes (isa_iow, low effectively); The signal that state transitions circuit is connected with Multibus tri-bus is that M bus transfer confirms (m_xack, low effectively), the timing control signal that state transitions circuit outputs to sequential processing circuit comprises: isa bus is read (isa_rd, high effectively), isa bus writes (isa_wt, high effectively), isa bus read/write (isa_rd_wt, effectively high), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END (effectively high); The reset signal of state transitions circuit is carry out the general reset of self-resetting circuit (rst, effectively high);

State transitions circuit comprises first and equals comparator [E01], second and equal comparator [E02], the 3rd and equal comparator [E03], the 4th and equal comparator [E04], the 5th and equal comparator [E05], first or door [OR01], second or door [OR02], the 3rd or door [OR03], the first multiplexer [M01], the second multiplexer [M02], the first d type flip flop [D01], the first state machine module [U01];

The above-mentioned A input equaling comparator exports high level, unequal output low level time equal with B input.Above-mentioned first multiplexer [M01] is alternative multiplexer, and the second multiplexer [M02] is four select a multiplexer, when the S selecting side of alternative multiplexer is low level, D0 input is communicated with Q output, and when the S selecting side of alternative multiplexer is high level, D1 input is connected with Q output, four [the S1 selecting a multiplexer, S2] selecting side when being 2 ' b00 D0 input be communicated with Q output, [S1, S2] selecting side when being 2 ' b01 D1 input be communicated with Q output, [S1, S2] selecting side when being 2 ' b10 D2 input be communicated with Q output, when [S1, S2] selecting side is 2 ' b11, D3 input is communicated with Q output, first equals comparator [E01], second equals comparator [E02], 3rd equals comparator [E03], 4th equals comparator [E04], 5th input equaling comparator [E05] is 4 bit widths, the data terminal of the first multiplexer [M01], the data terminal of the second multiplexer [M02], the data terminal of the first d type flip flop [D01], 5th input equaling comparator [E05] is 2 bit widths, first or door [OR01], second or door [OR02], 3rd or the external interface of door [OR03] and the first state machine module [U01] be 1 bit width,

First equals comparator [E01], second equals comparator [E02], the 3rd and equals the A input that comparator [E03], the 4th equals comparator [E04] and be connected, and is connected to that isa bus I/O writes isa_iow, isa_memw write by isa bus memory, isa bus I/O reads isa_ior, isa_memr read by isa bus memory from a high position to low level successively, the first B input equaling comparator [E01] is connected to level state 4 ' hE from a high position to low level, the second B input equaling comparator [E02] is connected to level state 4 ' hD from a high position to low level, the 3rd B input equaling comparator [E03] is connected to level state 4 ' hB from a high position to low level, and the 4th B input equaling comparator [E04] is connected to level state 4 ' h7 from a high position to low level, the first OUT output equaling comparator [E01] is connected to first or door [OR01] input 1, the second OUT output equaling comparator [E02] is connected to first or door [OR01] input 2, first or the output end signal of door [OR01] be that isa bus reads (isa_rd, be connected to the input 1 of the 3rd or door [OR03] and output to sequential processing circuit, the 3rd OUT output equaling comparator [E03] is connected to second or door [OR02] input 1, the 4th OUT output equaling comparator [E04] is connected to second or door [OR02] input 2, second or the output end signal of door [OR02] be that isa bus is write (isa_wt), be connected to the input 2 of the 3rd or door [OR03] and output to sequential processing circuit, 3rd or the output end signal of door [OR03] be isa bus read/write (isa_rd_wt), be connected to the T1 input of the first state machine module [U01] and output to sequential processing single channel,

The D1 input of the first multiplexer [M01] is connected to level state 2 ' b11 from high to low, the anti-phase S selecting side of the first multiplexer [M01] is connected to external signal M bus transfer and confirms m_xack, the Q output of the first multiplexer [M01] is connected to the D2 input of the second multiplexer [M02], the D0 input of the second multiplexer [M02] is connected to level state 2 ' b01 from a high position to low level, the D1 input of the second multiplexer [M02] is connected to level state 2 ' b10 from a high position to low level, the D3 input of the second multiplexer [M02] is connected to level state 2 ' b00 from a high position to low level, the Q output of the second multiplexer [M02] is connected to the D input of the first d type flip flop [D01], the clock end of the first d type flip flop [D01] is connected to isa bus clock isa_bclk, the EN Enable Pin of the first d type flip flop [D01] is connected to status signal RD_WT, the CLR reset terminal of the first d type flip flop [D01] is connected to general reset rst, the Q output of the first d type flip flop [D01] is count signal isa_ws_cnt, with the D0 input of the first multiplexer [M01], [the S1 of the second multiplexer [M02], S2] selecting side, the 5th A input equaling comparator [E05] is connected, and output to sequential processing circuit, the 5th B input equaling comparator [E05] is connected to level state 2 ' b11 from a high position to low level, the 5th OUT output equaling comparator [E05] is connected to the T2 input of the first state machine module [U01], the CLK clock end of the first state machine module [U01] is connected to isa bus clock isa_bclk, the CLR reset terminal of the first state machine module [U01] is connected to general reset rst, the state output end signal of the first state machine module [U01] comprises status signal IDLE, RD_WT, BT_END, outputs to sequential processing circuit respectively.

Described first state machine module [U01] adopts isa bus clock isa_bclk as state machine work clock, the state transitions condition of the first state machine module [U01] comprises T1 and T2, effective status comprises state1, state2, state3, corresponding states signal IDLE respectively, RD_WT, BT_END (being high level effective), when general reset rst is effective, system is in state1 state, status signal IDLE is effective, under the normal running conditions that general reset rst cancels, when T1 is invalid (T1=0), state machine is in state1 state, when T1 is effective (T1=1), state machine transfers to state2 state, status signal RD_WT is effective, when T2 is invalid, state machine is in state2 state, when T2 is effective (T2=1), state machine transfers to state3 state, status signal BT_END is effective, after state3 state stops an isa bus clock (isa_clk), transfer to state1 state, complete the state transitions operation of a state machine.

State transitions main circuit wants the state transitions of completion status machine to control, when carrying out isa bus memory read operation, [isa_iow, isa_memw, isa_ior, isa_memr]=4 ' b1110=4 ' hE, when carrying out isa bus I/O read operation, [isa_iow, isa_memw, isa_ior, isa_memr]=4 ' b1101=4 ' hD, when carrying out isa bus memory write operation, [isa_iow, isa_memw, isa_ior, isa_memr]=4 ' b1011=4 ' hB, when carrying out isa bus I/O write operation, [isa_iow, isa_memw, isa_ior, isa_memr]=4 ' b0111=4 ' h7, therefore, first or the output end signal of door [OR01] be isa bus and read isa_rd, second or the output end signal of door [OR02] be isa bus and write isa_wt, the 3rd or the output end signal state transitions condition T1 of the first state machine module [U01] (also i.e.) of door [OR03] be isa bus read/write isa_rd_wt, when there is effective isa bus read command, isa_rd is effective, and when there is effective isa bus write order, isa_wt is effective, and when occurring that effective isa bus reads or writes order, isa_rd_wt is effective, and namely T1 is effective,

When general reset rst is effective, the Q output end signal of the first d type flip flop [D01] and count signal isa_ws_cnt are 2 ' b00, under state2 state, status signal RD_WT is effective, first d type flip flop [D01] and the second multiplexer [M02] form a controlled counter, and count signal isa_ws_cnt carries out adding 1 counting according to isa bus clock isa_bclk from 2 ' b00, when isa_ws_cnt is 2 ' b10, if M bus transfer confirms that m_xack effectively (low level), isa_ws_cnt normally adds 1 and becomes 2 ' b11, if M bus transfer confirms m_xack invalid (high level), isa_ws_cnt remains 2 ' b10 state, until M bus transfer confirms that m_xack effective (low level) adds 1 again and becomes 2 ' b11, after isa_ws_cnt becomes 2 ' b11, next isa bus clock isa_bclk adds 1 again and resets to 2 ' b00, when count signal isa_ws_cnt is 2 ' b11, the state transitions condition T2 of the first state machine module [U01] is effective,

The isa bus operation cycle (without inserting latent period) of standard is six isa bus clock cycle, possible insertion latent period is between the 5th isa bus operation cycle and the 6th isa bus operation cycle, even if occur inserting latent period, still this isa bus operation cycle of inserting after latent period was called for the 6th isa bus operation cycle herein; Isa_ws_cnt is 2 ' b10 corresponding 5th isa bus operation cycle and possible insertion latent period, and isa_ws_cnt is 2 ' the b11 corresponding 6th isa bus operation cycle;

The corresponding reset mode of the state1 state of state machine, bus idle state and first, second isa bus operation cycle, state2 state corresponding three to the five isa bus operation cycle of state machine, possible insertion latent period and the 6th isa bus operation cycle, state3 state last extra isa bus cycle corresponding of state machine;

Under reset or bus idle state, state machine is in state1 state, status signal IDLE is effective, when there is isa bus read or write order, state machine transfers to state2 state, status signal RD_WT is effective, under state2 state, count down to for the 5th isa bus operation cycle from the 3rd isa bus operation cycle, the 5th isa bus operation cycle, judge that whether effectively M bus transfer confirms m_xack (whether the read-write of M bus data completes), if m_xack is invalid, then enter latent period, if m_xack is effective, in the 6th isa bus operation cycle, state machine is from state2 state transitions to state3 state, status signal BT_END is effective, extra isa bus cycle is taken (for Multibus bus address under state3 state, data keep), directly jump to state1 state, terminate the operation of this state transitions.

By reference to the accompanying drawings 1, accompanying drawing 3 illustrate that the outside of the circuit of sequential processing circuit connects, comprising modules and major function.

The signal that sequential processing circuit is connected with ISA tri-bus comprises isa bus memory and reads (isa_memr, low effectively), isa bus memory is write (isa_memw, low effectively), isa bus I/O reads (isa_ior, low effectively), isa bus I/O writes (isa_iow, low effectively), isa bus address (isa_addr), isa bus data (isa_dat), isa bus is from device ready (isa_chrdy, effectively high), and the output signal of the state transitions circuit that sequential processing circuit receives comprises isa bus and reads (isa_rd, effectively high), isa bus is write (isa_wt, effectively high), isa bus read/write (isa_rd_wt, effectively high), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END (being effectively high), the signal that sequential processing circuit is connected with Multibus tri-bus comprises M bus driver and reads (m_mrdc, low effectively), M bus driver is write (m_mwtc, low effectively), M bus I/O reads (m_iorc, low effectively), M bus I/O writes (m_iowc, low effectively), M bus address (m_addr), M bus data (m_dat), M bus transfer confirms (m_xack, low effectively), and the reset signal of sequential processing circuit carrys out the general reset of self-resetting circuit (rst, effectively high),

Sequential processing circuit comprises address conversion circuit, read write command change-over circuit, data write change-over circuit, data read change-over circuit, feedback circuit.Address conversion circuit, read write command change-over circuit, data write change-over circuit, data read change-over circuit, feedback circuit all adopts isa bus clock (isa_bclk) as work clock, adopt general reset (rst) as reset signal.

Address conversion circuit is used for realizing isa bus address (isa_addr) to be changed to the read-write sequence of M bus address (m_addr), and the timing control signal of input comprises isa bus read/write (isa_rd_wt), status signal IDLE, RD_WT, BT_END;

Read write command change-over circuit is used for realizing the read-write sequence conversion of isa bus read-write operation order (isa_memr read by isa bus memory, isa_memw write by isa bus memory, isa bus I/O read isa_ior, I/O bus I/O and write isa_iow) to M bus read-write operation order (M bus driver read m_mrdc, M bus driver write m_mwtc, M bus I/O read m_iorc, M bus I/O and write m_iowc), and the timing control signal of input comprises count signal (isa_ws_cnt), status signal RD_WT;

Data write change-over circuit for realizing the write operation timing conversion of isa bus data (isa_dat) to M bus data (m_dat), and the timing control signal of input comprises that isa bus reads (isa_rd), isa bus writes (isa_wt), status signal IDLE, RD_WT, BT_END;

Data read the read operation timing conversion of change-over circuit for the M bus data (m_dat) to isa bus data (isa_dat) that realize read operation, the timing control signal of input comprises that isa bus reads (isa_rd), isa bus writes (isa_wt), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END, and the feedback signal of input is that M bus transfer confirms (m_xack);

Feedback circuit is used for realizing M bus transfer and confirms (m_xack) timing conversion to isa bus from the feedback signal of device ready (isa_chrdy), and the timing control signal of input comprises count signal (isa_ws_cnt), status signal RD_WT.

By reference to the accompanying drawings 6, composition and the operation principle of address conversion circuit are described.

Described address conversion circuit comprises first selector [S01], the second d type flip flop [D02], 3d flip-flop [D03], the first triple gate [T01]; First selector [S01] is No. three selectors, when being high level when only having S0 selecting side, D0 input is communicated with OUT output, when being high level when only having S1 selecting side, D1 input is communicated with OUT output, when being high level when only having S2 selecting side, D2 input and OUT output gating; The data terminal of first selector [S01], the second d type flip flop [D02] is 1 bit width, the data terminal corresponding address bus of 3d flip-flop [D03], the first triple gate [T01], data width can adjust according to practical application, is defaulted as 20 bit widths;

The D0 input of first selector [S01] is connected to high level, the D1 input of first selector [S01] is connected to low level, the D2 input of first selector [S01] is connected to isa bus read/write isa_rd_wt, the S0 selecting side of first selector [S01] is connected to status signal BT_END, the S1 selecting side of first selector [S01] is connected to status signal RD_WT, the S2 selecting side of first selector [S01] is connected to status signal IDLE, the OUT output of first selector [S01] and the EN Enable Pin of the second d type flip flop [D02], the EN Enable Pin of 3d flip-flop [D03] is connected, the anti-phase D input of the second d type flip flop [D02] is connected to status signal BT_END, the Q output of the second d type flip flop [D02] is connected to the ENB Enable Pin of the first triple gate [T01], the D input of 3d flip-flop [D03] is connected to isa bus address isa_addr, the Q output of 3d flip-flop [D03] is connected to the input of the first triple gate [T01], second d type flip flop [D02], the clock end of 3d flip-flop [D03] is all connected to isa bus clock isa_bclk, second d type flip flop [D02], the CLR reset terminal of 3d flip-flop [D03] is all connected to general reset rst, the output of the first triple gate [T01] is connected to M bus address m_addr.

In state1 state, status signal IDLE is effective, the OUT output of first selector [S01] is communicated with D2 input, if there is isa bus read-write operation, effectively (high level), the EN Enable Pin of the second d type flip flop [D02], 3d flip-flop [03] is high level to isa_rd_wt, and the ENB Enable Pin of the first triple gate [T01] is high level, first triple gate [T01] conducting, isa bus address isa_addr outputs to M bus address m_addr; In state2 state, status signal RD_WT is effective, and the OUT output of first selector [S01] is communicated with D1 input for low level, and the second d type flip flop [D02], 3d flip-flop [03] are closed, and M bus address m_addr keeps; In state3 state, status signal BT_END is effective, the OUT output of first selector [S01] is communicated with for high level with D0 input, the ENB Enable Pin of the first triple gate [T01] is low level, first triple gate [T01] is closed, terminate the driving to M bus address m_addr, release M address bus.

Isa bus address isa_addr outputs to M bus address m_addr in the second isa bus operation cycle, after M bus address m_addr remains to the 6th isa bus operation cycle (corresponding M bus read write command terminates), then keep an isa bus cycle release.

By reference to the accompanying drawings 7, composition and the operation principle of read write command change-over circuit are described.

Described read write command change-over circuit comprises the 3rd multiplexer [M03], four d flip-flop [D04]; 3rd multiplexer [M03] is four select a multiplexer, and the 3rd multiplexer [M03], four d flip-flop [D04] data terminal are 4 bit widths;

The D0 input of the 3rd multiplexer [M03] connects isa bus I/O successively and writes isa_iow from a high position to low level, isa_memw write by isa bus memory, isa bus I/O reads isa_ior, isa_memr read by isa bus memory, the D1 input position corresponding to D2 input of the 3rd multiplexer [M03] is connected, and connect with the corresponding position of Q output of four d flip-flop [D04], the D3 input of the 3rd multiplexer [M03] is connected to level state 4 ' hF from a high position to low level, [the S1 of the 3rd multiplexer [M03], S2] selecting side is connected to count signal isa_ws_cnt, the Q output of the 3rd multiplexer [M03] is connected to the D input of four d flip-flop [D04], the clock end of four d flip-flop [D04] is connected to isa bus clock isa_bclk, the EN Enable Pin of four d flip-flop [D04] is connected to status signal RD_WT, the SET set end of four d flip-flop [D04] is connected to general reset rst, the Q output of four d flip-flop [D04] is connected to M bus I/O successively and writes m_iowc from a high position to low level, M bus driver writes m_mwtc, M bus I/O reads m_iorc, M bus driver reads m_mrdc.

In state2 state, status signal RD_WT is effective, count signal isa_ws_cnt counts from 2 ' b00, when isa_ws_cnt is 2 ' b00, isa bus read write command (isa_iow, isa_memw, isa_ior, isa_memr) M bus read write command end (m_iowc is outputted to, m_mwtc, m_iorc, m_mrdc), when isa_ws_cnt is 2 ' b01 and 2 ' b10, M bus read write command (m_iowc, m_mwtc, m_iorc, m_mrdc) remain unchanged, when isa_ws_cnt is 2 ' b11, M bus read write command (m_iowc, m_mwtc, m_iorc, m_mrdc) (all becoming high level) is terminated,

Isa bus read write command outputs to M bus read write command end in the 3rd isa bus operation cycle, and M bus read write command remained to for the 6th isa bus operation cycle and terminates (M bus read write command terminate terminate with isa bus read write command corresponding consistent).

By reference to the accompanying drawings 8, accompanying drawing 9, data write change-over circuit, data read change-over circuit composition and operation principle are described.

Described data are write change-over circuit and are comprised the 4th multiplexer [M04], the 5th multiplexer [M05], the 6th multiplexer [M06], second selector [S02], the 5th d type flip flop [D05], the 6th d type flip flop [D06], the second triple gate [T02], 4th multiplexer [M04], 5th multiplexer [M05], 6th multiplexer [M06] is alternative multiplexer, second selector [S02] is No. 3 selectors, 4th multiplexer [M04], 5th multiplexer [M05], second selector [S02], the data terminal of the 5th d type flip flop [D05] is 1 bit width, 6th multiplexer [M06], 6th d type flip flop [D06], the data terminal corresponding data bus of the second triple gate [T02], data width is 8 or 16, can adjust according to practical application,

The D0 input of the 4th multiplexer [M04] and the D1 input of second selector [S02], the Q output of the 5th d type flip flop [D05], the ENB Enable Pin of the second triple gate [T02] is connected, the D1 input of the 4th multiplexer [M04] is connected to high level, the S selecting side of the 4th multiplexer [M04] is connected to isa bus and writes isa_wt, the Q output of the 4th multiplexer [M04] is connected to the D0 input of the 5th multiplexer [M05], the D1 input of the 5th multiplexer [M05] is connected to low level, the S selecting side of the 5th multiplexer [M05] is connected to isa bus and reads isa_rd, the Q output of the 5th multiplexer [M05] is connected to the D2 input of second selector [S02], the D0 input of second selector [S02] is connected to low level, the S0 selecting side of second selector [S02] is connected to status signal BT_END, the S1 selecting side of second selector [S02] is connected to status signal RD_WT, the S2 selecting side of second selector [S02] is connected to status signal IDLE, the OUT output of second selector [S02] is connected to the D input of the 5th d type flip flop [D05], the clock end of the 5th d type flip flop [D05] is connected to isa bus clock isa_bclk, the CLR reset terminal of the 5th d type flip flop [D05] is connected to general reset rst,

The D0 input of the 6th multiplexer [M06] and the Q output of the 6th d type flip flop [D06], the input of the second triple gate [T02] is connected, the D1 input of the 6th multiplexer [M06] is connected to isa bus data isa_dat, the S selecting side of the 6th multiplexer [M06] is connected to isa bus and writes isa_wt, the Q output of the 6th multiplexer [M06] is connected to the D input of the 6th d type flip flop [D06], the clock end of the 6th d type flip flop [D06] is connected to isa bus clock isa_bclk, the EN Enable Pin of the 6th d type flip flop [D06] is connected to status signal IDLE, the CLR reset terminal of the 6th d type flip flop [D06] is connected to general reset rst, the output of the second triple gate [T02] is connected to M bus data m_dat.

Described data read that change-over circuit comprises the 7th multiplexer [M07], the 8th multiplexer [M08], the 9th multiplexer [M09], the tenth multiplexer [M10], the 11 multiplexer [M11], third selector [S03], the 6th equal comparator [E06], the 7th d type flip flop [D07], the 8th d type flip flop [D08], the 3rd triple gate [T03]; The data terminal of the 7th multiplexer [M07], the 8th multiplexer [M08], third selector [S03], the 7th d type flip flop [D07] is 1 bit width, 6th input equaling comparator [E06] is 2 bit widths, the data terminal corresponding data bus of the 9th multiplexer [M09], the tenth multiplexer [M10], the 11 multiplexer [M11], the 8th d type flip flop [D08], the 3rd triple gate [T03], data width is 8 or 16, can adjust according to practical application;

The D0 input of the 7th multiplexer [M07] and the D1 input of third selector [S03], the Q output of the 7th d type flip flop [D07], the ENB Enable Pin of the 3rd triple gate [T03] is connected, the D1 input of the 7th multiplexer [M07] is connected to low level, the S selecting side of the 7th multiplexer [M07] is connected to isa bus and writes isa_wt, the Q output of the 7th multiplexer [M07] is connected to the D0 input of the 8th multiplexer [M08], the D1 input of the 8th multiplexer [M08] is connected to high level, the S selecting side of the 8th multiplexer [M08] is connected to isa bus and reads isa_rd, the Q output of the 8th multiplexer [M08] is connected to the D2 input of third selector [S03], the D0 input of third selector [S03] is connected to low level, the S0 selecting side of third selector [S03] is connected to status signal BT_END, the S1 selecting side of third selector [S03] is connected to status signal RD_WT, the S2 selecting side of third selector [S03] is connected to status signal IDLE, the OUT output of third selector [S03] is connected to the D input of the 7th d type flip flop [D07], the clock end of the 7th d type flip flop [D07] is connected to isa bus clock isa_bclk, the CLR reset terminal of the 7th d type flip flop [D07] is connected to general reset rst,

The D0 input of the 9th multiplexer [M09] and the D0 input of the tenth multiplexer [M10], the D0 input of the 11 multiplexer [M11], the Q output of the 8th d type flip flop [D08], the input of the 3rd triple gate [T03] is connected, the D1 input of the 9th multiplexer [M09] is connected to M bus data m_dat, the S selecting side of the 9th multiplexer [M09] is connected to isa bus and reads isa_rd, the Q output of the 9th multiplexer [M09] is connected to the D1 input of the tenth multiplexer [M10], the anti-phase S selecting side of the tenth multiplexer [M10] is connected to M bus transfer and confirms m_xack, the Q output of the tenth multiplexer [M10] is connected to the D1 input of the 11 multiplexer [M11], the 6th A input equaling comparator [E06] is connected to count signal isa_ws_cnt, the 6th B input equaling comparator [E06] is connected to level state 2 ' b10 from high to low, the 6th OUT output equaling comparator [E06] is connected to the S selecting side of the 11 multiplexer [M11], the Q output of the 11 multiplexer [M11] is connected to the D input of the 8th d type flip flop [D08], the clock end of the 8th d type flip flop [D08] is connected to isa bus clock isa_bclk, 8th d type flip flop [D08] EN Enable Pin be connected to status signal RD_WT, the CLR reset terminal of the 8th d type flip flop [D08] is connected to general reset rst, the output of the 3rd triple gate [T03] is connected to isa bus data isa_dat.

For data write operation, it is high level that isa bus writes isa_wt, it is low level that isa bus reads isa_rd, at state1, state2, under state3 tri-states, corresponding states signal IDLE respectively, RD_WT, BT_END is effective, the output of third selector [S03] is low level, the ENB Enable Pin of the 3rd triple gate [T03] is low level, 3rd triple gate [T03] is closed, isa bus data isa_dat is made to be unidirectional input, in state1 state, status signal IDLE is effective, the output of second selector [S02] is high level, the Enable Pin of the second triple gate [T02] is high level, second triple gate [T02] conducting, the corresponding unidirectional output of M bus data m_dat, isa bus data isa_dat outputs to M bus data m_dat, in state2 state, status signal RD_WT is effective, the Enable Pin of the second triple gate [T02] remains high level, M bus data m_dat keeps, in state3 state, status signal BT_END is effective, the Enable Pin of the second triple gate [T02] becomes low level, second triple gate [T02] is closed, M bus data m_dat discharges,

For data write operation, isa bus data output to M bus data m_dat in the second isa bus operation cycle, and M bus data m_dat remains to the next isa bus cycle release after the 6th isa bus operation cycle (corresponding M bus read write command terminates);

For data reading operation, isa bus writes that isa_wt is low level, to read isa_rd be high level to isa bus, under state1, state2, state3 tri-states, corresponding states signal IDLE, RD_WT, BT_END is effective respectively, the output of second selector [S02] is low level, the ENB Enable Pin of the second triple gate [T02] is low level, second triple gate [T02] is closed, and makes M bus data m_dat be unidirectional input, at state1, under state2 state, corresponding states signal IDLE respectively, RD_WT is effective, the output of third selector [S03] is high level, the ENB Enable Pin of the 3rd triple gate [T03] is high level, 3rd triple gate [T03] conducting, under state2 state, status signal RD_WT is effective, when count signal isa_ws_cnt is 2 ' b10 and M bus transfer confirms that m_xack is low level, M bus data m_dat delivers to isa bus data terminal isa_dat, under state3 state, status signal BT_END is effective, the Enable Pin of the 3rd triple gate [T03] becomes low level, 3rd triple gate [T03] is closed, isa bus data isa_dat discharges,

For data reading operation, from the 5th isa bus operation cycle, after waiting for that M bus data m_dat effectively, M bus data m_dat is outputted to isa bus data terminal isa_dat, and isa bus data isa_dat remains to the next isa bus cycle release after the 6th isa bus operation cycle (corresponding M bus read write command terminates).

By reference to the accompanying drawings 10, composition and the operation principle of feedback circuit are described.

Described feedback circuit comprises the 12 multiplexer [M12], the 13 multiplexer [M13], the 9th d type flip flop [D09]; 12 multiplexer [M12] is four select a multiplexer, 13 multiplexer [M13] is alternative multiplexer, and the data terminal of the 12 multiplexer [M12], the 13 multiplexer [M13], the 9th d type flip flop [D09] is 1 bit width;

The D0 input of the 12 multiplexer [M12] and the D2 input of the 12 multiplexer [M12], the Q output of the 9th d type flip flop [D09], the S selecting side of the 13 multiplexer [M13] is connected, the D1 input of the 12 multiplexer [M12] is connected to high level, the D3 input of the 12 multiplexer [M12] is connected to low level, [the S1 of the 12 multiplexer [M12], S2] selecting side is connected to count signal isa_ws_cnt, the Q output of the 12 multiplexer [M12] is connected to the D input of the 9th d type flip flop [D09], the clock end of the 9th d type flip flop [D09] is connected to isa bus clock isa_bclk, the EN Enable Pin of the 9th d type flip flop [D09] is connected to status signal RD_WT, the CLR reset terminal of the 9th d type flip flop [D09] is connected to general reset rst, the D0 input of the 13 multiplexer [M13] is connected to high level, the anti-phase D1 input of the 13 multiplexer [M13] is connected to M bus transfer and confirms m_xack, the Q output of the 13 multiplexer [M13] is connected to isa bus from device ready isa_chrdy.

Under the effective reset mode of general reset rst, the Q output of the 9th d type flip flop [D09] is low level, isa bus is high level from device ready isa_chrdy, under state1 state, status signal IDLE is effective, the EN Enable Pin of the 9th d type flip flop [D09] is invalid, isa bus remains high level from device ready isa_chrdy, under state2 state, status signal RD_WT is effective, when count signal isa_ws_cnt is 2 ' b00, isa bus is still high level from device ready isa_chrdy, when isa_ws_cnt is 2 ' b01 and 2 ' b10, isa bus is the negate that M bus transfer confirms m_xack from device ready isa_chrdy, when isa_ws_cnt is 2 ' b11, isa bus is high level from device ready isa_chrdy, under state3 state, status signal BT_END is effective, the EN Enable Pin of the 9th d type flip flop [D09] is invalid, isa bus remains high level from device ready isa_chrdy,

M bus transfer confirms that m_xack is Low level effective, represent M bus write data complete or read data ready, isa bus read-write operation can at the 5th isa bus operation cycle and the possible ready isa_chrdy of insertion latent period sampled I SA bus slave, to judge that whether isa bus read data is ready, therefore isa bus from device ready isa_chrdy within the four to the six isa bus operation cycle, value is the inverse value that M bus transfer confirms m_xack, be fixed as high level in other situation, its feedback function can be realized.

By reference to the accompanying drawings 11, composition and the operation principle of reset circuit are described.

Reset circuit receives isa bus reset (isa_resetdrv, effectively high) and system reset (sys_rst, low effectively), export M bus reset (m_init, low effectively), and export general reset (rst, effectively high) to state transitions circuit and sequential processing circuit;

Reset circuit comprises the 4th or door [OR04], the first not gate [N01]; 4th or door [OR04], the first not gate [N01] port be 1 bit width, 4th or the inverting input 1 of door [OR04] be connected to system reset sys_rst, 4th or the input 2 of door [OR04] and the input of the first not gate [N01] be connected to isa bus reset isa_resetdrv, 4th or the output of door [OR04] be connected to general reset rst, the output of the first not gate [N01] is connected to M bus reset m_init.

Isa bus reset isa_resetdrv is effectively high, M bus reset m_init is effectively low, so the two is changed by not gate, and the combination that the general reset rst that state transitions circuit and sequential processing circuit use is system reset sys_rst and isa bus reset isa_resetdrv, system reset sys_rst and isa bus reset isa_resetdrv have one effective time, general reset rst is effective.Multibus bus is called for short M bus.

As from the foregoing, circuit structure of the present invention is simple, and support 8 and 16 bit data width, address wire can be expanded as required; This circuit conversion efficiency is high, and frequency adaptability is strong, may be used for the isa bus clock ranges of 7MHz ~ 10MHz; This circuit highly versatile, can realize, take resource few on general CPLD/FPGA logic chip, low in energy consumption; This circuit is changed by the read-write sequence of isa bus to Multibus bus, achieves on isa bus cabinet, configure Multibus bus slave mixed insertion and compatibility; In field tests, based on the test macro of isa bus, except direct test I SA bus module, if adopt circuit of the present invention, can extend testing Multibus bus from module, and then improve system testing ability.

Claims (4)

1. isa bus is to a read-write operation change-over circuit for Multibus bus, it is characterized in that: comprise state transitions circuit, sequential processing circuit, reset circuit, interrupt circuit; Wherein core ISA tri-bus of isa bus is connected with sequential processing circuit with state transitions circuit, core ISA tri-bus of isa bus comprises control bus, address bus, data/address bus, isa bus interrupt signal is connected with interrupt circuit, and state transitions circuit output timing control signal is to sequential treatment circuit; Core Multibus tri-bus of Multibus bus is connected with sequential processing circuit with state transitions circuit, Multibus bus interrupt signal is connected with interrupt circuit, reset circuit receives isa bus reset signal and systematic reset signal, export general reset signal to state transitions circuit and sequential processing circuit, and export Mulitbus bus reset signal to Multibus bus;

State transitions circuit adopts isa bus clock as the work clock of state machine, and carry out state transitions process by synchronous finite state-machine, output timing control signal is to sequential treatment circuit;

The timing control signal that sequential processing circuit provides according to state transitions circuit carries out sequential processing to ISA tri-bus, realizes the timing conversion of ISA tri-bus to the read-write operation of Multibus tri-bus;

Interrupt circuit receives Multibus bus interrupt signal from Multibus bus, exports isa bus interrupt signal to isa bus, realizes the transfer process of interrupt signal;

Reset circuit realizes the conversion of isa bus reset signal to Multibus bus reset signal, and provides the general reset signal that state transitions circuit and sequential processing circuit use.

2. isa bus according to claim 1 is to the read-write operation change-over circuit of Multibus bus, it is characterized in that: the signal that state transitions circuit is connected with ISA tri-bus comprises isa bus clock (isa_bclk), isa bus memory reads (isa_memr), isa bus memory writes (isa_memw), isa bus I/O reads (isa_ior), isa bus I/O writes (isa_iow); The signal that state transitions circuit is connected with Multibus tri-bus is that M bus transfer confirms (m_xack), and the timing control signal that state transitions circuit outputs to sequential processing circuit comprises: isa bus is read (isa_rd), isa bus writes (isa_wt), isa bus read/write (isa_rd_wt), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END; The reset signal of state transitions circuit is carry out the general reset of self-resetting circuit (rst);

State transitions circuit comprises first and equals comparator [E01], second and equal comparator [E02], the 3rd and equal comparator [E03], the 4th and equal comparator [E04], the 5th and equal comparator [E05], first or door [OR01], second or door [OR02], the 3rd or door [OR03], the first multiplexer [M01], the second multiplexer [M02], the first d type flip flop [D01], the first state machine module [U01];

The above-mentioned A input equaling comparator exports high level, unequal output low level time equal with B input, and above-mentioned first multiplexer [M01] is alternative multiplexer, and the second multiplexer [M02] is four select a multiplexer, when the S selecting side of alternative multiplexer is low level, D0 input is communicated with Q output, and when the S selecting side of alternative multiplexer is high level, D1 input is connected with Q output, four [the S1 selecting a multiplexer, S2] selecting side when being 2 ' b00 D0 input be communicated with Q output, [S1, S2] selecting side when being 2 ' b01 D1 input be communicated with Q output, [S1, S2] selecting side when being 2 ' b10 D2 input be communicated with Q output, when [S1, S2] selecting side is 2 ' b11, D3 input is communicated with Q output, first equals comparator [E01], second equals comparator [E02], 3rd equals comparator [E03], 4th equals comparator [E04], 5th input equaling comparator [E05] is 4 bit widths, the data terminal of the first multiplexer [M01], the data terminal of the second multiplexer [M02], the data terminal of the first d type flip flop [D01], 5th input equaling comparator [E05] is 2 bit widths, first or door [OR01], second or door [OR02], 3rd or the external interface of door [OR03] and the first state machine module [U01] be 1 bit width,

First equals comparator [E01], second equals comparator [E02], the 3rd and equals the A input that comparator [E03], the 4th equals comparator [E04] and be connected, and is connected to that isa bus I/O writes isa_iow, isa_memw write by isa bus memory, isa bus I/O reads isa_ior, isa_memr read by isa bus memory from a high position to low level successively; The first B input equaling comparator [E01] is connected to level state 4 ' hE from a high position to low level, the second B input equaling comparator [E02] is connected to level state 4 ' hD from a high position to low level, the 3rd B input equaling comparator [E03] is connected to level state 4 ' hB from a high position to low level, and the 4th B input equaling comparator [E04] is connected to level state 4 ' h7 from a high position to low level; the first OUT output equaling comparator [E01] is connected to first or door [OR01] input 1, the second OUT output equaling comparator [E02] is connected to first or door [OR01] input 2, first or the output end signal of door [OR01] be that isa bus is read (isa_rd), be connected to the input 1 of the 3rd or door [OR03] and output to sequential processing circuit, the 3rd OUT output equaling comparator [E03] is connected to second or door [OR02] input 1, the 4th OUT output equaling comparator [E04] is connected to second or door [OR02] input 2, second or the output end signal of door [OR02] be that isa bus is write (isa_wt), be connected to the input 2 of the 3rd or door [OR03] and output to sequential processing circuit, 3rd or the output end signal of door [OR03] be isa bus read/write (isa_rd_wt), be connected to the T1 input of the first state machine module [U01] and output to sequential processing single channel,

The D1 input of the first multiplexer [M01] is connected to level state 2 ' b11 from high to low, the anti-phase S selecting side of the first multiplexer [M01] is connected to external signal M bus transfer and confirms m_xack, the Q output of the first multiplexer [M01] is connected to the D2 input of the second multiplexer [M02], the D0 input of the second multiplexer [M02] is connected to level state 2 ' b01 from a high position to low level, the D1 input of the second multiplexer [M02] is connected to level state 2 ' b10 from a high position to low level, the D3 input of the second multiplexer [M02] is connected to level state 2 ' b00 from a high position to low level, the Q output of the second multiplexer [M02] is connected to the D input of the first d type flip flop [D01], the clock end of the first d type flip flop [D01] is connected to isa bus clock isa_bclk, the EN Enable Pin of the first d type flip flop [D01] is connected to status signal RD_WT, the CLR reset terminal of the first d type flip flop [D01] is connected to general reset rst, the Q output of the first d type flip flop [D01] is count signal isa_ws_cnt, with the D0 input of the first multiplexer [M01], [the S1 of the second multiplexer [M02], S2] selecting side, the 5th A input equaling comparator [E05] is connected, and output to sequential processing circuit, the 5th B input equaling comparator [E05] is connected to level state 2 ' b11 from a high position to low level, the 5th OUT output equaling comparator [E05] is connected to the T2 input of the first state machine module [U01], the CLK clock end of the first state machine module [U01] is connected to isa bus clock isa_bclk, the CLR reset terminal of the first state machine module [U01] is connected to general reset rst, the state output end signal of the first state machine module [U01] comprises status signal IDLE, RD_WT, BT_END, outputs to sequential processing circuit respectively,

Described first state machine module [U01] adopts isa bus clock isa_bclk as state machine work clock, the state transitions condition of the first state machine module [U01] comprises T1 and T2, effective status comprises state1, state2, state3, corresponding states signal IDLE respectively, RD_WT, BT_END, when general reset rst is effective, system is in state1 state, status signal IDLE is effective, under the normal running conditions that general reset rst cancels, when T1 is invalid (T1=0), state machine is in state1 state, when T1 is effective (T1=1), state machine transfers to state2 state, status signal RD_WT is effective, when T2 is invalid, state machine is in state2 state, when T2 is effective (T2=1), state machine transfers to state3 state, status signal BT_END is effective, after state3 state stops an isa bus clock (isa_clk), transfer to state1 state, complete the state transitions operation of a state machine.

3. isa bus according to claim 1 is to the read-write operation change-over circuit of Multibus bus, it is characterized in that: the signal that sequential processing circuit is connected with ISA tri-bus comprises isa bus memory and reads (isa_memr), isa bus memory is write (isa_memw), isa bus I/O reads (isa_ior), isa bus I/O writes (isa_iow), isa bus address (isa_addr), isa bus data (isa_dat), isa bus is from device ready (isa_chrdy), and the output signal of the state transitions circuit that sequential processing circuit receives comprises isa bus and reads (isa_rd), isa bus is write (isa_wt), isa bus read/write (isa_rd_wt), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END, the signal that sequential processing circuit is connected with Multibus tri-bus comprises M bus driver and reads (m_mrdc, low effectively), M bus driver is write (m_mwtc), M bus I/O reads (m_iorc), M bus I/O writes (m_iowc), M bus address (m_addr), M bus data (m_dat), M bus transfer confirms (m_xack), and the reset signal of sequential processing circuit carrys out the general reset of self-resetting circuit (rst),

Sequential processing circuit comprises address conversion circuit, read write command change-over circuit, data write change-over circuit, data read change-over circuit, feedback circuit; Address conversion circuit, read write command change-over circuit, data write change-over circuit, data read change-over circuit, feedback circuit all adopts isa bus clock (isa_bclk) as work clock, adopt general reset (rst) as reset signal;

Address conversion circuit is used for realizing isa bus address (isa_addr) to be changed to the read-write sequence of M bus address (m_addr), and the timing control signal of input comprises isa bus read/write (isa_rd_wt), status signal IDLE, RD_WT, BT_END;

Read write command change-over circuit is used for realizing the read-write sequence conversion of isa bus read-write operation order (isa_memr read by isa bus memory, isa_memw write by isa bus memory, isa bus I/O read isa_ior, I/O bus I/O and write isa_iow) to M bus read-write operation order (M bus driver read m_mrdc, M bus driver write m_mwtc, M bus I/O read m_iorc, M bus I/O and write m_iowc), and the timing control signal of input comprises count signal (isa_ws_cnt), status signal RD_WT;

Data write change-over circuit for realizing the write operation timing conversion of isa bus data (isa_dat) to M bus data (m_dat), and the timing control signal of input comprises that isa bus reads (isa_rd), isa bus writes (isa_wt), status signal IDLE, RD_WT, BT_END;

Data read change-over circuit for realizing the read operation timing conversion of M bus data (m_dat) to isa bus data (isa_dat), the timing control signal of input comprises that isa bus reads (isa_rd), isa bus writes (isa_wt), count signal (isa_ws_cnt), status signal IDLE, RD_WT, BT_END, and the feedback signal of input is that M bus transfer confirms (m_xack);

Feedback circuit is used for realizing M bus transfer and confirms (m_xack) timing conversion to isa bus from the feedback signal of device ready (isa_chrdy), and the timing control signal of input comprises count signal (isa_ws_cnt), status signal RD_WT;

Described address conversion circuit comprises first selector [S01], the second d type flip flop [D02], 3d flip-flop [D03], the first triple gate [T01]; First selector [S01] is No. three selectors, when being high level when only having S0 selecting side, D0 input is communicated with OUT output, when being high level when only having S1 selecting side, D1 input is communicated with OUT output, when being high level when only having S2 selecting side, D2 input and OUT output gating; The data terminal of first selector [S01], the second d type flip flop [D02] is 1 bit width, the data terminal corresponding address bus of 3d flip-flop [D03], the first triple gate [T01], data width can adjust according to practical application, is defaulted as 20 bit widths;

The D0 input of first selector [S01] is connected to high level, the D1 input of first selector [S01] is connected to low level, the D2 input of first selector [S01] is connected to isa bus read/write isa_rd_wt, the S0 selecting side of first selector [S01] is connected to status signal BT_END, the S1 selecting side of first selector [S01] is connected to status signal RD_WT, the S2 selecting side of first selector [S01] is connected to status signal IDLE, the OUT output of first selector [S01] and the EN Enable Pin of the second d type flip flop [D02], the EN Enable Pin of 3d flip-flop [D03] is connected, the anti-phase D input of the second d type flip flop [D02] is connected to status signal BT_END, the Q output of the second d type flip flop [D02] is connected to the ENB Enable Pin of the first triple gate [T01], the D input of 3d flip-flop [D03] is connected to isa bus address isa_addr, the Q output of 3d flip-flop [D03] is connected to the input of the first triple gate [T01], second d type flip flop [D02], the clock end of 3d flip-flop [D03] is all connected to isa bus clock isa_bclk, second d type flip flop [D02], the CLR reset terminal of 3d flip-flop [D03] is all connected to general reset rst, the output of the first triple gate [T01] is connected to M bus address m_addr,

Described read write command change-over circuit comprises the 3rd multiplexer [M03], four d flip-flop [D04]; 3rd multiplexer [M03] is four select a multiplexer, and the 3rd multiplexer [M03], four d flip-flop [D04] data terminal are 4 bit widths;

The D0 input of the 3rd multiplexer [M03] connects isa bus I/O successively and writes isa_iow from a high position to low level, isa_memw write by isa bus memory, isa bus I/O reads isa_ior, isa_memr read by isa bus memory, the D1 input position corresponding to D2 input of the 3rd multiplexer [M03] is connected, and connect with the corresponding position of Q output of four d flip-flop [D04], the D3 input of the 3rd multiplexer [M03] is connected to level state 4 ' hF from a high position to low level, [the S1 of the 3rd multiplexer [M03], S2] selecting side is connected to count signal isa_ws_cnt, the Q output of the 3rd multiplexer [M03] is connected to the D input of four d flip-flop [D04], the clock end of four d flip-flop [D04] is connected to isa bus clock isa_bclk, the EN Enable Pin of four d flip-flop [D04] is connected to status signal RD_WT, the SET set end of four d flip-flop [D04] is connected to general reset rst, the Q output of four d flip-flop [D04] is connected to M bus I/O successively and writes m_iowc from a high position to low level, M bus driver writes m_mwtc, M bus I/O reads m_iorc, M bus driver reads m_mrdc,

Described data are write change-over circuit and are comprised the 4th multiplexer [M04], the 5th multiplexer [M05], the 6th multiplexer [M06], second selector [S02], the 5th d type flip flop [D05], the 6th d type flip flop [D06], the second triple gate [T02], 4th multiplexer [M04], 5th multiplexer [M05], 6th multiplexer [M06] is alternative multiplexer, second selector [S02] is No. 3 selectors, 4th multiplexer [M04], 5th multiplexer [M05], second selector [S02], the data terminal of the 5th d type flip flop [D05] is 1 bit width, 6th multiplexer [M06], 6th d type flip flop [D06], the data terminal corresponding data bus of the second triple gate [T02], data width is 8 or 16, can adjust according to practical application,

The D0 input of the 4th multiplexer [M04] and the D1 input of second selector [S02], the Q output of the 5th d type flip flop [D05], the ENB Enable Pin of the second triple gate [T02] is connected, the D1 input of the 4th multiplexer [M04] is connected to high level, the S selecting side of the 4th multiplexer [M04] is connected to isa bus and writes isa_wt, the Q output of the 4th multiplexer [M04] is connected to the D0 input of the 5th multiplexer [M05], the D1 input of the 5th multiplexer [M05] is connected to low level, the S selecting side of the 5th multiplexer [M05] is connected to isa bus and reads isa_rd, the Q output of the 5th multiplexer [M05] is connected to the D2 input of second selector [S02], the D0 input of second selector [S02] is connected to low level, the S0 selecting side of second selector [S02] is connected to status signal BT_END, the S1 selecting side of second selector [S02] is connected to status signal RD_WT, the S2 selecting side of second selector [S02] is connected to status signal IDLE, the OUT output of second selector [S02] is connected to the D input of the 5th d type flip flop [D05], the clock end of the 5th d type flip flop [D05] is connected to isa bus clock isa_bclk, the CLR reset terminal of the 5th d type flip flop [D05] is connected to general reset rst,

The D0 input of the 6th multiplexer [M06] and the Q output of the 6th d type flip flop [D06], the input of the second triple gate [T02] is connected, the D1 input of the 6th multiplexer [M06] is connected to isa bus data isa_dat, the S selecting side of the 6th multiplexer [M06] is connected to isa bus and writes isa_wt, the Q output of the 6th multiplexer [M06] is connected to the D input of the 6th d type flip flop [D06], the clock end of the 6th d type flip flop [D06] is connected to isa bus clock isa_bclk, the EN Enable Pin of the 6th d type flip flop [D06] is connected to status signal IDLE, the CLR reset terminal of the 6th d type flip flop [D06] is connected to general reset rst, the output of the second triple gate [T02] is connected to M bus data m_dat,

Described data read that change-over circuit comprises the 7th multiplexer [M07], the 8th multiplexer [M08], the 9th multiplexer [M09], the tenth multiplexer [M10], the 11 multiplexer [M11], third selector [S03], the 6th equal comparator [E06], the 7th d type flip flop [D07], the 8th d type flip flop [D08], the 3rd triple gate [T03]; The data terminal of the 7th multiplexer [M07], the 8th multiplexer [M08], third selector [S03], the 7th d type flip flop [D07] is 1 bit width, 6th input equaling comparator [E06] is 2 bit widths, the data terminal corresponding data bus of the 9th multiplexer [M09], the tenth multiplexer [M10], the 11 multiplexer [M11], the 8th d type flip flop [D08], the 3rd triple gate [T03], data width is 8 or 16, can adjust according to practical application;

The D0 input of the 7th multiplexer [M07] and the D1 input of third selector [S03], the Q output of the 7th d type flip flop [D07], the ENB Enable Pin of the 3rd triple gate [T03] is connected, the D1 input of the 7th multiplexer [M07] is connected to low level, the S selecting side of the 7th multiplexer [M07] is connected to isa bus and writes isa_wt, the Q output of the 7th multiplexer [M07] is connected to the D0 input of the 8th multiplexer [M08], the D1 input of the 8th multiplexer [M08] is connected to high level, the S selecting side of the 8th multiplexer [M08] is connected to isa bus and reads isa_rd, the Q output of the 8th multiplexer [M08] is connected to the D2 input of third selector [S03], the D0 input of third selector [S03] is connected to low level, the S0 selecting side of third selector [S03] is connected to status signal BT_END, the S1 selecting side of third selector [S03] is connected to status signal RD_WT, the S2 selecting side of third selector [S03] is connected to status signal IDLE, the OUT output of third selector [S03] is connected to the D input of the 7th d type flip flop [D07], the clock end of the 7th d type flip flop [D07] is connected to isa bus clock isa_bclk, the CLR reset terminal of the 7th d type flip flop [D07] is connected to general reset rst,

The D0 input of the 9th multiplexer [M09] and the D0 input of the tenth multiplexer [M10], the D0 input of the 11 multiplexer [M11], the Q output of the 8th d type flip flop [D08], the input of the 3rd triple gate [T03] is connected, the D1 input of the 9th multiplexer [M09] is connected to M bus data m_dat, the S selecting side of the 9th multiplexer [M09] is connected to isa bus and reads isa_rd, the Q output of the 9th multiplexer [M09] is connected to the D1 input of the tenth multiplexer [M10], the anti-phase S selecting side of the tenth multiplexer [M10] is connected to M bus transfer and confirms m_xack, the Q output of the tenth multiplexer [M10] is connected to the D1 input of the 11 multiplexer [M11], the 6th A input equaling comparator [E06] is connected to count signal isa_ws_cnt, the 6th B input equaling comparator [E06] is connected to level state 2 ' b10 from high to low, the 6th OUT output equaling comparator [E06] is connected to the S selecting side of the 11 multiplexer [M11], the Q output of the 11 multiplexer [M11] is connected to the D input of the 8th d type flip flop [D08], the clock end of the 8th d type flip flop [D08] is connected to isa bus clock isa_bclk, 8th d type flip flop [D08] EN Enable Pin be connected to status signal RD_WT, the CLR reset terminal of the 8th d type flip flop [D08] is connected to general reset rst, the output of the 3rd triple gate [T03] is connected to isa bus data isa_dat,

Described feedback circuit comprises the 12 multiplexer [M12], the 13 multiplexer [M13], the 9th d type flip flop [D09]; 12 multiplexer [M12] is four select a multiplexer, 13 multiplexer [M13] is alternative multiplexer, and the data terminal of the 12 multiplexer [M12], the 13 multiplexer [M13], the 9th d type flip flop [D09] is 1 bit width;

The D0 input of the 12 multiplexer [M12] and the D2 input of the 12 multiplexer [M12], the Q output of the 9th d type flip flop [D09], the S selecting side of the 13 multiplexer [M13] is connected, the D1 input of the 12 multiplexer [M12] is connected to high level, the D3 input of the 12 multiplexer [M12] is connected to low level, [the S1 of the 12 multiplexer [M12], S2] selecting side is connected to count signal isa_ws_cnt, the Q output of the 12 multiplexer [M12] is connected to the D input of the 9th d type flip flop [D09], the clock end of the 9th d type flip flop [D09] is connected to isa bus clock isa_bclk, the EN Enable Pin of the 9th d type flip flop [D09] is connected to status signal RD_WT, the CLR reset terminal of the 9th d type flip flop [D09] is connected to general reset rst, the D0 input of the 13 multiplexer [M13] is connected to high level, the anti-phase D1 input of the 13 multiplexer [M13] is connected to M bus transfer and confirms m_xack, the Q output of the 13 multiplexer [M13] is connected to isa bus from device ready isa_chrdy.

4. isa bus according to claim 1 is to the read-write operation change-over circuit of Multibus bus, it is characterized in that: reset circuit receives isa bus reset (isa_resetdrv) and system reset (sys_rst), export M bus reset (m_init), and export general reset (rst) to state transitions circuit and sequential processing circuit;

Reset circuit comprises the 4th or door [OR04], the first not gate [N01]; 4th or door [OR04], the first not gate [N01] port be 1 bit width, 4th or the inverting input 1 of door [OR04] be connected to system reset sys_rst, 4th or the input 2 of door [OR04] and the input of the first not gate [N01] be connected to isa bus reset isa_resetdrv, 4th or the output of door [OR04] be connected to general reset rst, the output of the first not gate [N01] is connected to M bus reset m_init.