CN203520396U - Integrated circuit for optimizing control signals of registers - Google Patents
Integrated circuit for optimizing control signals of registers Download PDFInfo
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- CN203520396U CN203520396U CN201320514529.6U CN201320514529U CN203520396U CN 203520396 U CN203520396 U CN 203520396U CN 201320514529 U CN201320514529 U CN 201320514529U CN 203520396 U CN203520396 U CN 203520396U
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Abstract
The utility model relates to an integrated circuit for optimizing control signals of registers. The integrated circuit comprises a logical unit. The logical unit comprises the registers, a combined logical circuit for conducting logical operation, and an input end for mapping the control signal of the register which originally belongs to the registers to the register, wherein the registers with the different control signals are distributed in the same logical unit. By means of the integrated circuit, the various registers with the independent control signals can be distributed in the same PLB, the number of the independent control signals is lowered, and the success rate of wire arrangement is improved.
Description
Technical field
The utility model relates to FPGA, is specifically related to a kind of integrated circuit in FPGA hardware structure.
Background technology
At many FPGA(Field-Programmable Gate Array, be field programmable gate array) hardware structure in, conventionally can be by a PLB(Programmable Logic Block, be programmed logical module) in one group of register share identical control signal (enabling/reset/set), therefore when placement-and-routing, the register that must have identical control signal just can be placed in the middle of same PLB, for having the large-scale design of register of more independent control signal, during layout, must be distributed in the middle of different PLB, thereby make the result of layout quite loose, and then can increase the complexity while connecting up, reduce the success ratio of wiring.Even for the too much design of control signal independently, will be failed at layout stage.
Design and a kind ofly in the logic synthesis stage, reduce the integrated circuit that the quantity of control signal independently promotes placement-and-routing's success ratio, to eliminate original the enabling of this register/synchronous set/synchronous reset signal, reducing the independently quantity of control signal, is problem demanding prompt solution.
Utility model content
The purpose of this utility model is to provide and a kind ofly in the logic synthesis stage, reduces the integrated circuit that the quantity of control signal independently promotes placement-and-routing's success ratio, to solve under large-scale design, the register that has more independent control signal is controlled signals disperse when layout, layout result is loose, the problem that complicacy is larger.
For achieving the above object, the utility model provides a kind of integrated circuit of optimizing register control signal, by adding the mode of a part of combinational logic, eliminate original the enabling of this register/synchronous set/synchronous reset signal, thereby reach, reduce the independently object of the quantity of control signal.
The utility model provides a kind of integrated circuit of optimizing register control signal, comprise: LE, comprise a plurality of registers, as the combinational logic circuit of logical operation, the former control signal that belongs to a register in a plurality of registers is mapped to the input end of this register.
The utility model has solved the problem that large-scale layout result is loose, complexity is higher of the register that has more independent control signal under prior art, used less general-purpose device, realize the optimization of register control signal, improved the success ratio of placement-and-routing.
Accompanying drawing explanation
Fig. 1 is the process mapping method process flow diagram of optimizing register control signal in the utility model;
Fig. 2 be in the utility model embodiment 1 in a LE register share enable signal schematic diagram;
Fig. 3 a-b contains the prioritization scheme schematic diagram of the register control signal of enable signal in the utility model embodiment 1;
Fig. 4 contains the prioritization scheme schematic diagram of the register control signal of synchronous reset signal in the utility model embodiment 2;
Fig. 5 contains the prioritization scheme schematic diagram of synchronous asserts signal register control signal in the utility model embodiment 3;
Fig. 6 contains the prioritization scheme schematic diagram of enable signal and synchronous reset signal register control signal in the utility model embodiment 4;
Fig. 7 is the prioritization scheme schematic diagram that contains enable signal and synchronous asserts signal register control signal in the utility model embodiment 5;
Fig. 8 is the prioritization scheme schematic diagram that contains enable signal, synchronous reset signal and synchronous asserts signal register control signal in the utility model embodiment 6.
Embodiment
Fig. 1 is a kind of process mapping method process flow diagram of optimizing register control signal in the utility model.The method comprises the following steps:
In step 100, user design is carried out to Method at Register Transfer Level comprehensive, obtain the gate level netlist of register.RTL(Register-transfer Level), it is Method at Register Transfer Level, between statement in RTL model literary style and the structural model of actual register, have direct mapping relations, Method at Register Transfer Level is comprehensively mapped to RTL literary style on concrete device exactly, realizes function of equal value; Gate level netlist is the function that (such as smic0.13um logic G) lower concrete device (such as standard block) is realized RTL under concrete technique.For example, in RTL, Y=A+C; In gate level netlist, will become so: under smic0.13um logic G, have a standard block OR2X2, it is input as A, C, it is output as Y.
In step 101, gather in control signal source to register, adds up corresponding gauze fan-out, when fan-out is less than certain numerical value (such as 100), illustrate that in register, independently the quantity of control signal is too much, need to be optimized the control signal of register.
It should be noted that, this certain numerical value can be different because of different chip architectures, even under identical chip architecture, according to different place-and-route algorithms or different user's designs, its rational value is also uncertain, and normally the chip for certain certain architectures provides a numerical value roughly as a reference according to the historical experience of placement-and-routing.
In step 110, the control signal of at least one register is mapped to the input end of register by combinational logic, make the register layout that contains different control signals in same LE.
Wherein, described control signal comprises enable signal, synchronous reset signal and synchronous asserts signal, and this control signal high level is effective.
In step 111, described combinational logic is mapped in the look-up table LUT of LE.
Below in conjunction with Fig. 2, the concrete implementation step of Fig. 1 is described further.
At FPGA(field programmable gate array) in a basic logic piece PLB(programmed logical module) under, comprise LE(Logic Element, i.e. a logical block) and Xbar, wherein, a LE comprises again 4 LP(Logic Parcel, i.e. logic bag).In one embodiment, combinational logic comprises MUX, in concrete LP, combinational logic is positioned at Muxes (multiplexer, be multiplexer) unit, its again with 34 input LUT(Look-Up Table, look-up table) be LUT0, LUT40 is connected with LUT41, LUT can realize the function identical with logical circuit, each LUT is equivalent to have the RAM of 4 line addresses, after user is by schematic diagram or logical circuit of HDL language description, FPGA develops software and understands all possible outcomes of automatic calculation logic circuit, and truth table (result) is write in RAM in advance, signal of every like this input carries out logical operation and just equals to input an address and table look-up, find out content corresponding to address output.In Fig. 2, whole 8 registers in LE are shared same enable signal.
Below in conjunction with Fig. 3-Fig. 8, to optimizing the specific implementation method of register control signal, do concrete description.Fig. 3 a-b contains the prioritization scheme schematic diagram of the register control signal of enable signal in the utility model embodiment 1.
Wherein, the register 1 that is arranged in LE1 contains enable signal En1, and the register 2 that is arranged in LE2 contains enable signal En2, and their clock signal is identical, and enable signal is different, and combinational logic comprises MUX, gives in register and adds MUX.Wherein, enable signal is connected to the data selection end of MUX, data input signal is connected to the input end of MUX, the output terminal of register is connected to the another input end of MUX, and when enable signal is invalid, register can keep original state; The output terminal of MUX is connected to the input end of register, is arranged in the register that contains enable signal of different LE, by add the mode of MUX can layout in same LE.
Fig. 4 is the prioritization scheme schematic diagram of the register control signal that contains synchronous reset signal in the utility model embodiment 2.
Wherein, control signal in register comprises synchronous reset signal Rst1 and Rst2, combinational logic comprises and door and not gate, by after synchronous reset signal negate (can be to connect not gate), be connected to the input end with door together with data input signal, output terminal with door is connected to the input end of register, is arranged in the register that contains synchronous reset signal of different LE, by add not gate and with the mode of door can layout in same LE.
Fig. 5 is the prioritization scheme schematic diagram of the register control signal that contains synchronous asserts signal in the utility model embodiment 3.
Wherein, control signal in register is synchronous asserts signal Set1 and Set2, combinational logic comprises or door, by synchronous asserts signal and data input signal is connected to or door input end, by or the output terminal of door be connected to the input end of register, be arranged in the register that contains synchronous asserts signal of different LE, by add not gate and with the mode of door can layout in same LE.
Fig. 6 is the prioritization scheme schematic diagram of the register control signal that contains enable signal En and synchronous reset signal in the utility model embodiment 4.Wherein, control signal in register is enable signal En and synchronous reset signal Rst, combinational logic comprise MUX, with door and not gate, enable signal is connected to the data selection end of MUX, data input signal is connected to the input end of MUX, the another input end of MUX is connected to the output terminal of register, by synchronous reset signal through the non-first input end being connected to behind the door with door, the output terminal of MUX is connected to the second input end with door, the output terminal with door is connected to the input end of register.Be arranged in the register that contains enable signal En and synchronous reset signal Rst of different LE, by add MUX, with the mode of door and not gate can layout in same LE.
Fig. 7 is the prioritization scheme schematic diagram that contains the register control signal of enable signal and synchronous asserts signal in the utility model embodiment 5.Wherein, the control signal of register is enable signal En and synchronous asserts signal Set, combinational logic comprise MUX and or door, enable signal is connected to the data selection end of MUX, the another input end of MUX is connected to the output terminal of register, synchronous asserts signal is connected to or the first input end of door, the output terminal of MUX is connected to or the second input end of door, by or the output terminal of door be connected to the input end of register.Be arranged in the register that contains enable signal and synchronous asserts signal of different LE, by add MUX and or the mode of door can layout in same LE.
Fig. 8 is the prioritization scheme schematic diagram that contains the register control signal of enable signal, synchronous reset signal and synchronous asserts signal in the utility model embodiment 6.Wherein, the control signal of register is enable signal En, synchronous reset signal Rst and synchronous asserts signal Set, combinational logic comprises MUX, not gate, with door and or door, enable signal is connected to the data selection end of MUX, data input signal is connected to the data input pin of MUX, the another input end of MUX is connected to the output terminal of register, synchronous asserts signal is connected to or door first input end, the output terminal of MUX be connected to or door the second input end, by synchronous reset signal through the non-first input end being connected to behind the door with door, by or the output terminal of door be connected to the second input end with door, be connected to the input end of register with the output terminal of door.Be arranged in the register that contains enable signal, synchronous reset signal and synchronous asserts signal of different LE, by add MUX, not gate, with door and or the mode of door can layout in same LE.
It should be noted that, in fpga chip, can realize by existing look-up table resource on chip the function of added combinational logic.
It should be noted last that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not depart from the spirit and scope of technical solutions of the utility model.
Claims (7)
1. an integrated circuit of optimizing register control signal, comprise: logical block, comprise a plurality of registers, combinational logic circuit as logical operation, the former control signal that belongs to a register in a plurality of registers is mapped to the input end of this register, makes the register layout that contains different control signals in same logical block.
2. a kind of integrated circuit of optimizing register control signal as claimed in claim 1, is characterized in that, described control signal is enable signal, and described combinational logic comprises MUX; Enable signal is coupled to the data selection end of MUX, and the another input end of MUX is connected to the output terminal of register, and the output terminal of MUX is connected to the input end of register.
3. a kind of integrated circuit of optimizing register control signal as claimed in claim 1, it is characterized in that, described control signal is synchronous reset signal, described combinational logic comprises and door, not gate, synchronous reset signal is connected to the input end with door with data input signal behind the door through non-, the output terminal with door is connected to the input end of register.
4. a kind of integrated circuit of optimizing register control signal as claimed in claim 1, is characterized in that, described control signal is synchronous asserts signal, and described combinational logic comprises or door; By synchronous asserts signal with data input signal is connected to or the input end of door, by or door be connected to the input end of register.
5. a kind of integrated circuit of optimizing register control signal as claimed in claim 1, is characterized in that, described control signal is enable signal and synchronous reset signal, described combinational logic comprise MUX, not gate and with door; Enable signal is coupled to the data selection end of MUX, the another input end of MUX is connected to the output terminal of register, by synchronous reset signal through the non-first input end being connected to behind the door with door, the output terminal of MUX is connected to the second input end with door, the output terminal with door is connected to the input end of register.
6. a kind of integrated circuit of optimizing register control signal as claimed in claim 1, is characterized in that, described control signal is enable signal and synchronous asserts signal, described combinational logic comprise MUX and or door; Enable signal is coupled to the data selection end of MUX, the another input end of MUX is connected to the output terminal of register, synchronous asserts signal is connected to or door first input end, the output terminal of MUX is connected to or the second input end of door, by or the output terminal of door be connected to the input end of register.
7. a kind of integrated circuit of optimizing register control signal as claimed in claim 1, it is characterized in that, described control signal is enable signal, synchronous reset signal and synchronous asserts signal, described combinational logic comprise MUX or door, not gate and with door; Enable signal is coupled to the input end of MUX, the another input end of MUX is connected to the output terminal of register, synchronous asserts signal is connected to or door first input end, the output terminal of MUX be connected to or door the second input end, by synchronous reset signal through the non-first input end being connected to behind the door with door, by or the output terminal of door be connected to the second input end with door, be connected to the input end of register with the output terminal of door.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320514529.6U CN203520396U (en) | 2013-08-22 | 2013-08-22 | Integrated circuit for optimizing control signals of registers |
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| CN201320514529.6U CN203520396U (en) | 2013-08-22 | 2013-08-22 | Integrated circuit for optimizing control signals of registers |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017113058A1 (en) * | 2015-12-28 | 2017-07-06 | 京微雅格（北京）科技有限公司 | Fpga chip wiring method based on plb |
| CN109581207A (en) * | 2018-12-19 | 2019-04-05 | 天津大学 | Low-cost circuit state control method for fault injection attack hardware simulation |
| CN110018654A (en) * | 2019-03-19 | 2019-07-16 | 中科亿海微电子科技（苏州）有限公司 | Fine granularity programmable timing sequence control logic module |
| CN112653445A (en) * | 2020-12-03 | 2021-04-13 | 北京博雅慧视智能技术研究院有限公司 | Digital logic circuit and electronic equipment |
-
2013
- 2013-08-22 CN CN201320514529.6U patent/CN203520396U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017113058A1 (en) * | 2015-12-28 | 2017-07-06 | 京微雅格（北京）科技有限公司 | Fpga chip wiring method based on plb |
| CN109581207A (en) * | 2018-12-19 | 2019-04-05 | 天津大学 | Low-cost circuit state control method for fault injection attack hardware simulation |
| CN109581207B (en) * | 2018-12-19 | 2020-12-11 | 天津大学 | Low-cost circuit state control method for fault injection attack hardware simulation |
| CN110018654A (en) * | 2019-03-19 | 2019-07-16 | 中科亿海微电子科技（苏州）有限公司 | Fine granularity programmable timing sequence control logic module |
| CN110018654B (en) * | 2019-03-19 | 2021-09-14 | 中科亿海微电子科技（苏州）有限公司 | Fine-grained programmable sequential control logic module |
| CN112653445A (en) * | 2020-12-03 | 2021-04-13 | 北京博雅慧视智能技术研究院有限公司 | Digital logic circuit and electronic equipment |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140402 Termination date: 20160822 |