CN110018654B - Fine-grained programmable sequential control logic module - Google Patents

Fine-grained programmable sequential control logic module Download PDF

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CN110018654B
CN110018654B CN201910207604.6A CN201910207604A CN110018654B CN 110018654 B CN110018654 B CN 110018654B CN 201910207604 A CN201910207604 A CN 201910207604A CN 110018654 B CN110018654 B CN 110018654B
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programmable
register
clock
logic
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CN110018654A (en
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高丽江
韦援丰
夏金军
蔡刚
魏育成
杨海钢
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Ehiway Microelectronic Science And Technology Suzhou Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24215—Scada supervisory control and data acquisition

Abstract

A fine-grained programmable timing control logic module, comprising: and the programmable clock module is positioned on the internal clock path of the register in each programmable logic unit, and under the condition that a certain register does not meet the setup time and/or the hold time, the programmable clock module of the internal clock path performs delay compensation on the register corresponding to the occurrence condition so as to meet the setup time and/or the hold time. The fine-grained programmable sequential control logic module realizes fine-grained programmability of each programmable logic unit, has good flexibility, meets the sequential requirements of a user circuit, reduces the failure rate caused by the fact that the set-up time and/or the hold time are not met, and improves the performance and the stability of a circuit system.

Description

Fine-grained programmable sequential control logic module
Technical Field
The disclosure belongs to the technical field of digital integrated circuits, and relates to a fine-grained programmable sequential control logic module.
Background
The FPGA is a universal logic circuit, and is called three general signal processing devices together with a CPU and a DSP. The method has the advantages of high flexibility, high parallelism and low development risk, is widely applied to the fields of industrial control, aerospace, communication, automotive electronics, data centers, intelligent processing and the like, and occupies more and more market shares. As a programmable device, the FPGA is composed of a programmable Logic module (CLB), a programmable interconnect resource (RR), a programmable input output module (Reconfigurable IO module), an embedded IP (Block memory, DSP, etc.), and the like. The programmable logic module is the core of the FPGA, and the general logic functions in the user circuit are realized by configuring the CLB. And the CLB is composed of a programmable Logic Element (BLE). Therefore, the research on the flexible and efficient BLE structure has important significance for improving the function and performance of the FPGA. The main functions of the programmable logic units in the FPGA are to provide the most basic logic functions, arithmetic functions, data storage functions, etc. for the digital system. Researchers have proposed a variety of BLE implementation structures, including those based on pass tubes, nand gates, multiplexers, look-up tables, and nand cones. Considering the factors of area, speed, power consumption and realizing function comprehensively, the current FPGA generally adopts a programmable logic unit based on a lookup table structure.
Integrated circuits can be divided into synchronous circuits and asynchronous circuits, the difference being whether or not there is a clock signal that uniformly controls the operation of the circuit. In the design of the synchronous circuit, the clock period depends on the delay of the critical path, and further determines the highest clock frequency which the circuit can work, and whether the circuit can work normally depends on whether the holding time is met. Because the clock path delay of the FPGA chip is fixed, the uncertainty of the clock skew at different positions makes it difficult to satisfy the setup and hold time constraints by using the inherent clock skew.
Besides, the programmable logic block LC is generally formed by a plurality of programmable logic units BLE, which often share a clock, while considering that the registers of the programmable logic units often are the same rising edge triggered registers. When a user needs part of BLE to be triggered by rising and part of BLE to be triggered by falling edges, the two parts of BLE need to be packed into different LCs, and the limitation condition is more.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a fine-grained programmable sequential control logic module to at least partially solve the above-mentioned technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a fine-grained programmable timing control logic module, comprising:
and the programmable clock module is positioned on the internal clock path of the register in each programmable logic unit, and under the condition that the register in a certain programmable logic unit does not meet the setup time and/or the hold time, the programmable clock module of the internal clock path performs delay compensation on the register in the corresponding occurrence condition so as to meet the setup time and/or the hold time.
In some embodiments of the disclosure, the programmable clock module comprises: the programmable delay units respectively correspond to respective clocks; and the input end of the multiplexer is connected with the outputs of the programmable delay units, and the output end of the multiplexer is connected with the clock signal input end of the register in the corresponding programmable logic unit.
In some embodiments of the disclosure, the input terminal of the multiplexer is further connected to the forward direction and the reverse direction of the clock corresponding to the plurality of programmable delay units at the same time.
In some embodiments of the present disclosure, when a falling edge triggered register is required, a corresponding inverted connected clock signal is input to the clock signal input of the register.
In some embodiments of the present disclosure, when the timing of a certain programmable logic unit does not meet the design requirement, the delays of other programmable logic units are not changed, and the programmable clock module on the internal clock path corresponding to the programmable logic unit that does not meet the design requirement provides a proper first delay to compensate so that the programmable clock module meets the timing requirement.
In some embodiments of the disclosure, when the data transmission is too fast and the holding time cannot be met, the programmable clock module on the internal clock path corresponding to the transmission register provides a suitable second delay to delay the transmission of the data to meet the timing requirement.
In some embodiments of the present disclosure, the register is controlled by the synchronous clear signal, the asynchronous clear signal, the synchronous set signal, and the asynchronous set signal simultaneously.
In some embodiments of the present disclosure, each programmable logic unit comprises: the k input function generation unit is used for realizing any logic operation of k inputs, and k is more than or equal to 2; and a register for implementing data registration in sequential logic; the k input function generation unit realizes arbitrary logical operation of k inputs in the form of a look-up table.
In some embodiments of the present disclosure, the control terminal of the register is provided with a logic gate controlled by the SRAM to mask unwanted control signals.
In some embodiments of the present disclosure, when a programmable logic unit (plc) is located in a plurality of programmable logic units (plc) in the same configurable logic unit (CLB), the programmable logic unit does not need to be controlled by the first control signal, and the programmable logic unit is shielded by the first control signal through the logic gate.
(III) advantageous effects
According to the technical scheme, the fine-grained programmable sequential control logic module provided by the disclosure has the following beneficial effects:
1. by inserting the corresponding programmable delay units into the internal clock path of each programmable logic unit instead of inserting delay units with different sizes into the clock paths of the configurable logic units (CLBs) with a plurality of programmable logic units together when the setup time and/or the hold time are not satisfied, the circuit timing can satisfy the setup time and/or the hold time by compensating the path delay or increasing the relative delay between the registers, thereby solving the problem that the inherent clock skew is difficult to satisfy the constraint of the setup hold time due to the fixed clock path delay of the FPGA chip and the uncertainty of the clock skew at different positions in the prior art, having good flexibility, satisfying the timing requirement of the user circuit, and reducing the failure rate caused by the unsatisfied setup time and/or hold time, the performance and stability of the circuit system are improved.
2. Through the arrangement that the input end of the multiplexer is simultaneously connected with the forward direction and the reverse direction of the clock corresponding to the plurality of programmable delay units, when a user needs to trigger part of BLE for rising and part of BLE for falling, the clock signal input end of the register is selected to input the inverted clock when the register triggered by the falling is needed, two parts of BLE do not need to be packaged into different LCs, the regulation and control are simple and efficient, and the structural grouping of the BLE does not need to be changed.
3. Through adding logic gates controlled by SRAM at the register control end of BLE (such as synchronous setting, asynchronous setting, synchronous resetting, asynchronous resetting and the like), unnecessary control signals are shielded, and finally the BLE can coexist in a configurable logic unit CLB together with other BLE controlled by the same clock enable signal (aclr signal), so that the area and cost caused by the complexity of structural separation setting are avoided.
Drawings
Fig. 1 is a block diagram of a typical programmable logic unit (BLE) in the prior art.
Fig. 2 is a schematic structural diagram of a fine-grained programmable timing control logic module according to a first embodiment of the disclosure.
FIG. 3 is a schematic diagram of a programmable clock module (PCLK) according to an embodiment of the disclosure.
Fig. 4 is a schematic structural diagram of a programmable delay unit (PD) according to an embodiment of the present disclosure.
Fig. 5 shows a corresponding circuit configuration of an embodiment of a programmable delay unit (PD) according to an example of the present disclosure.
Fig. 6 shows a circuit structure corresponding to a second embodiment of the programmable delay unit (PD) according to an example of the present disclosure.
Fig. 7 is a circuit timing diagram corresponding to fig. 5.
Fig. 8 is a circuit timing diagram corresponding to fig. 6.
Fig. 9 is a schematic structural diagram of a fine-grained programmable timing control logic module according to a second embodiment of the disclosure.
[ notation ] to show
10-a programmable clock module;
11-a clock multiplexer;
12-a programmable delay element;
12A-a first programmable delay element; 12B-a second programmable delay element;
r1 — first register; r2 — second register;
r3 — third register; r4 — fourth register;
r5 — fifth register; r6-sixth register.
Detailed Description
Fig. 1 is a block diagram of a typical programmable logic unit (BLE) in the prior art. Referring to FIG. 1, a typical BLE includes a k-input function generation unit (k ≧ 2) and a register. Wherein the k input function generation unit implements arbitrary logical operations of k inputs, typically using a form of a look-up table; the register is used for realizing data register in sequential logic. BLE has basic functional modes including logical mode, arithmetic mode, timing mode, etc.
The invention provides a fine-grained programmable sequential control logic module, which is characterized in that a corresponding programmable delay unit is inserted into an internal clock path of each programmable logic unit instead of a clock common path of a configurable logic unit (CLB) formed by combining a plurality of programmable logic units, delay units with different sizes can be respectively inserted into clock paths which correspondingly cause problems when the set-up time and/or the holding time are not satisfied, so that the path delay is compensated or the relative delay between registers is increased, the circuit timing satisfies the set-up time and/or the holding time, and the problem that the constraint of the set-up holding time is hardly satisfied by using the inherent clock deviation due to the fixed clock path delay of an FPGA chip and the uncertainty of the clock deviations at different positions in the prior art is solved.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings. In the whole text, the meaning of "not satisfying the establishment time and/or the retention time" means the condition that only the establishment time is not satisfied, or only the retention time is not satisfied, or both the establishment time and the retention time are not satisfied. The meaning of "A and/or B" means A or B or both A and B.
First embodiment
In a first exemplary embodiment of the present disclosure, a fine-grained programmable timing control logic module is provided.
Fig. 2 is a schematic structural diagram of a fine-grained programmable timing control logic module according to a first embodiment of the disclosure.
Referring to fig. 2, the fine-grained programmable sequential control logic module of the present disclosure includes: and the programmable clock module is positioned on the internal clock path of the register in each programmable logic unit, and under the condition that the register in a certain programmable logic unit does not meet the setup time and/or the hold time, the programmable clock module of the internal clock path performs delay compensation on the register in the corresponding occurrence condition so as to meet the setup time and/or the hold time.
In this embodiment, as shown in fig. 2, a structure of a programmable logic unit is illustrated, in which the programmable logic unit includes a k input function generation unit and a register, and a programmable clock module (PCLK)10 is connected to an internal clock path of the register. In this disclosure, a corresponding programmable clock module may be inserted on the internal clock path of each of the plurality of programmable logic units.
FIG. 3 is a schematic diagram of a programmable clock module (PCLK) according to an embodiment of the disclosure.
Referring to fig. 3, in this embodiment, the programmable clock module (PCLK)10 includes: the plurality of programmable delay units (PD) respectively correspond to respective clocks, in this embodiment, two paths of programmable delay units are illustrated, which are respectively a first programmable delay unit 12A and a second programmable delay unit 12B, and the corresponding clocks are respectively CLK0 and CLK 1; and a multiplexer (clkmux)11, an input terminal of which is connected to the outputs of the plurality of programmable delay units, and an output terminal of which is connected to the clock signal input terminal of the register in the corresponding programmable logic unit.
Fig. 4 is a schematic structural diagram of a programmable delay unit (PD) according to an embodiment of the present disclosure.
Referring to fig. 4, in the present embodiment, the clock of the programmable delay unit (PD)12 is CLK, and includes m delays, which are delay one, delay two, … …, delay m-1 and delay m, respectively, and m delay outputs are indicated by thick black lines and "m" in fig. 4.
Referring to fig. 3, the m delay outputs of each programmable delay unit are connected to the inputs of the multiplexer, so that the multiplexer (clkmux)11 selects the delay size for outputting according to the delay compensation required to be provided to the corresponding register.
In some embodiments of the disclosure, the input terminal of the multiplexer is further connected to the forward direction and the reverse direction of the clock corresponding to the plurality of programmable delay units at the same time.
In this embodiment, referring to fig. 3, the operations are specifically: two clock signals CLK0, CLK1 are connected to two positive inputs and two negative inputs of the multiplexer respectively to realize positive input and negative input of the clock.
In some embodiments of the present disclosure, when a register requiring falling edge triggering, a corresponding reversely connected clock signal is input to a clock signal input terminal of the register requiring falling edge triggering. And other registers needing rising edge triggering do not need to change the access direction of the clock signal and are not influenced. Therefore, through the arrangement that the input end of the multiplexer is simultaneously connected with the forward direction and the reverse direction of the clock corresponding to the plurality of paths of programmable delay units, when a user needs to trigger part of BLE for rising and part of BLE for falling, the reverse-phase clock is selected to be input to the clock signal input end of the register when the register needing falling is triggered, two parts of BLE do not need to be packaged into different LCs, regulation and control are simple and efficient, and structural grouping of BLE does not need to be changed.
In some embodiments of the present disclosure, the k-input function generation unit implements arbitrary logical operations of k inputs in the form of a look-up table.
In some embodiments of the present disclosure, the register is controlled by the synchronous clear signal, the asynchronous clear signal, the synchronous set signal, and the asynchronous set signal simultaneously.
Of course, the structure of the programmable clock module (PCLK)10 and the structure of the programmable delay unit (PD) are only examples, and any structure capable of implementing the above functions is within the scope of the disclosure.
Specific examples of the fine-grained programmable timing control logic module of the present embodiment that performs delay compensation to meet the setup time and/or hold time are described below with reference to fig. 5-8.
In some embodiments of the present disclosure, in the plurality of programmable logic units, when the timing of a certain programmable logic unit does not meet the design requirement, the delays of other programmable logic units are not changed, and the programmable clock module corresponding to the programmable logic unit that does not meet the design requirement provides a suitable first delay to compensate so that the programmable clock module meets the timing requirement.
Fig. 5 shows a corresponding circuit configuration of an embodiment of a programmable delay unit (PD) according to an example of the present disclosure. Fig. 7 is a circuit timing diagram corresponding to fig. 5.
For example, in one example shown in FIG. 5, assuming a clock signal period of T, in the following three registers: a first combinational logic I and a second combinational logic II exist between the first register R1 and the second register R2, and between the second register R2 and the third register R3, and the corresponding time delay of the first combinational logic I and the second combinational logic II is Tdata1、Tdata2And the corresponding programmable clock module is connected to the clock path corresponding to each register. Referring to the timing diagram of the circuit shown in fig. 7, at the rising edge of the clock clk, the first register R1 experiences a delay tcqThe input data is connected with the output end of R1 and is delayed by Tdata1To DcaptureAnd t issetup+tcq+Tdata1> T. At this time, the second register R2 cannot register data in one clock cycle in which data of the first register R1 is transferred to the second register R2 but is not registered in the second register due to the establishment time not being satisfied, causing a problem. Based on the fine-grained programmable sequential control logic module, the delay delta 1 of the programmable delay unit corresponding to the second register R2 is utilized to meet tsetup+tcq+Tdata＞T＞tsetup+tcq+TdataΔ 1, in this case after a delay Δ 1Is connected to the clock terminal of the second register R2, when the second register R2 is able to clock D in one clock cyclecaptureAnd (7) registering. Therefore, the time sequence requirement of the user circuit is met, and the system performance is improved.
Wherein, the time delay tcqDelay from the clock effective edge of the register to the data output; t is tsetupThe setup time of the register, i.e. the minimum time required for the register to sample the data correctly, is the time before the arrival of the valid edge of the clock.
In some embodiments of the disclosure, in the plurality of programmable logic units, when the data transmission is too fast and the holding time cannot be met, the programmable clock module corresponding to the transmission register provides a suitable second delay to delay the transmission of the data to meet the timing requirement.
Fig. 6 shows a circuit structure corresponding to a second embodiment of the programmable delay unit (PD) according to an example of the present disclosure. Fig. 8 is a circuit timing diagram corresponding to fig. 6.
For example, in another example shown in fig. 6, assuming a clock signal period of T, in the following three registers: a combinational logic three and a combinational logic four exist between the fourth register R4 and the fifth register R5 and between the fifth register R5 and the sixth register R6 respectively, and the corresponding time delay of the combinational logic three and the combinational logic four is T respectivelydata3、Tdata4And a corresponding programmable clock module is connected to the clock path corresponding to each register, and the access direction of the clock in the example is opposite to that of the previous example. Referring to the timing diagram of the circuit shown in fig. 7, at the rising edge of the clock clk, the fourth register R4 experiences a delay tcqThe input data is connected to the output of the fourth register R4 through a combinational logic three-delay Tdata3To DcaptureAnd t iscq+Tdata1＜Thold. At this point, the fifth register R5 will not be able to meet the hold time due to too fast a data transfer, and the function will be in error. Based on the fine-grained programmable sequential control logic module, the delay delta 3 of the programmable delay unit corresponding to the fourth register R4 is utilized to meet tcq+Tdata1＞TholdΔ 3, the clock signal delayed by Δ 3 is connected to the clock terminal of the fourth register R4, and the fourth register R4 can delay the transmission of data to meet the hold time, thereby meeting the timing requirement of the user circuit.
Wherein, the time delay tcqThe meaning is the same as above; t is tho1dThe hold time of a register, i.e. the minimum time a register needs to sample data correctly for the data to be maintained after a clock active edge.
Second embodiment
In a second exemplary embodiment of the present disclosure, a fine-grained programmable timing control logic module is provided. The fine-grained programmable sequential control logic module of the embodiment is further optimally set on the basis of the first embodiment.
Fig. 9 is a schematic structural diagram of a fine-grained programmable timing control logic module according to a second embodiment of the disclosure.
Referring to fig. 9, in this embodiment, based on the structure of the first embodiment, a logic gate is provided at the control end of the register, and the logic gate is controlled by the SRAM to shield unnecessary control signals.
In this embodiment, the register is simultaneously controlled by the synchronous clear signal, the asynchronous clear signal, the synchronous count signal, and the asynchronous count signal.
In some embodiments of the present disclosure, when a programmable logic unit (plc) is located in a plurality of programmable logic units (plc) in the same configurable logic unit (CLB), the programmable logic unit does not need to be controlled by the first control signal, and the programmable logic unit is shielded by the first control signal through the logic gate.
For example, the clock enable signal (aclr) is taken as an asynchronous clear signal for description. When the present BLE does not need the asynchronous clear signal and other BLE installed in the same CLB need the signal, the control signal can be shielded by the SRAM through the logic gate (and gate or gate), so that the present BLE and other BLE controlled by the asynchronous clear signal aclr signal can coexist in one CLB. Specifically selecting an AND gate or an OR gate, wherein the selection needs to be determined according to the effective level of the control signal, and when the effective level is high, the selection is performed on the AND gate; when the active level is low, the or gate is selected.
According to the optimized embodiment, logic gates controlled by SRAM are added at the register control end of BLE (such as synchronous setting, asynchronous setting, synchronous resetting, asynchronous resetting and the like) to shield unnecessary control signals, and finally the BLE can coexist in a configurable logic unit CLB together with other BLE controlled by the same clock enable signal (aclr signal), so that the area and cost caused by the complexity of structural separation are avoided.
In summary, the present disclosure provides a fine-grained programmable timing control logic module, where a corresponding programmable delay unit is inserted into an internal clock path of each programmable logic unit, instead of a clock common path of a configurable logic unit (CLB) where a plurality of programmable logic units are integrated, delay units with different sizes can be respectively inserted into clock paths that have problems when setup time and/or hold time are not satisfied, so as to compensate path delay or increase relative delay between registers, so that a circuit timing meets setup time and/or hold time, and solve the problem in the prior art that it is difficult to satisfy the constraint of setup hold time by using inherent clock skew due to the fact that clock path delay of an FPGA chip is fixed and uncertainty of clock skew at different positions, and the fine-grained programmable timing control logic module implements fine-grained programmable timing control of each programmable logic unit The method has good flexibility, meets the time sequence requirement of a user circuit, reduces the failure rate caused by the fact that the establishment time and/or the retention time are not met, and improves the performance and the stability of a circuit system. Through the arrangement that the input end of the multiplexer is simultaneously connected with the forward direction and the reverse direction of the clock corresponding to the plurality of programmable delay units, when a user needs to trigger part of BLE for rising and part of BLE for falling, the clock signal input end of the register is selected to input the inverted clock when the register triggered by the falling is needed, two parts of BLE do not need to be packaged into different LCs, the regulation and control are simple and efficient, and the structural grouping of the BLE does not need to be changed. Through adding logic gates controlled by SRAM at the register control end of BLE (such as synchronous setting, asynchronous setting, synchronous resetting, asynchronous resetting and the like), unnecessary control signals are shielded, and finally the BLE can coexist in a configurable logic unit CLB together with other BLE controlled by the same clock enable signal (aclr signal), so that the area and cost caused by the complexity of structural separation setting are avoided.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (8)

1. A fine-grained programmable sequential control logic module, comprising:
the programmable clock module is positioned on the internal clock path of the register in each programmable logic unit, under the condition that the register in a certain programmable logic unit does not meet the setup time and/or the hold time, the programmable clock module of the internal clock path carries out delay compensation on the register in the corresponding occurrence condition so as to meet the setup time and/or the hold time,
the programmable clock module comprises:
the programmable delay units respectively correspond to respective clocks; and
the input end of the multiplexer is connected with the outputs of the programmable delay units, the output end of the multiplexer is connected with the clock signal input end of the register in the corresponding programmable logic unit, and the input end of the multiplexer is simultaneously connected with the forward direction and the reverse direction of the clock corresponding to the programmable delay units.
2. The fine grain programmable timing control logic module of claim 1, wherein when a falling edge triggered register is required, a corresponding reverse connected clock signal is input to a clock signal input terminal of the falling edge triggered register.
3. The fine-grained programmable sequential control logic module according to claim 1, wherein when the timing of a programmable logic unit does not meet the design requirements, the delays of other programmable logic units are not changed, and the programmable clock module on the internal clock path corresponding to the programmable logic unit that does not meet the design requirements provides a proper first delay to compensate so that the programmable clock module meets the timing requirements.
4. The fine-grained programmable timing control logic module according to claim 1, wherein the programmable clock module on the internal clock path corresponding to the transmission register provides a second delay suitable for delaying transmission of data to meet timing requirements when the data transmission is too fast and the hold time cannot be met.
5. The fine grain programmable timing control logic module of claim 1 wherein the registers are simultaneously controlled by a synchronous clear signal, an asynchronous clear signal, a synchronous set signal, and an asynchronous set signal.
6. The fine-grained programmable sequential control logic module according to claim 1, wherein each programmable logic cell comprises: the k input function generation unit is used for realizing any logic operation of k inputs, and k is more than or equal to 2; and a register for implementing data registration in sequential logic; the k input function generation unit realizes arbitrary logical operation of k inputs in the form of a look-up table.
7. The fine-grained programmable sequential control logic module according to any one of claims 1 to 6, characterized in that the control terminal of the register is provided with a logic gate controlled by an SRAM to mask out unwanted control signals.
8. The fine-grained programmable sequential control logic module according to claim 7, wherein when one programmable logic cell does not require control of the first control signal among a plurality of programmable logic cells located in the same configurable logic cell, the programmable logic cell is shielded by the first control signal using the logic gate.
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