CN110018654A - Fine granularity programmable timing sequence control logic module - Google Patents
Fine granularity programmable timing sequence control logic module Download PDFInfo
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- CN110018654A CN110018654A CN201910207604.6A CN201910207604A CN110018654A CN 110018654 A CN110018654 A CN 110018654A CN 201910207604 A CN201910207604 A CN 201910207604A CN 110018654 A CN110018654 A CN 110018654A
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
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Abstract
A kind of fine granularity programmable timing sequence control logic module, it include: programmable clock module, on the internal clocking path of register in each programmable logic cells, in the case where some register is unsatisfactory for settling time and/or retention time, the programmable clock module in internal clocking path makees compensation of delay to the corresponding register that a situation arises to meet settling time and/or retention time.The fine granularity programmable timing sequence control logic module realizes programmable to the fine granularity of each programmable logic cells, with good flexibility, meet the timing requirements of subscriber's line circuit, reduce the performance and its stability that circuit system is improved since settling time and/or retention time are unsatisfactory for caused failure rate.
Description
Technical field
The disclosure belongs to digital integrated circuit technology field, is related to a kind of fine granularity programmable timing sequence control logic module.
Background technique
FPGA is a kind of general logic circuit, with CPU, DSP and referred to as three big general purpose signal processor parts.With flexible
Property high, concurrency is high, development risk is low advantage, be widely used in Industry Control, aerospace, communication, automotive electronics,
The fields such as data center, Intelligent treatment, and in occupation of more and more market shares.As a kind of programming device, FPGA
By programmed logical module (Configurable Logic Block, CLB), programmable interconnection resource (Reconfigurable
Routing, RR), programmable input/output module (Reconfiguable IO module), embedded IP (block storage, DSP
Deng) etc. composition.Wherein programmed logical module is the core of FPGA, and the generic logic function in subscriber's line circuit, which will pass through, to be configured
CLB is realized.And CLB is made of programmable logic cells (Basic Logic Element, BLE).Therefore it studies flexible
Efficient BLE structure has great importance to the function and performance that promote FPGA.Programmable logic cells is main in FPGA
Function is that most basic logic function, arithmetic function, data storage function etc. are provided for digital display circuit.Researchers are it is proposed that mistake
A variety of BLE realize structures, including based on transfer tube, NAND gate, multiple selector, look-up table and structure with non-cone etc..It is comprehensive
Consider area, speed, power consumption and realize the factors such as function, what is generallyd use in FPGA at present is compiling based on look-up table configuration
Journey logic unit.
Integrated circuit can be divided into synchronous circuit and asynchronous circuit on implementation, and the difference of the two is whether there is
The clock signal that circuit work is uniformly controlled.In synchronous circuit design, the clock cycle depends on prolonging for critical path
When, further determine the workable maximum clock frequency of circuit institute, and can circuit work normally, and be depending on the retention time
No satisfaction.Since the clock path delay of fpga chip is fixed, and the uncertainty of the clock jitter of different location causes
Intrinsic clock jitter is difficult with to meet the constraint of foundation, retention time.
In addition to this, programmable logic block LC is generally made of multiple programmable logic cells BLE, and multiple may be programmed is patrolled
Unit often common clock is collected, while in view of the register of programmable logic cells is often same rising edge triggering deposit
Device.When user needs part BLE to rise triggering, when partially being triggered for failing edge, it is necessary to by this two parts BLE vanning to not
In same LC, restrictive condition is more.
Summary of the invention
(1) technical problems to be solved
Present disclose provides a kind of fine granularity programmable timing sequence control logic modules, set forth above at least partly to solve
The technical issues of.
(2) technical solution
According to one aspect of the disclosure, a kind of fine granularity programmable timing sequence control logic module is provided, comprising:
Programmable clock module, on the internal clocking path of register in each programmable logic cells, at some
In the case that register is unsatisfactory for settling time and/or retention time in programmable logic cells, internal clocking path is compiled
Journey clock module makees compensation of delay to the corresponding register that a situation arises to meet settling time and/or retention time.
In some embodiments of the present disclosure, which includes: if main line programmable delay unit, respectively
Corresponding respective clock；And multiple selector, if input terminal is connect with the output of main line programmable delay unit, output
End is connected to the clock signal input terminal of register in corresponding programmable logic cells.
In some embodiments of the present disclosure, if the input terminal of multiple selector is also corresponding with main line programmable delay unit
The forward and reverse of clock connect simultaneously.
In some embodiments of the present disclosure, in the register for needing failing edge to trigger, the clock of corresponding Opposite direction connection
Signal is input to the clock signal input terminal of register.
In some embodiments of the present disclosure, when the timing of some programmable logic cells is unsatisfactory for design requirement,
The delay of its programmable logic cells does not change, when corresponding internal by the programmable logic cells for being unsatisfactory for design requirement
Programmable clock module on clock path, which provides suitable first delay and compensates, makes it meet timing requirements.
In some embodiments of the present disclosure, when data transmission is too fast, when the retention time is unable to satisfy, transmitting register pair
Programmable clock module on the internal clocking path answered provides suitable second delay to postpone the transmitting of data to meet
Timing requirements.
In some embodiments of the present disclosure, register simultaneously by synchronous reset signal, asynchronous resetting signal, synchronize and set number
Signal and the asynchronous control for setting several signals.
In some embodiments of the present disclosure, each programmable logic cells include: that k input function generates unit, are used for
Realize any logical operation of k input, k >=2；And register, for realizing the data register in sequential logic；K input
Function generates any logical operation that unit realizes k input by searching for the form of table.
In some embodiments of the present disclosure, the control terminal of register is provided with logic gate, which is controlled by SRAM,
To shield unwanted control signal.
It is multiple programmable in the same configurable logic cell (CLB) when being located in some embodiments of the present disclosure
In logic unit, a certain programmable logic cells do not need the control of first control signal, using the logic gate realize this
Shielding of the one control signal to the programmable logic cells.
(3) beneficial effect
It can be seen from the above technical proposal that the fine granularity programmable timing sequence control logic module that the disclosure provides, has
Below the utility model has the advantages that
1, by being inserted into corresponding programmable delay unit in the internal clocking path of each programmable logic cells, without
It is that can established on the clock common path of the configurable logic cell (CLB) in multiple programmable logic cells together
When time and/or retention time are unsatisfactory for, delay unit not of uniform size is inserted into respectively to the clock path accordingly led to the problem of,
To compensate path delay or increase the relative time delay between register, when so that circuit sequence meeting settling time and/or keeps
Between, it solves in the prior art since the clock path delay of fpga chip is fixed, and the clock jitter of different location
Uncertainty causes to be difficult with intrinsic clock jitter to have good spirit the problem of meeting the constraint for establishing the retention time
Activity meets the timing requirements of subscriber's line circuit, reduces since settling time and/or retention time are unsatisfactory for caused failure
Rate improves the performance and its stability of circuit system.
If 2, passing through the forward and reverse of the input terminal of multiple selector clock corresponding with main line programmable delay unit
While the setting of connection, when user needs part BLE needing failing edge to touch when partially triggering for failing edge for rising triggering
It selects inversion clock to be input to the clock signal input terminal of the register when register of hair, does not need to case two parts BLE
Into different LC, regulation is easy and efficient, and the grouping of the structure without changing BLE.
3, by the register control terminal (such as synchronous set, asynchronous set, synchronous reset, asynchronous reset) in BLE, increase
Add the logic gate controlled by SRAM, to shield unwanted control signal, enables this BLE with by same clock
Other BLE of signal (aclr signal) control are coexisted in a configurable logic cell CLB, are avoided and are separated setting in structure
Complexity thus bring area and cost.
Detailed description of the invention
Fig. 1 is the structural block diagram of typical programmable logic unit (BLE) in the prior art.
Fig. 2 is the structural representation of the fine granularity programmable timing sequence control logic module according to shown in the first embodiment of the present disclosure
Figure.
Fig. 3 is the structural schematic diagram of the programmable clock module (PCLK) according to shown in one embodiment of the disclosure.
Fig. 4 is the structural schematic diagram of the programmable delay unit (PD) according to shown in one embodiment of the disclosure.
Fig. 5 is the corresponding circuit knot of embodiment one of the programmable delay unit (PD) according to shown in one example of the disclosure
Structure.
Fig. 6 is the corresponding circuit knot of embodiment two of the programmable delay unit (PD) according to shown in one example of the disclosure
Structure.
Fig. 7 is circuit timing diagram corresponding with Fig. 5.
Fig. 8 is circuit timing diagram corresponding with Fig. 6.
Fig. 9 is the structural representation of the fine granularity programmable timing sequence control logic module according to shown in the second embodiment of the present disclosure
Figure.
[symbol description]
10- programmable clock module；
11- clock multiple selector；
12- programmable delay unit；
12A- the first programmable delay unit；12B- the second programmable delay unit；
The first register of R1-；The second register of R2-；
R3- third register；The 4th register of R4-；
The 5th register of R5-；The 6th register of R6-.
Specific embodiment
Fig. 1 is the structural block diagram of typical programmable logic unit (BLE) in the prior art.Shown in referring to Fig.1, typically
BLE includes that a k input function generates unit (k >=2) and a register.Wherein it is usually used to generate unit for k input function
The form of look-up table come realize k input any logical operation；Register is used to realize the data register in sequential logic.
The basic function mode that BLE has includes logical schema, arithmetic mode, time series pattern etc..
The disclosure proposes a kind of fine granularity programmable timing sequence control logic module, by each programmable logic cells
Corresponding programmable delay unit is inserted into internal clocking path, rather than in multiple programmable logic cells together configurable
On the clock common path of logic unit (CLB), it can be generated when being unsatisfactory for settling time and/or retention time to corresponding
The clock path of problem is inserted into delay unit not of uniform size respectively, to compensate path delay or increase opposite between register
Delay, so that circuit sequence meets settling time and/or retention time, solves the clock in the prior art due to fpga chip
Path delay is fixed, and the uncertainty of the clock jitter of different location causes to be difficult with intrinsic clock jitter to expire
The problem of foot establishes the constraint of retention time.
For the purposes, technical schemes and advantages of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
The disclosure is further described in attached drawing.Wherein, in full text, the meaning table of " being unsatisfactory for settling time and/or retention time "
Show that only settling time is unsatisfactory for, perhaps only the retention time be unsatisfactory for or settling time and the retention time it is all ungratified
Situation.The meaning of " A and/or B " indicates A or B or simultaneously A and B.
First embodiment
In first exemplary embodiment of the disclosure, a kind of fine granularity programmable timing sequence control logic mould is provided
Block.
Fig. 2 is the structural representation of the fine granularity programmable timing sequence control logic module according to shown in the first embodiment of the present disclosure
Figure.
Referring to shown in Fig. 2, the fine granularity programmable timing sequence control logic module of the disclosure, comprising: programmable clock module,
On the internal clocking path of register in each programmable logic cells, register is not in some programmable logic cells
In the case where meeting settling time and/or retention time, a situation arises to corresponding to for the programmable clock module in internal clocking path
Register make compensation of delay to meet settling time and/or retention time.
In the present embodiment, as shown in Fig. 2, the structure of a programmable logic cells is illustrated, in the programmable logic list
Unit and a register are generated comprising a k input function in member, being connected with one on the internal clocking path of register can
Mbus module (PCLK) 10.In the disclosure, on internal clocking path that can be each in multiple programmable logic cells
It is inserted into corresponding programmable clock module.
Fig. 3 is the structural schematic diagram of the programmable clock module (PCLK) according to shown in one embodiment of the disclosure.
Referring to shown in Fig. 3, in the present embodiment, which includes: if main line programmable delay
Unit (PD), respectively corresponds respective clock, in the present embodiment, is illustrated with two-way programmable delay unit, respectively
One programmable delay unit 12A and the second programmable delay unit 12B, corresponding clock is respectively CLK0 and CLK1；And it is more
Road selector (clkmux) 11, if input terminal is connect with the output of main line programmable delay unit, output end is connected to pair
The clock signal input terminal of register in the programmable logic cells answered.
Fig. 4 is the structural schematic diagram of the programmable delay unit (PD) according to shown in one embodiment of the disclosure.
Referring to shown in Fig. 4, in the present embodiment, the clock of programmable delay unit (PD) 12 is CLK, is delayed comprising the road m, point
Wei not be delayed one, delay two ..., the output that is delayed in delay m-1 and delay m, Fig. 4 with heavy black and the illustrated road m " m ".
Referring to shown in Fig. 3, the road the m delay output end of each programmable delay unit accesses to the input of multiple selector
End, so that multiple selector (clkmux) 11 carries out delay size to the compensation of delay that corresponding register provides as needed
Selection is exported.
In some embodiments of the present disclosure, if the input terminal of multiple selector is also corresponding with main line programmable delay unit
The forward and reverse of clock connect simultaneously.
In the present embodiment, referring to shown in Fig. 3, concrete operations are as follows: two-way clock signal clk 0, CLK1 are separately connected multichannel choosing
Two positive inputs and two reverse input ends for selecting device realize the positive input and reversed input of clock.
In some embodiments of the present disclosure, in the register for needing failing edge to trigger, the clock of corresponding Opposite direction connection
Signal is input to the clock signal input terminal of the register of needs failing edge triggering.And other need posting for rising edge triggering
Storage does not have to the access direction of change clock signal, unaffected.If therefore can by the input terminal of multiple selector and main line
The setting that the forward and reverse of the corresponding clock of delay unit connects simultaneously is programmed, is to rise triggering when user needs part BLE,
When part is failing edge triggering, in the register for needing failing edge to trigger, selection inversion clock is input to the clock letter of register
Number input terminal does not need to case two parts BLE into different LC, and regulation is easy and efficiently, and the structure without changing BLE
Grouping.
In some embodiments of the present disclosure, k input function generates unit and realizes k input by searching for the form of table
Any logical operation.
In some embodiments of the present disclosure, register simultaneously by synchronous reset signal, asynchronous resetting signal, synchronize and set number
Signal and the asynchronous control for setting several signals.
Certainly, the structure of above-mentioned programmable clock module (PCLK) 10, the structure of programmable delay unit (PD) are only made
For example, any structure that can be realized above-mentioned function is within the protection scope of the disclosure.
Figure 5-8 introduces the progress of the fine granularity programmable timing sequence control logic module in the present embodiment with reference to the accompanying drawing
Compensation of delay is to meet the specific example of settling time and/or retention time.
In some embodiments of the present disclosure, in multiple programmable logic cells, when some programmable logic cells
When timing is unsatisfactory for design requirement, the delay of other programmable logic cells does not change, by this be unsatisfactory for design requirement can
The corresponding programmable clock module of programmed logic unit, which provides suitable first delay and compensates, makes it meet timing requirements.
Fig. 5 is the corresponding circuit knot of embodiment one of the programmable delay unit (PD) according to shown in one example of the disclosure
Structure.Fig. 7 is circuit timing diagram corresponding with Fig. 5.
For example, in an example shown in Fig. 5, it is assumed that clock signal period T, in following three register: first
Combinational logic one, combination are respectively present between register R1 and the second register R2, the second register R2 and third register R3
Logic two, the combinational logic one and the corresponding delay of combinational logic two are respectively Tdata1、Tdata2, corresponding in each register
Corresponding programmable clock module is connected on clock path.Referring to shown in circuit timing diagram shown in Fig. 7, clock clk's
Rising edge time, the first register R1 is by delay tcqBy the output end of input data connection R1, it is delayed by combinational logic one
Tdata1Reach Dcapture, and tsetup+tcq+Tdata1> T.The second register R2 cannot be within a clock cycle by data at this time
Deposit, within the clock cycle, due to being unsatisfactory for settling time, the data of the first register R1 reach the second register R2 still
It is not deposited in the second register, leads to the problem of.Fine granularity programmable timing sequence control logic module based on the application, benefit
With the delay Δ 1 of the corresponding programmable delay unit of the second register R2, it is made to meet tsetup+tcq+Tdata> T > tsetup+tcq
+TdataΔ 1, at this point, the clock signal after the Δ 1 that is delayed is connected to the clock end of the second register R2, the second deposit at this time
Device R2 can be within a clock cycle by DcaptureDeposit.In this way, meet the timing requirements of subscriber's line circuit, improve
System performance.
Wherein, be delayed tcqThe delay exported for the clock effective edge edge of register to data；tsetupFor the foundation of register
Time, i.e. register want correct sampled data that data is needed to shift to an earlier date clock effective edge along the minimum time reached.
In some embodiments of the present disclosure, in multiple programmable logic cells, when data transmit too fast, the retention time
When being unable to satisfy, the corresponding programmable clock module of transmitting register provides suitable second delay to postpone the transmitting of data
To meet timing requirements.
Fig. 6 is the corresponding circuit knot of embodiment two of the programmable delay unit (PD) according to shown in one example of the disclosure
Structure.Fig. 8 is circuit timing diagram corresponding with Fig. 6.
For example, in another example shown in Fig. 6, it is assumed that clock signal period T, in following three register: the
Combinational logic three, group are respectively present between four register R4 and the 5th register R5, the 5th register R5 and the 6th register R6
Logical four, the combinational logic three and the corresponding delay of combinational logic four are respectively Tdata3、Tdata4, answered in each register pair
Clock path on be connected with corresponding programmable clock module, in the example, the access direction of clock and an example above
It is contrary.Referring to shown in circuit timing diagram shown in Fig. 7, in the rising edge time of clock clk, the 4th register R4 passes through
Be delayed tcqThe output end that input data is connected to the 4th register R4, by the delay of combinational logic three Tdata3Reach Dcapture, and
tcq+Tdata1< Thold.At this time since data transmission is too fast, the 5th register R5 will be unable to meet the retention time, and function will malfunction.
Fine granularity programmable timing sequence control logic module based on the application, utilizes the corresponding programmable delay unit of the 4th register R4
Delay Δ 3, so that it is met tcq+Tdata1> TholdClock signal after the Δ 3 that is delayed is connected to the 4th register R4 by Δ 3
Clock end, the 4th register R4 can postpone the transmitting of data at this time, to meet the retention time, to meet subscriber's line circuit
Timing requirements.
Wherein, be delayed tcqMeaning is same as above；tho1dFor the retention time of register, i.e. register wants correct sampled data needs
The minimum time that data maintain after in clock effective edge.
Second embodiment
In second exemplary embodiment of the disclosure, a kind of fine granularity programmable timing sequence control logic mould is provided
Block.The fine granularity programmable timing sequence control logic module of embodiment further progress on the basis of one embodiment is excellent
Change setting.
Fig. 9 is the structural representation of the fine granularity programmable timing sequence control logic module according to shown in the second embodiment of the present disclosure
Figure.
Referring to shown in Fig. 9, in the present embodiment, based on the structure of one embodiment, it is provided in the control terminal of register
Logic gate, the logic gate are controlled by SRAM, to shield unwanted control signal.
In the present embodiment, register simultaneously by synchronous reset signal, asynchronous resetting signal, synchronize and set several signals and asynchronous set
The control of number signal.
It is multiple programmable in the same configurable logic cell (CLB) when being located in some embodiments of the present disclosure
In logic unit, a certain programmable logic cells do not need the control of first control signal, using the logic gate realize this
Shielding of the one control signal to the programmable logic cells.
For example, being introduced so that clock enable signal (aclr) is asynchronous resetting signal as an example.When this BLE do not need it is asynchronous
Reset signal, and when other BLE for being attached to the same CLB need this signal, can by SRAM by logic gate (with door or
Or door) signal shielding will be controlled, finally allow this BLE and other BLE controlled by asynchronous resetting signal aclr signal total
It is stored in a CLB.Wherein, specific choice and door or or door, need to be determined according to the significant level of the control signal, when having
When effect level is high, selection and door；When significant level is low, selection or door.
The optimal enforcement example passes through register control terminal (such as the synchronous set, asynchronous set, synchronous reset, asynchronous in BLE
Reset etc.), increase the logic gate that is controlled by SRAM, to shield unwanted control signal, finally allow this BLE with by same
Other BLE of one clock enable signal (aclr signal) control are coexisted in a configurable logic cell CLB, avoid structure
It is upper to separate the complexity being arranged thus bring area and cost.
In conclusion present disclose provides a kind of fine granularity programmable timing sequence control logic module, by being compiled each
Corresponding programmable delay unit is inserted into the internal clocking path of journey logic unit, rather than is existed in multiple programmable logic cells
On the clock common path of configurable logic cell (CLB) together, it can be unsatisfactory in settling time and/or retention time
When, delay unit not of uniform size is inserted into the clock path accordingly led to the problem of respectively, is posted with compensating path delay or increasing
Relative time delay between storage so that circuit sequence meets settling time and/or retention time, solve in the prior art due to
The clock path delay of fpga chip is fixed, and the uncertainty of the clock jitter of different location causes to be difficult with inherently
Clock jitter come the problem of meeting the constraint for establishing the retention time, which is realized
It is programmable to the fine granularity of each programmable logic cells, there is good flexibility, meet the timing requirements of subscriber's line circuit,
Reduce the performance that circuit system is improved since settling time and/or retention time are unsatisfactory for caused failure rate and its steady
It is qualitative.If being connected simultaneously by the forward and reverse of the input terminal of multiple selector clock corresponding with main line programmable delay unit
The setting connect when partially triggering for failing edge, is needing posting for failing edge triggering when user needs part BLE to rise triggering
It selects inversion clock to be input to the clock signal input terminal of the register when storage, does not need to case two parts BLE to difference
LC in, regulation is easy and efficiently, and the grouping of the structure without changing BLE.By the register control terminal in BLE (as synchronized
Set, asynchronous set, synchronous reset, asynchronous reset etc.), increase the logic gate controlled by SRAM, to shield unwanted control
Signal, finally allowing this BLE to coexist in one with the other BLE controlled by same clock enable signal (aclr signal) can
In configuration logic unit CLB, avoids and separate the complexity of setting thus bring area and cost in structure.
Similarly, it should be understood that in order to simplify the disclosure and help to understand one or more of each open aspect,
Above in the description of the exemplary embodiment of the disclosure, each feature of the disclosure is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the disclosed method should not be interpreted as reflecting the following intention: i.e. required to protect
The disclosure of shield requires features more more than feature expressly recited in each claim.More precisely, as following
Claims reflect as, open aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following specific embodiment are expressly incorporated in the specific embodiment, wherein each claim itself
All as the separate embodiments of the disclosure.
Particular embodiments described above has carried out further in detail the purpose of the disclosure, technical scheme and beneficial effects
Describe in detail it is bright, it is all it should be understood that be not limited to the disclosure the foregoing is merely the specific embodiment of the disclosure
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of fine granularity programmable timing sequence control logic module characterized by comprising
Programmable clock module can be compiled on the internal clocking path of register in each programmable logic cells at some
In the case that register is unsatisfactory for settling time and/or retention time in journey logic unit, internal clocking path it is programmable when
Clock module makees compensation of delay to the corresponding register that a situation arises to meet settling time and/or retention time.
2. fine granularity programmable timing sequence control logic module according to claim 1, which is characterized in that the programmable clock
Module includes:
If main line programmable delay unit, respectively corresponds respective clock；And
Multiple selector, if input terminal is connect with the output of main line programmable delay unit, output end is connected to corresponding
The clock signal input terminal of register in programmable logic cells.
3. fine granularity programmable timing sequence control logic module according to claim 2, which is characterized in that the multi-path choice
If the forward and reverse of the input terminal of device clock also corresponding with main line programmable delay unit connects simultaneously.
4. fine granularity programmable timing sequence control logic module according to claim 3, which is characterized in that needing failing edge
When the register of triggering, the clock signal of corresponding Opposite direction connection is input to the clock letter of the register of needs failing edge triggering
Number input terminal.
5. fine granularity programmable timing sequence control logic module according to claim 1, which is characterized in that when some is programmable
When the timing of logic unit is unsatisfactory for design requirement, the delay of other programmable logic cells does not change, and is unsatisfactory for setting by this
The programmable clock module offer one suitable first counted on the desired corresponding internal clocking path of programmable logic cells is prolonged
When compensate it made to meet timing requirements.
6. fine granularity programmable timing sequence control logic module according to claim 1, which is characterized in that when data are transmitted too
Fastly, when the retention time is unable to satisfy, the programmable clock module on the corresponding internal clocking path of transmitting register provides one and closes
The second suitable delay is to postpone the transmitting of data to meet timing requirements.
7. fine granularity programmable timing sequence control logic module according to claim 1, which is characterized in that the register is same
When by synchronous reset signal, asynchronous resetting signal, synchronize and set several signals and the asynchronous control for setting several signals.
8. fine granularity programmable timing sequence control logic module according to claim 1, which is characterized in that each may be programmed is patrolled
Collecting unit includes: that k input function generates unit, any logical operation inputted for realizing k, k >=2；And register, it uses
Data register in realization sequential logic；The k input function generates unit and realizes k input by searching for the form of table
Any logical operation.
9. fine granularity programmable timing sequence control logic module according to any one of claim 1 to 8, which is characterized in that
The control terminal of the register is provided with logic gate, which is controlled by SRAM, to shield unwanted control signal.
10. fine granularity programmable timing sequence control logic module according to claim 9, which is characterized in that same when being located at
In multiple programmable logic cells in a configurable logic cell, a certain programmable logic cells do not need first control signal
Control when, realize shielding of the first control signal to the programmable logic cells using the logic gate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112732620A (en) * | 2021-01-12 | 2021-04-30 | 安徽省东科半导体有限公司 | Signal relay method of physical layer logic module based on pipeline register |
| CN113792520A (en) * | 2021-09-23 | 2021-12-14 | 西安紫光国芯半导体有限公司 | Layout wiring method, layout wiring device, synchronous circuit and integrated circuit chip |
| CN115276613A (en) * | 2022-08-05 | 2022-11-01 | 珠海錾芯半导体有限公司 | Integrated circuit based on edge trigger and sensitive latch and programmable circuit thereof |
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