CN112732620A - Signal relay method of physical layer logic module based on pipeline register - Google Patents

Signal relay method of physical layer logic module based on pipeline register Download PDF

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CN112732620A
CN112732620A CN202110036465.2A CN202110036465A CN112732620A CN 112732620 A CN112732620 A CN 112732620A CN 202110036465 A CN202110036465 A CN 202110036465A CN 112732620 A CN112732620 A CN 112732620A
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register
logic unit
signal
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CN112732620B (en
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赵少峰
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Anhui Dongke Semiconductor Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file

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Abstract

The embodiment of the invention relates to a signal relay method of a physical layer logic module based on a pipeline register, which comprises the following steps: determining the insertion stage number of a flow register required by signal synchronization of a first logic unit and a second logic unit with signal transmission in the same clock domain; determining the maximum offset of each stage of register according to the maximum transmission displacement of the signal in one clock cycle; determining a barrier blocking module according to a module boundary in a range with a signal output end of a previous stage as a central point and the maximum offset as a radius; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a residual path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placing position of the current stage register according to the shortest preset position of the residual path until the insertion of each stage of the pipeline register corresponding to the stage number is completed; the registers of each stage are wired in series to form a signal relay pipeline register.

Description

Signal relay method of physical layer logic module based on pipeline register
Technical Field
The invention relates to the technical field of microelectronics, in particular to a signal relay method of a physical layer logic module based on a pipeline register.
Background
In the Field Programmable Gate Array (FPGA) design, there is often a requirement of sequential logic for a module in a chip from input to output or from input to a register inside the module, and when the timing is not satisfied, the register is often inserted to implement clock synchronization between the front and the back.
However, in the existing design tool, the register is often blocked and cannot be automatically placed, and in such a case, the designer needs to manually place the register, which is time-consuming and labor-consuming.
Therefore, it is urgently needed to optimize the signal relay method of the design tool in the module so as to realize the signal relay of the physical layer logic module under various complex practical situations.
Disclosure of Invention
The invention aims to provide a signal relay method of a physical layer logic module based on a flow register, which can automatically identify and judge the optimal insertion position of the flow register between two physical layer logic modules and realize signal relay between the two physical layer logic modules through automatic insertion on the optimal insertion position.
To this end, an embodiment of the present invention provides a signal relaying method for a physical layer logic module based on a pipeline register, where the signal relaying method includes:
determining a first logic unit and a second logic unit with signal transmission under the same clock domain; the first logic unit and the second logic unit are two logic units to be synchronized by a clock; a straight line path from the output end of the first logic unit to the first input end of the second logic unit is an optimal path;
determining the insertion stage number of the flow register required by signal synchronization of the first logic unit and the second logic unit; each stage of the pipeline register comprises one or a group of registers, all stages are connected in series, and each stage of the pipeline register is provided with a determined module boundary;
determining the maximum offset of each stage of register according to the maximum transmission displacement of the signal in one clock cycle;
determining a barrier blocking module according to a module boundary in a range with a signal output end of the first logic unit as a central point and the maximum offset as a radius; the type of the barrier module comprises macro cells or reserved vacancies; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a surplus path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placement position of the first-stage register according to the preset position with the shortest surplus path;
determining a barrier blocking module according to the module boundary within the range that the signal output end of the previous-stage register is a central point and the maximum offset is a radius; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a residual path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placing position of the current stage register according to the preset position with the shortest residual path until the placing position of each stage of the flow register corresponding to the insertion stage is determined;
and inserting and serially wiring registers at all levels according to the determined placing positions to form a flow register between the first logic unit and the second logic unit, and relaying a first signal output by the output end of the first logic unit to the first input end of the second logic unit through the flow register.
Preferably, the calculating the remaining path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit specifically includes:
remaining path [ (distance between preset position and first input of second logic unit)2- (distance of Preset location to optimal Path)2]1/2。
Preferably, the determining the placement position of the first-stage register according to the preset position with the shortest remaining path specifically includes:
and taking the preset position with the shortest residual path as the position of the signal input end of the first pole register, and placing the first pole register.
Preferably, the determining the placement position of the current level register according to the preset position with the shortest remaining path specifically includes:
and taking the preset position with the shortest residual path as the position of the signal input end of the current one-pole register, and placing the current one-pole register.
Preferably, the reserved empty space comprises a punch-through structure.
Preferably, the method further comprises: determining whether the signal transmission delay on a connecting line between the signal output end of the last stage register and the first input end of the second logic unit is less than or equal to one clock cycle;
if not, outputting prompt information of inserting the error of the pipeline register
The signal relay method of the physical layer logic module based on the pipeline register, provided by the embodiment of the invention, can automatically identify and judge the optimal insertion position of the pipeline register between the two physical layer logic modules, and realize the signal relay between the two physical layer logic modules through the automatic insertion on the optimal insertion position.
Drawings
FIG. 1 is a flow chart of a signal relaying method for a physical layer logic module based on a pipeline register;
fig. 2 is a schematic diagram illustrating a process of determining the placement position of the primary register.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
The embodiment of the invention provides a signal relay method of a physical layer logic module based on a pipeline register, the main steps of the method flow are shown in figure 1, and the method comprises the following steps:
step 110, determining a first logic unit and a second logic unit with signal transmission in the same clock domain;
the first logic unit and the second logic unit are two logic units to be synchronized by a clock; there is a requirement for sequential logic between them.
Step 120, determining the insertion stage number of the flow register required by the signal synchronization of the first logic unit and the second logic unit;
specifically, according to the requirement of sequential logic, the signal output from the first logic unit is tapped and then transferred to the signal input of the second logic unit. And beating the signals, and realizing through a register. One way to beat the signal is to delay the signal transmission by one clock cycle by passing the signal through a register once. If multi-beat is needed, it is realized by using multi-stage connected registers, i.e. pipeline registers.
Each stage of the pipeline register includes one or a group of registers connected in series between stages, each stage of the pipeline register having defined module boundaries. That is, the minimum occupied chip area required to insert the primary register is determined.
Step 130, determining the maximum offset of each stage of register according to the maximum transmission displacement of the signal in one clock cycle;
in particular, the maximum displacement that a signal can travel, i.e. the furthest distance a signal can travel, per clock cycle can be determined. Thereby, the maximum offset of the register of each stage from the output position of the signal of the previous stage can be calculated. This maximum offset is the maximum transmission displacement of the signal in one clock cycle. If the maximum offset is exceeded, the signal cannot be transferred to this register within one clock cycle.
Step 140, determining a barrier blocking module according to a module boundary within a range taking the signal output end of the first logic unit as a central point and the maximum offset as a radius; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a surplus path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placement position of the first-stage register according to the preset position with the shortest surplus path;
specifically, the type of the barrier module includes macro cells or reserved slots; the reserved slots include a feed through structure (feed through), and of course, other design rules such as the boundaries of the physical layer logic block dictate that slots not used to place insert registers.
And a straight-line path from the output end of the first logic unit to the first input end of the second logic unit is defined as an optimal path. In a preferred embodiment, the remaining path [ (distance between the preset position and the first input of the second logic unit)2- (distance of Preset location to optimal Path)2]1/2。
And placing the first pole register by taking the preset position with the shortest residual path as the position of the signal input end of the first pole register.
Fig. 2 is a schematic diagram illustrating a process of determining the placement position of the primary register. As shown, taking the empty space available for placing the register of the stage as A, B, C, the three preset positions are x1, x2 and x3 respectively, and the distances from the preset positions to the optimal path (shown by the dashed line connecting the output end of the first logic unit to the input end of the second logic unit in fig. 2) are y1, y2 and y3 respectively. The maximum offset is shown by the circles in fig. 2, where the shaded portions are all blocking obstacle modules. The remaining paths for placing the registers at these three places are calculated using the above formulas, respectively. And selecting the vacancy B with the shortest residual path as the determined placing position.
In the actual execution process, when a plurality of preset positions exist, traversing and calculating the residual paths corresponding to the preset positions, and selecting the shortest path as the placing position.
Step 150, determining a barrier blocking module according to the module boundary within the range that the signal output end of the former-stage register is a central point and the maximum offset is a radius; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a residual path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placing position of the current stage of register according to the shortest preset position of the residual path until the placing position of each stage of flow register corresponding to the insertion stage is determined;
in this step, the calculation method of the remnant path is the same as that in step 140, and the placement of the current one-pole register is performed by using the preset position where the remnant path is shortest as the position of the signal input end of the current one-pole register.
And 160, inserting and serially wiring registers at all levels according to the determined placing positions to form a flow register between the first logic unit and the second logic unit, and relaying a first signal output by the output end of the first logic unit to the first input end of the second logic unit through the flow register.
In a preferred embodiment, after the above procedure is performed, a verification is performed again. Verifying by determining whether signal transmission delay on a connecting line between a signal output end of the last stage register and a first input end of the second logic unit is less than or equal to one clock cycle, and when the signal transmission delay is less than or equal to one clock cycle, indicating that the insertion of the flow register is correct, and completely relaying signals from the first logic unit to the second logic unit by the inserted flow register under the condition of meeting the sequential logic; if not, outputting a prompt message of inserting the error of the pipeline register.
The signal relay method of the physical layer logic module based on the pipeline register, provided by the embodiment of the invention, can automatically identify and judge the optimal insertion position of the pipeline register between the two physical layer logic modules, and realize the signal relay between the two physical layer logic modules through the automatic insertion on the optimal insertion position.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (6)

1. A signal relay method of a physical layer logic module based on a pipeline register is characterized by comprising the following steps:
determining a first logic unit and a second logic unit with signal transmission under the same clock domain; the first logic unit and the second logic unit are two logic units to be synchronized by a clock; a straight line path from the output end of the first logic unit to the first input end of the second logic unit is an optimal path;
determining the insertion stage number of the flow register required by signal synchronization of the first logic unit and the second logic unit; each stage of the pipeline register comprises one or a group of registers, all stages are connected in series, and each stage of the pipeline register is provided with a determined module boundary;
determining the maximum offset of each stage of register according to the maximum transmission displacement of the signal in one clock cycle;
determining a barrier blocking module according to a module boundary in a range with a signal output end of the first logic unit as a central point and the maximum offset as a radius; the type of the barrier module comprises macro cells or reserved vacancies; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a surplus path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placement position of the first-stage register according to the preset position with the shortest surplus path;
determining a barrier blocking module according to the module boundary within the range that the signal output end of the previous-stage register is a central point and the maximum offset is a radius; in a plurality of preset positions which are not blocked by the blocking barrier module, calculating a residual path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input end of the second logic unit, and determining the placing position of the current stage register according to the preset position with the shortest residual path until the placing position of each stage of the flow register corresponding to the insertion stage is determined;
and inserting and serially wiring registers at all levels according to the determined placing positions to form a flow register between the first logic unit and the second logic unit, and relaying a first signal output by the output end of the first logic unit to the first input end of the second logic unit through the flow register.
2. The signal relaying method of claim 1, wherein the calculating the remaining path according to the distance from the preset position to the optimal path and the distance from the preset position to the first input terminal of the second logic unit is specifically:
remaining path [ (distance between preset position and first input of second logic unit)2- (distance of Preset location to optimal Path)2]1/2。
3. The signal relaying method of claim 1, wherein the determining the placement position of the first-stage register according to the preset position with the shortest remaining path specifically comprises:
and taking the preset position with the shortest residual path as the position of the signal input end of the first pole register, and placing the first pole register.
4. The signal relaying method of claim 1, wherein the determining of the placement position of the current stage register according to the preset position with the shortest remaining path specifically comprises:
and taking the preset position with the shortest residual path as the position of the signal input end of the current one-pole register, and placing the current one-pole register.
5. The signal relaying method of claim 1, wherein the reserved null comprises a punchthrough structure.
6. The signal relaying method of claim 1, further comprising: determining whether the signal transmission delay on a connecting line between the signal output end of the last stage register and the first input end of the second logic unit is less than or equal to one clock cycle;
if not, outputting a prompt message of inserting the error of the pipeline register.
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