CN115129642B - Chip bus delay adjustment method, electronic equipment and medium - Google Patents

Chip bus delay adjustment method, electronic equipment and medium Download PDF

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CN115129642B
CN115129642B CN202210674668.9A CN202210674668A CN115129642B CN 115129642 B CN115129642 B CN 115129642B CN 202210674668 A CN202210674668 A CN 202210674668A CN 115129642 B CN115129642 B CN 115129642B
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Muxi Integrated Circuit Nanjing Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application relates to a chip bus delay adjustment method, electronic equipment and a medium, wherein the method comprises the following steps: step S1, obtaining an ith group initiation terminal Se i And a receiving end Re i Bus information { Bundle "between which delay adjustment is required 1 i ，Bundle 2 i ，…Bundle Ni i -a }; step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises a bus type identifier, a delay stage number and a clock domain identifier; step S3, based on Bundle n i Corresponding bus type identification determines corresponding delay series, clock domain identification, delay module type and delay unit type, and generates corresponding type delay module WR n The method comprises the steps of carrying out a first treatment on the surface of the Step S4, WR is processed n Inserting a Bundle n i Establishing WR n With Se i And Re (Re) i Interconnection between based on WR n With Se i And Re (Re) i Interconnection between the two, corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; s5, analyzing the delay configuration file information and automatically generating a Bundle n i Corresponding WR n Is a RTL code of (c). The application improves the chip delay adjustment efficiency and the chip design efficiency.

Description

Chip bus delay adjustment method, electronic equipment and medium
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a method for adjusting chip bus delay, an electronic device, and a medium.
Background
In the chip design process, a logic interconnection relationship between modules needs to be established first, and then physical connection is established based on the logic interconnection relationship. Because of different layout and wiring modes, the distances and types of different connecting lines between different modules may be different, especially when the distances are too long, the connection between the modules is directly established in a logic interconnection mode, which affects the time sequence (timing) performance between two interconnected modules, so that some delay modules are usually required to be inserted between the two interconnected modules to optimize the time sequence between the two interconnected modules. However, in the prior art, the insertion of the delay module is realized based on RTL-level processing, so that the processing process is complex, the efficiency is low, the error is easy, and the flexibility is poor. In addition, as the chip scale increases, this approach is clearly not used for large-scale chip design, and once the delay modules need to be changed, the delay modules also need to be changed one by one in the RTLs of the corresponding parts, resulting in low chip design efficiency.
Disclosure of Invention
The application aims to provide a chip bus delay adjustment method, electronic equipment and a medium, which improve chip delay adjustment efficiency and chip design efficiency.
According to a first aspect of the present application, there is provided a method for adjusting a chip bus delay, the chip including a plurality of groups of initiator terminals and receiver terminals, each group of initiator terminals and receiver terminals being interconnected by at least one bus; the method comprises the following steps:
step S1, obtaining an ith group initiation terminal Se i And a receiving end Re i Bus information { Bundle "between which delay adjustment is required 1 i ，Bundle 2 i ，…Bundle Ni i }，Bundle n i Is Se i And Re (Re) i The nth bus needing delay adjustment has the value range of n from 1 to Ni, and Ni is Se i And Re (Re) i The number of buses needing delay adjustment, wherein the value range of i is 1 to M, and M is the total number of groups of an initiating end and a receiving end;
step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises bus type identification, delay progression and clock domain identification, each bus type identification corresponds to one delay module type and one delay unit type, and Pi is Se i And Re (Re) i The number of bus types among the bus types Pi is less than or equal to Ni;
step S3, based on Bundle n i Corresponding bus type identification determines corresponding delay series, clock domain identification, delay module type and delay unit type, and generates corresponding type delay module WR n The delay level is according to Bundle n i Determining a corresponding target physical distance;
step S4, WR is processed n Inserting a Bundle n i Establishing WR n With Se i And Re (Re) i Interconnection between based on WR n With Se i And Re (Re) i Interconnection between the two, corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; the delay level is WR n The number of corresponding delay units; the clock domain identification is used for determining WR n A connected clock signal; each type of delay unit is configured with a corresponding RTL code;
s5, analyzing the delay configuration file information and automatically generating a Bundle n i Corresponding WR n Is a RTL code of (c).
According to a second aspect of the present application, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the application.
According to a third aspect of the present application there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present application.
Compared with the prior art, the application has obvious advantages and beneficial effects. By means of the technical scheme, the chip bus delay adjustment method, the electronic equipment and the medium provided by the application can achieve quite technical progress and practicality, and have wide industrial utilization value, and have at least the following advantages:
the application does not need to realize the insertion of the delay module based on RTL level processing, directly inserts delay information at the initiating terminal, generates delay configuration file information, then analyzes the delay configuration file information to automatically generate RTL codes corresponding to the delay module, has good flexibility, high delay adjustment efficiency and difficult error, and can realize batch configuration and modification, thereby improving the delay adjustment efficiency of chips and further improving the design efficiency of the chips.
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application, as well as the preferred embodiments thereof, together with the following detailed description of the application, given by way of illustration only, together with the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a method for adjusting chip bus delay according to a first embodiment of the present application;
FIG. 2 is a schematic diagram of an insertion delay module according to a first embodiment of the present application;
FIG. 3 is a flow chart of a method for adjusting the time delay of a bidirectional interconnection bus according to a second embodiment of the present application;
fig. 4 is a schematic diagram of an inserting bidirectional delay module according to a second embodiment of the present application;
FIG. 5 is a flowchart of a method for adjusting the latency of a bidirectional interconnect bus according to a third embodiment of the present application;
fig. 6 is a schematic diagram of a first delay module and a second delay module inserted in a third embodiment of the present application.
Detailed Description
In order to further describe the technical means and effects adopted by the application to achieve the preset aim, the following detailed description refers to a specific implementation manner of a chip bus delay adjustment method, electronic equipment and media and effects thereof according to the application by combining the accompanying drawings and preferred embodiments.
Embodiment 1,
The first embodiment provides a method for adjusting a chip bus delay (Repeater), as shown in fig. 1, the chip includes a plurality of groups of initiating terminals and receiving terminals, and each group of initiating terminals and receiving terminals are interconnected through at least one bus; the method comprises the following steps:
step S1, obtaining an ith group initiation terminal Se i And a receiving end Re i Bus information { Bundle "between which delay adjustment is required 1 i ，Bundle 2 i ，…Bundle Ni i }，Bundle n i Is Se i And Re (Re) i The nth bus needing delay adjustment has the value range of n from 1 to Ni, and Ni is Se i And Re (Re) i The number of buses needing delay adjustment is between, the value range of i is 1 to M, and M is the total number of groups of an initiating end and a receiving end.
Wherein the initiating terminal Se i And a receiving end Re i The bus information can be directly obtained based on the original first logic interconnection information, and the current buses need to be subjected to delay adjustment according to the physical distance between the minimum component modules at the two ends corresponding to the buses in the physical layout.
It should be noted that the first logic interconnection information refers to logic interconnection information formed by a module corresponding to the initiator, a module corresponding to the receiver, and at least one bus corresponding between the initiator module and the receiver module. Other constituent modules can be nested in each module, wherein the modules are interconnected by buses, only the minimum constituent units are generated by writing RTL codes, and other layers of modules or modules and the minimum constituent units are interconnected by high-level buses, so that the RTL codes of chip designs can be automatically generated, and the RTL codes can be reconfigured and configured. It will be appreciated that the original logical interconnect information is the original interconnect relationship without delay adjustment.
Step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises bus type identification, delay progression and clock domain identification, each bus type identification corresponds to a delay Module (Repeater) type and a delay unit (Repeater Module) type, and Pi is Se i And Re (Re) i The number of bus types in between, pi is less than or equal to Ni.
The delay level in the delay information refers to the number of default delay units corresponding to the type of the delay module corresponding to the bus type identifier, and the clock domain identifier refers to the default clock domain identifier corresponding to the type of the delay module corresponding to the bus type identifier. Only the delay information is inserted into the initiating terminal, so that the delay has directivity and disorder is avoided. The delay information may further include user identification (Owner) information and Comment information (command), etc., where clock periods corresponding to clock signals in the same clock domain are the same. The user identity may specifically refer to a developer identity.
Step S3, based on Bundle n i Corresponding bus type identification determines corresponding delay series, clock domain identification, delay module type and delay unit type, and generates corresponding classDelay module WR n The delay level is according to Bundle n i And determining the corresponding physical distance of the target. Bundle n i The corresponding target physical distance refers to Bundle n i The minimum component units connected at the two ends are in corresponding physical distances in the physical layout and wiring of the chip.
Step S4, WR is processed n Inserting a Bundle n i Establishing WR n With Se i And Re (Re) i Interconnection between based on WR n With Se i And Re (Re) i Interconnection between the two, corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; the delay level is WR n The number of corresponding delay units; the clock domain identification is used for determining WR n A connected clock signal; each type of delay element is configured with a corresponding RTL code.
It will be appreciated that the delay profile information includes at least WR n Corresponding delay progression, clock domain identification, and may also include WR n Corresponding originating terminal identification and receiving terminal identification.
It can be understood that after adding a delay module to the first logic interconnection information and connecting the delay module with the initiating terminal and the receiving terminal, a new interconnection relationship, namely the second logic interconnection information, is generated. It should be noted that, the second logic interconnection relationship is a newly generated top interconnection relationship, which buses need to be inserted with delay modules, and specific details of the delay modules are generated based on the delay units therein, and after subsequent connection, if the current delay modules need to be adjusted, the delay units and the number of stages of the delay units in the second logic interconnection relationship are directly adjusted, so that the top interconnection relationship is not affected. In addition, the checking (review) and adjustment of the delay adjustment can be facilitated by generating the delay profile information, that is, the checking is performed based on the generated delay profile information, and the delay adjustment is directly implemented by adjusting the fields in the delay profile information, so that the RTL code does not need to be directly changed, and the method is also suitable for designing a large-scale chip, wherein the format of the delay profile information is XML, JSON, YMAL or CSV.
In step S5, WR is obtained by analyzing the delay profile information n Corresponding delay unit type and delay stage number, in WR n Corresponding delay series delay units are generated, and after all delay units are connected in series, one end of each delay unit is connected to WR n And one end is connected to WR n To establish WR n Interconnection of the delay cells. Based on WR n Interconnection of medium delay units and RTL codes corresponding to the delay units, and automatic generation of Bundle n i Corresponding WR n Is a RTL code of (c).
As an example, the delay unit may be embodied as Flip-Flop (Flip-Flop). A schematic diagram of a set of an originating terminal and a receiving terminal after insertion of a delay module is shown in fig. 2.
It should be noted that, based on the delay profile information, it may be determined that a bus to be added to the delay module is needed, and the delay module is added to a corresponding position. The detailed information of the delay module is generated based on the corresponding delay unit. The process can automatically generate RTL codes of the delay module and the delay unit, does not need to write a large amount of delay RTL codes manually, greatly saves delay adjustment time and workload, and adjusts the efficiency of chip delay.
The corresponding RTL code may specifically be Verilog code, system Verilog code, VHDL code, or the like.
As an embodiment, the bus to be delay-adjusted refers to a bus in which a target physical distance between two minimum constituent units to which both ends of the bus are connected is greater than a preset physical distance threshold. The target physical distance refers to the physical distance between two minimum constituent units in the corresponding chip physical layout wiring.
The preset distance threshold is determined according to a specific chip design parameter, but it can be understood that when the target physical distance corresponding to the bus is greater than the preset distance threshold, delay adjustment is needed, otherwise, the time sequence between the two interconnected modules is affected, and when the target physical distance corresponding to the bus is less than or equal to the preset distance threshold, delay adjustment is not needed, namely, insertion of the corresponding bus is not neededIs provided. It can be known that, in the buses in the same group of the initiator and the receiver, a part of buses may need to be inserted with a delay module, a part of buses may not need to be inserted with a delay module, and the delay modules inserted by each bus may not be the same. The bus may include a multi-bit (bits) signal or may be a single bit (bit) signal, such as a reset signal. As an embodiment, in the step S4, WR is based on n With Se i And Re (Re) i Interconnection between the two, corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information;
step S41 based on WR n With Se i And Re (Re) i The interconnection between the two determines whether a custom delay progression and a custom clock domain identification exist:
if the custom delay progression exists, the Bundle is used n i Setting the delay series in the corresponding delay configuration file information as a self-defined delay series, otherwise, setting the delay series in the delay information;
if the custom clock domain identifier exists, the Bundle is added n i The clock domain identification in the corresponding delay configuration file information is set as the self-defined clock domain identification, otherwise, the clock domain identification in the delay information is set.
The flexible configuration of delay progression information and clock domain identification information is realized based on the step S41, and for a large number of instances of the delay module needing default delay progression information, the delay progression information can be directly generated in batch to realize inheritance, and in addition, when the design part implementation details need to be changed, the delay module type can be directly changed.
As an embodiment, the delay level in the delay information is a default delay level value or a default preset delay level range. In the step S41, a Bundle is used n i The delay progression in the corresponding delay profile information is set as the delay progression in the delay information:
step S411, if the delay level in the delay information is the default delay level value, the Bundle is used n i Corresponding toSetting the delay progression in the delay configuration file information as a corresponding default delay progression value; this situation can be used in the chip design phase. If the delay information is within the preset delay progression range, randomly selecting a value from the preset delay progression range as a Bundle n i The delay progression in the corresponding delay profile information. This case may be applicable to the chip verification phase. Different delay progression information setting modes ensure the flexibility of design and can be applied to different stages of chip design.
In order to avoid adding a delay module and facilitate subsequent delay adjustment, in the process of generating the delay configuration file information, the method further comprises the following steps:
step S10, for any bus Bundle which does not need to be subjected to delay adjustment at present k K is the number of buses which do not need to be subjected to delay adjustment at present, and the value of K is in the range of 1 to K k And (4) regarding the bus to be subjected to delay adjustment, generating corresponding delay configuration file information according to the mode of the step S1-the step S4, and setting the corresponding delay progression to 0. Therefore, if the delay information is needed to be added to the bus without the delay information, the modification is directly carried out based on the delay configuration file information, and the top-layer interconnection information is not needed to be changed. In addition, can also be directed to Bundle k Generating prompt information, and identifying the currently configured buses without delay adjustment so as to prompt engineers to check and confirm. In addition, in the case of the optical fiber,
after the logic interconnection is established and delay information is added, physical interconnection can be performed, and in the physical interconnection process, the minimum constituent units are recombined according to the physical layout and wiring of the chip, but it is understood that the logic interconnection connection relationship between the minimum constituent units is unchanged. As an embodiment, the step S5 further includes: step S6, establishing physical interconnection based on the second logic interconnection information, specifically including:
step S61, obtaining split information { W } corresponding to the delay module 1 n ,W 2 n },W 1 n To follow the initiator in the process of establishing physical interconnectionNumber of time delay units of module recombination, W 2 n To establish the number of delay units, W, of module reorganization along with the receiving end in the physical interconnection process 1 n +W 2 n ＝W n ，W n The total number of delay units in the delay module is the total number of delay units;
step S62, W in the delay module 1 n The delay units and the initiating terminal are used as an integral module, W in the delay module 2 n The delay units and the receiving end are physically interconnected with other modules as a whole module.
Note that { W 1 n ,W 2 n The specific value of the is based on physical layout wiring, and in the physical implementation, recombination (regrouping) is involved, so as to improve the clock between the initiating terminal and the receiving terminal, keep balance, and specifically determine the number of delay units following the physical layout of the initiating terminal or the receiving terminal according to the load between the initiating terminal and the receiving terminal and the Zhong Songjin degree in time. For example, a delay module including 10-stage delay units is inserted between the module a and the module B, and when physical interconnection is performed, 3 delay units and the module a are physically interconnected with other modules as a whole, and 7 delay units and the module B are physically interconnected with other modules as a whole. It will be appreciated that the total number of delay cells between module a and module B is unchanged, i.e., 10 delay cells remain passing between module a and module B after the physical placement and routing is completed.
After the physical layout and wiring are completed, whether the delay modules inserted between each group of the initiating terminal and the receiving terminal meet the requirements or not can be detected, wherein part of the delay modules do not meet the requirements, further adjustment can be continued, as an embodiment, after the step S6, if a delay adjustment instruction is received, execution is performed:
s7, analyzing an initiating terminal identifier, a receiving terminal identifier, a bus type identifier field and delay adjustment information from the delay adjustment instruction, wherein the delay adjustment information comprises target delay stage number information and/or target splitting information { W } 1 n’ ,W 2 n’ }。
If the delay adjustment information includes the target delay progression information, returning to step S5, updating the delay progression information corresponding to the delay profile information, and then continuing to execute the subsequent steps, thereby obtaining that delay adjustment can be achieved by directly changing the delay profile information.
If the delay adjustment information includes target split information { W } 1 n’ ,W 2 n’ When step S51 is performed, W is set 1 n ＝W 1 n’ ,W 2 n ＝W 2 n’ And then continues to perform the subsequent steps.
The embodiment does not need to realize the insertion of the delay module based on RTL-level processing, directly inserts delay information at the initiating terminal, generates delay configuration file information, then analyzes the delay configuration file information to automatically generate RTL codes corresponding to the delay module, has good flexibility, high delay adjustment efficiency and difficult error, and can realize batch configuration and modification, thereby improving the chip delay adjustment efficiency and further improving the chip design efficiency. It should be noted that, the related technical details in other embodiments are also applicable to the related steps in the present embodiment, and the detailed description is not repeated here.
It should be noted that, in the first embodiment, the signal transmission directions of all connection lines in the unidirectional transmission buses between the transmitting end and the receiving end are identical, but in some application scenarios, there may be bidirectional interconnection buses, that is, a group of buses, there are two connection lines in two directions, and based on such scenarios, two embodiments of the second embodiment and the third embodiment are further proposed.
Embodiment II,
A second embodiment provides a bidirectional interconnect bus delay adjustment method, as illustrated in fig. 3, including:
step C1, obtaining a bidirectional interconnection bus Bundle between a first module and a second module in chip design i ＝{L 1 i ，L 2 i ，…L iX i ，S 1 i ，S 2 i ，…S iY i I is a value from 1 to N, N is the total number of buses between the first module and the second module, L x i The x is a connecting line taking the first module as an initiating terminal and the second module as a receiving terminal, and the value range of x is 1 to iX, S y i A connection line taking the second module as an initiating terminal and the first module as a receiving terminal is the y-th connection line, and the value range of y is 1 to iY;
it should be noted that, if unidirectional transmission buses exist in the first module and the second module, the method described in the first embodiment may be directly adopted to perform delay adjustment, which is not described herein.
Step C2, inserting a bidirectional delay module between the first module and the second module, wherein in the first direction, S is 1 i ，S 2 i ，…S iY i Setting a delay mark, wherein the first direction is the direction from the first module to the second module; in the second direction, L 1 i ，L 2 i ，…L iX i Setting a non-delay mark, wherein the second direction is the direction from the second module to the first module; when the first module transmits a first signal to the second module, the first signal is along L 1 i ，L 2 i ，…L iX i Communicating with the second module through the bi-directional delay module; when the second module transmits a second signal to the first module, the second signal is along S 1 i ，S 2 i ，…S iY i And communicating with the first module through the bidirectional delay module.
Note that, bundle i If the corresponding target physical distance is larger than the preset distance threshold value, delay adjustment can be omitted.
According to the embodiment, the bidirectional delay module is inserted into the bidirectional interconnection bus between the first module and the second module, so that delay adjustment of the bidirectional interconnection bus is realized, and disorder is avoided.
As an embodiment, the step C2 includes:
step C21, based on Bundle i Determining a corresponding clock domain identifier, and determining delay progression information based on a target physical distance;
as one embodiment, the delay progression information is based on Bundle for the user i The target physical distance of the minimum component unit connected at two ends in the chip physical layout wiring determines a specified value. This situation can be used in the chip design phase. As another embodiment, the delay progression information may also determine a random value in the delay progression information range for the user based on the target physical distance, which may be applicable to the chip verification stage.
Step C22, according to { L ] 1 i ，L 2 i ，…L iX i ，S 1 i ，S 2 i ，…S iY i Generating corresponding delay information contact by corresponding clock domain identification and delay stage number information i1 And contact i2 Wherein, the method comprises the steps of, wherein,
contract i1 comprising a Bundle i Identification, delay progression information, clock domain identification, and L 1 i ，L 2 i ，…L iX i Corresponding delay identification and S 1 i ，S 2 i ，…S iY i A corresponding non-delay identifier;
contract i2 comprising a Bundle i Identification, delay progression information, clock domain identification, and L 1 i ，L 2 i ，…L iX i Corresponding non-delay identification and S 1 i ，S 2 i ，…S iY i Corresponding delay marks;
through the arrangement of the step C22, when the first module transmits signals to the second module, S 1 i ，S 2 i ，…S iY i Delay adjustment is not performed, and only relevant L is adjusted 1 i ，L 2 i ，…L iX i . Similarly, when the second module transmits signals to the first module, L 1 i ，L 2 i ，…L iX i Delay adjustment is not performed, and only relevant S is adjusted 1 i ，S 2 i ，…S iY i 。
Step C23, connecting i1 Inserting the first module to connect i2 Inserting the second module;
step C24, according to the composition i1 And contact i2 In Bundle i A bi-directional delay module is generated.
A schematic diagram of a framework formed by a set of first and second modules inserted into a bidirectional delay module is shown in fig. 4.
As an embodiment, the step C24 further includes:
step C241 based on the composition i1 And contact i2 Generating delay configuration file information;
it should be noted that, the delay profile information format is XML, JSON, YMAL or CSV, etc., and the detailed generation process and technical details about the delay profile information returning to adjust the delay after physical interconnection may be referred to the first embodiment, which is not described herein again.
And step C242, automatically generating RTL codes corresponding to the bidirectional delay modules based on the delay configuration file information.
As one embodiment, step C241 includes:
step C2411 based on contact i1 And contact i2 Generating a bidirectional delay module WR i 。
Step C2422, WR i Inserting a Bundle i Establishing WR i And interconnection between the first module and the second module.
Step C2423 based on WR i Interconnection with the first and second modules i1 And contact i2 Corresponding delay progression and clock domain identification generation Bundle i Corresponding delay configuration fileInformation; the delay level is determined according to physical layout, and the delay level is WR i The number of corresponding delay units; the clock domain identification is used for determining WR i A connected clock signal; each type of delay element is configured with a corresponding RTL code.
The RTL code corresponding to the bidirectional delay module includes the bidirectional delay module and the RTL code of the bidirectional delay unit in the bidirectional delay module, and the detailed generation technical details may be referred to the first embodiment and will not be described herein. The RTL code can be a Verilog code, a System Verilog code, a VHDL code, or the like.
As an example, in step C242, if WR i The bidirectional delay module generates a bidirectional delay unit of the appointed delay progression information if the appointed delay progression information is included in the system, and if the WR i The two-way delay module generates corresponding contact if no delay stage number information is specified i1 And contact i2 A two-way delay unit with medium delay stage number.
The flexible configuration of the delay progression information is realized based on the step C242, and for a large number of delay module instances requiring default delay progression information, the designated delay progression information can be directly generated in batch, and in addition, when the implementation details of the design part need to be changed, the delay module types can be directly changed.
According to the embodiment, the bidirectional delay module is inserted into the bidirectional interconnection bus between the first module and the second module, so that delay adjustment of the bidirectional interconnection bus is realized, disorder is avoided, the flexibility and the efficiency of delay adjustment of the bidirectional interconnection bus are improved, and the chip design efficiency is improved. It should be noted that, the related technical details in the foregoing embodiment and other embodiments are applicable to the related steps in the present embodiment, and are not repeated here.
The bidirectional delay module inserted in the second embodiment can only divide W for the first module when physically interconnecting 1 i Two-way delay units dividing W for the second module 2 n A bidirectional delay unit, but divided based on the first direction and the second directionThe results of the bidirectional delay units are not necessarily the same, but are different in most cases, but only a group of bidirectional delay units are provided, so that the first module and the second module can be considered as far as possible to divide the bidirectional delay units, the flexibility is poor, and based on the results, the application further provides a third embodiment.
Third embodiment,
An embodiment III provides a bidirectional interconnection bus delay adjustment method, as shown in fig. 5, including:
step E1, obtaining a bidirectional interconnection bus Bundle between a first module and a second module in chip design i ＝{L 1 i ，L 2 i ，…L iX i ，S 1 i ，S 2 i ，…S iY i I is a value from 1 to N, N is the total number of buses between the first module and the second module, L x i The x is a connecting line taking the first module as an initiating terminal and the second module as a receiving terminal, and the value range of x is 1 to iX, S y i A connection line taking the second module as an initiating terminal and the first module as a receiving terminal is the y-th connection line, and the value range of y is 1 to iY;
it should be noted that, if unidirectional transmission buses exist in the first module and the second module, the method described in the first embodiment may be directly adopted to perform delay adjustment, which is not described herein.
E2, inserting a first delay module and a second delay module between the first module and the second module, and when the first module transmits a first signal to the second module, the first signal is along L 1 i ，L 2 i ，…L iX i Communicating with the second module through the first delay module; when the second module transmits a second signal to the first module, the second signal is along S 1 i ，S 2 i ，…S iY i And communicating with the first module through the second delay module.
Note that, bundle i The corresponding physical distance of the target is larger than the preset distanceIf the threshold value is smaller than the preset distance threshold value, the delay adjustment is not performed.
As an embodiment, the step E2 includes:
step E21, based on Bundle i Determining a corresponding clock domain identifier, and determining delay progression information based on a target physical distance; wherein the target physical distance refers to Bundle i The physical distance between the minimum component units connected at two ends in the physical layout and wiring of the chip.
As one embodiment, the delay progression information specifies a value for the delay progression information determined by the user based on the target physical distance. This situation can be used in the chip design phase. As another embodiment, the delay progression information is a random value in a delay progression information range determined by the user based on the target physical distance, which may be applicable to the chip verification stage.
Step E22, according to { L ] 1 i ，L 2 i ，…L iX i Generating corresponding delay information contact by corresponding clock domain identification and delay stage number information i1 ’ ，contract i1 ’ Comprising a Bundle i Sign, L 1 i ，L 2 i ，…L iX i Identification, delay progression information and clock domain identification;
according to { S ] 1 i ，S 2 i ，…S iY i Generating corresponding delay information contact by corresponding clock domain identification and delay stage number information i2 ’ ，contract i2 ’ Comprising a Bundle i Sign, S 1 i ，S 2 i ，…S iY i Identification, delay progression information and clock domain identification;
through step E22, delay information can be generated based on two signal transmission directions of the first module and the second module, so as to generate an independent delay module.
Step E23, combining i1 ’ Inserting the first module to connect i2 ’ Inserting the second module;
step E24, according to the composition i1 ’ In Bundle i A first delay module is generated according to the contact i2 ’ In Bundle i A second delay module is generated.
A schematic diagram of an architecture formed by a set of first and second modules inserted after the first and second delay modules is shown in fig. 6.
As an embodiment, the step E24 further includes:
step E241, connect ij ’ Generating corresponding delay configuration file information, and storing the corresponding delay configuration file information into a corresponding delay configuration file, wherein the delay configuration file information comprises an initiating terminal identifier, a receiving terminal identifier, a bus identifier, a connecting identifier of the initiating terminal and the receiving terminal, delay series information and a clock domain identifier, and j takes a value of 1 or 2;
when j takes 1, the initiating terminal identification field in the corresponding delay configuration file information stores a first module identification, the receiving terminal identification field stores a second module identification, and the initiating terminal and receiving terminal connection identification field stores L 1 i ，L 2 i ，…L iX i Identification;
when j is 2, the initiating terminal identification field in the corresponding delay configuration file information stores a second module identification, the receiving terminal identification field stores a first module identification, and the connecting line identification field of the initiating terminal and the receiving terminal stores S 1 i ，S 2 i ，…S iY i And (5) identification.
It should be noted that, the delay profile can be generated based on the delay profile information, the inspection can be performed based on the generation of the delay profile, and the delay adjustment can be directly implemented by adjusting the fields in the delay profile, so that the RTL code does not need to be directly changed, and the method is also suitable for large-scale chip design. Other technical details regarding the delay profile L may refer to the first embodiment, and similar technical details are not described herein.
As described in the first embodiment, after the logic interconnection is established and the delay information is added, physical interconnection can be performed, and in the physical interconnection process, some modules are rearranged according to the physical layout and wiring, but it is understood that the connection relationship between the minimum constituent units is unchanged. In this embodiment, since two independent delay modules are established between the first module and the second module, when physical interconnection is implemented, the method further includes, as an embodiment, after the step E24:
step E3, establishing physical interconnection based on logical interconnection between the first module and the second module, specifically including:
step E31, obtaining split information { W } corresponding to the first delay module 11 i ,W 12 i Splitting information { W } corresponding to the second delay module 21 i ,W 22 i W, where 11 i To establish the number of first delay units, W, of module reorganization along with the first module in the physical interconnection process 12 i To establish the number of first delay units, W, of module reorganization along with the second module in the physical interconnection process 21 i To establish the number of second delay units, W, of module reorganization along with the first module in the physical interconnection process 12 i To establish the number of second delay units, W, of module reorganization along with the second module in the physical interconnection process 11 i +W 12 i ＝W 21 i +W 22 i ＝W i ，W i The total number of the first delay units in the first module is also the total number of the second delay units in the second module;
step E32, to be compared with W in the first delay module 11 i W in the first delay unit and the second delay module 21 i The second delay units and the first module are used as an integral module, W in the first delay module 12 i W in the first delay unit and the second delay module 22 i The second delay units and the second modules are used as an integral module and are physically interconnected with other modules.
Note that { W 11 i ,W 12 i }、{W 21 i ,W 22 i The specific value of the is based on the physical layout wiring of the chip, and in the physical implementation, the recombination is involved, so that the clock between the initiating terminal and the receiving terminal is improved, the balance is kept, and the number of delay units which follow the physical layout of the initiating terminal or the receiving terminal is determined according to the load between the initiating terminal and the receiving terminal and the Zhong Songjin degree in time. For example, a first delay module and a second delay module including 10-stage delay units are inserted between the module a and the module B, and when physical interconnection is performed, 3 first delay units, 6 second delay units and the module a are used as a whole to perform physical interconnection with other modules, and 7 first delay units, 4 second delay units and the module B are used as a whole to perform physical interconnection with other modules. It will be appreciated that the total number of first delay cells and second delay cells between module a and module B is unchanged, i.e., after the physical layout is completed, 10 first delay cells and 10 second delay cells are still passed between module a and module B. According to the embodiment, by arranging the independent first delay module and the independent second delay module, the physical interconnection is established, so that the time delays in different signal transmission directions between the first module and the second module can be independently considered, and the time delay adjustment is more flexible.
After the physical layout and wiring are completed, whether the delay modules inserted between each group of the initiating terminal and the receiving terminal meet the requirements or not can be detected, if part of the delay modules do not meet the requirements, further adjustment can be continuously performed on the first delay module and the second delay module, as an embodiment, after the step E3, if a delay adjustment instruction is received, execution is performed:
step E4, analyzing an initiating terminal identifier, a receiving terminal identifier, a bus type identifier field and delay adjustment information from the delay adjustment instruction, wherein the delay adjustment information comprises target delay stage number information and/or target splitting information { W (W) of the first delay module 11 i’ ,W 12 i’ Target split information { W } and/or second delay module 21 i’ ,W 22 i’ }。
If the delay adjustment information includes the target delay progression information, the execution step S241 is returned to, the delay progression information in the corresponding delay profile information is updated, and then the subsequent steps are continued to be executed.
If { W } is included in the delay adjustment information 11 i’ ,W 12 i’ Setting W before executing step E31 11 i ＝W 11 i’ ,W 12 i ＝W 12 i’ And/or if { W } is included in the delay adjustment information 21 i’ ,W 22 i’ Setting W before executing step E31 21 i ＝W 21 i’ ，W 22 i ＝W 22 i’ And then continues to perform the subsequent steps.
The embodiment realizes the delay adjustment of the bidirectional interconnection bus by arranging the independent first delay module and the independent second delay module between the first module and the second module, avoids disorder, and can split the delay modules according to the specific condition on each transmission direction when physical interconnection is carried out, thereby improving the flexibility of the physical interconnection. It should be noted that, the related technical details in the foregoing embodiment may also be applied to the related steps in the present embodiment, and the detailed description is not repeated here.
In the foregoing embodiment, corresponding gating signals may be set for the delay module of the first embodiment, the bidirectional delay module of the second embodiment, and the first delay module and the second delay module of the third embodiment, where each gating signal may be independent of each other. The gating signal needs to meet the corresponding timing requirement, for example, if the W clock gating signals need to be set to high level before the effective data, and if Q clock cycles are needed to be kept after the effective data is transmitted, W and Q are configured according to the specific timing requirement. The gating clock can integrally control the opening and closing of the first delay module of the first embodiment, the second bidirectional delay module of the second embodiment or the first delay module and the second delay module of the third embodiment, and the power consumption can be reduced by setting the gating clock.
It will be appreciated by those skilled in the art that the same technical details in the different embodiments described above may be used with each other, and that the technical features of the embodiments described above may be further combined, and all fall within the scope of the present application, which is not explicitly mentioned here.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the application also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method of any one of the embodiments of the present application.
The embodiment of the application also provides a computer readable storage medium, and the computer instructions are used for executing the method according to any embodiment of the application.
The present application is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the application.

Claims (10)

1. A method for adjusting the delay of a chip bus is characterized in that,
the chip comprises a plurality of groups of initiating terminals and receiving terminals, and each group of initiating terminals and receiving terminals are interconnected through at least one bus; the method comprises the following steps:
step S1, obtaining an ith group initiation terminal Se i And a receiving end Re i Bus information { Bundle "between which delay adjustment is required 1 i ，Bundle 2 i ，…Bundle Ni i }，Bundle n i Is Se i And Re (Re) i The nth bus needing delay adjustment has the value range of n from 1 to Ni, and Ni is Se i And Re (Re) i The number of buses needing delay adjustment, wherein the value range of i is 1 to M, and M is the total number of groups of an initiating end and a receiving end;
step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises bus type identification, delay progression and clock domain identification, each bus type identification corresponds to one delay module type and one delay unit type, and Pi is Se i And Re (Re) i The number of bus types among the bus types Pi is less than or equal to Ni;
step S3, based on Bundle n i Corresponding bus type identification determines corresponding delay series, clock domain identification, delay module type and delay unit type, and generates corresponding type delay module WR n The delay level is according to Bundle n i Determining a corresponding target physical distance;
step S4, WR is processed n Inserting a Bundle n i Establishing WR n With Se i And Re (Re) i Interconnections between based onWR n With Se i And Re (Re) i Interconnection between the two, corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; the delay level is WR n The number of corresponding delay units; the clock domain identification is used for determining WR n A connected clock signal; each type of delay unit is configured with a corresponding RTL code;
s5, analyzing the delay configuration file information and automatically generating a Bundle n i Corresponding WR n Is a RTL code of (c).
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the step S4, WR is based on n With Se i And Re (Re) i Interconnection between the two, corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay profile information, comprising:
step S41 based on WR n With Se i And Re (Re) i The interconnection between the two determines whether a custom delay progression and a custom clock domain identification exist:
if the custom delay progression exists, the Bundle is used n i Setting the delay series in the corresponding delay configuration file information as a self-defined delay series, otherwise, setting the delay series in the delay information;
if the custom clock domain identifier exists, the Bundle is added n i The clock domain identification in the corresponding delay configuration file information is set as the self-defined clock domain identification, otherwise, the clock domain identification in the delay information is set.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the delay progression in the delay information is a default delay progression value or a default preset delay progression range.
4. The method of claim 3, wherein the step of,
in the step S41, a Bundle is used n i The delay progression in the corresponding delay profile information is set as the delay progression in the delay information, including:
step S411, if the delay level in the delay information is the default delay level value, the Bundle is used n i The delay progression in the corresponding delay configuration file information is set as a corresponding default delay progression value;
if the delay level in the delay information is a preset delay level range, randomly selecting a value from the preset delay level range as a Bundle n i The delay progression in the corresponding delay profile information.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the delay profile information format is XML, JSON, YMAL or CSV.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the process of generating the delay profile information, the method further comprises the following steps:
step S10, for any bus Bundle which does not need to be subjected to delay adjustment at present k K is the number of buses which do not need to be subjected to delay adjustment at present, and the value of K is in the range of 1 to K k And (4) regarding the bus to be subjected to delay adjustment, generating corresponding delay configuration file information according to the mode of the step S1-the step S4, and setting the corresponding delay progression to 0.
7. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the delay information also includes user identification information and annotation information.
8. The method of claim 1, wherein the step of determining the position of the substrate comprises,
each delay element is implemented as Flip-Flop.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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