CN115129642A - Chip bus delay adjusting method, electronic device and medium - Google Patents
Chip bus delay adjusting method, electronic device and medium Download PDFInfo
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Abstract
The invention relates to a chip bus delay adjusting method, electronic equipment and a medium, wherein the method comprises the following steps: step S1, obtaining the i-th group of initiating terminals Se i And a receiving terminal Re i Bus information required to be adjusted in delay { Bundle } 1 i ，Bundle 2 i ，…Bundle Ni i }; step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises a bus type identifier, a delay progression and a clock domain identifier; step S3 based on Bundle n i The corresponding bus type identification determines the corresponding delay progression, clock domain identification, delay module type and delay unit type, and generates the corresponding type of delay module WR n (ii) a Step S4, WR n Insert Bundle n i Establishing WR n And Se i And Re i Interconnection between based on WR n And Se i And Re i Interconnection between them, and corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; step S5, analyzing the delay configuration file information and automatically generating Bundle n i Corresponding WR n The RTL code of (1). The invention improves the chip delay adjustment efficiency and the chip design efficiency.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a chip bus delay adjusting method, electronic equipment and a medium.
Background
In the chip design process, a logical interconnection relationship between modules needs to be established first, and then physical connection is established based on the logical interconnection relationship. Because the distances and types between different connecting lines between different modules may be different due to different layout and wiring manners, especially when the distance is too long, the connection between the modules is directly established in a logic interconnection manner, which may affect the timing performance (timing) between two interconnected modules, and therefore, some delay modules are usually required to be inserted between two interconnected modules to optimize the timing between the two interconnected modules. However, in the prior art, the insertion of the delay module is realized based on the processing at the RTL level, which results in a complex processing process, low efficiency, high error probability and poor flexibility. In addition, as the chip scale becomes larger, this method is obviously not used for large-scale chip design, and once the delay module needs to be changed, the RTLs of the corresponding parts also need to be changed one by one, resulting in low chip design efficiency.
Disclosure of Invention
The invention aims to provide a chip bus delay adjusting method, electronic equipment and a medium, and the chip bus delay adjusting efficiency and the chip design efficiency are improved.
According to a first aspect of the present invention, a method for adjusting a chip bus delay is provided, where the chip includes multiple sets of an initiator and a receiver, and each set of the initiator and the receiver is interconnected through at least one bus; the method comprises the following steps:
step S1, obtaining the i-th group of initiating terminals Se i And a receiving end Re i Bus information required to be adjusted by delay { Bundle } 1 i ，Bundle 2 i ，…Bundle Ni i }，Bundle n i Is Se i And Re i The nth bus needing delay adjustment, wherein the value range of n is from 1 to Ni, and Ni is Se i And Re i The number of buses needing delay adjustment, the value range of i is 1 to M, and M is the total number of the initiating terminal and the receiving terminal;
step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises bus type identifiers, delay progression and clock domain identifiers, each bus type identifier corresponds to one delay module type and one delay unit type, and Pi is Se i And Re i The number of bus types between, Pi is less than or equal to Ni;
step S3 based on Bundle n i The corresponding bus type identification determines the corresponding delay stage number, clock domain identification, delay module type and delay unit type, and generates the corresponding type of delay module WR n The delay progression is based on Bundle n i Determining a corresponding target physical distance;
step S4, WR n Insert Bundle n i Establishing WR n And Se i And Re i Interconnection between, based on WR n And Se i And Re i Interconnection between them, and corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; the delay progression is WR n The number of corresponding delay cells in; the clock domain identification is used to determine WR n A connected clock signal; each type of delay unit is configured with a corresponding RTL code;
step S5, analyzing the delay configuration file information and automatically generating Bundle n i Corresponding WR n The RTL code of (1).
According to a second aspect of the present invention, there is provided an electronic apparatus comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor and arranged to perform the method of the first aspect of the invention.
According to a third aspect of the invention, there is provided a computer readable storage medium, the computer instructions being for performing the method of the first aspect of the invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip bus delay adjusting method, the electronic equipment and the medium provided by the invention can achieve considerable technical progress and practicability, have industrial wide utilization value and at least have the following advantages:
the invention does not need to realize the insertion of the delay module based on the RTL level processing, directly inserts the delay information at the initiating end, generates the delay configuration file information, and then analyzes the delay configuration file information to automatically generate the RTL code corresponding to the delay module, has good flexibility, high efficiency of adjusting the delay, and is not easy to make mistakes, in addition, batch configuration and modification can be realized, the delay adjusting efficiency of the chip is improved, and the design efficiency of the chip is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a chip bus delay adjustment method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an insertion delay module according to an embodiment of the present invention;
fig. 3 is a flowchart of a bidirectional interconnection bus delay adjustment method according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of an inserted bidirectional delay module according to a second embodiment of the present invention;
fig. 5 is a flowchart of a bidirectional interconnection bus delay adjustment method according to a third embodiment of the present invention;
fig. 6 is a schematic diagram of inserting a first delay module and a second delay module according to a third embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to specific embodiments and effects of a method, an electronic device and a medium for adjusting a delay of a chip bus according to the present invention with reference to the accompanying drawings and preferred embodiments.
The first embodiment,
An embodiment provides a method for adjusting a chip bus delay (Repeater), as shown in fig. 1, where the chip includes multiple sets of an initiator and a receiver, and each set of the initiator and the receiver is interconnected through at least one bus; the method comprises the following steps:
step S1, obtaining the i-th group of initiating terminals Se i And a receiving end Re i Bus information required to be adjusted in delay { Bundle } 1 i ，Bundle 2 i ，…Bundle Ni i }，Bundle n i Is Se i And Re i The nth bus needing delay adjustment, wherein the value range of n is 1 to Ni, and Ni is Se i And Re i The number of buses needing delay adjustment is increased, the value range of i is 1 to M, and M is the total group number of the initiating terminal and the receiving terminal.
Wherein, the initiation end Se i And a receiving end Re i The bus information can be directly obtained based on the original first logic interconnection information, and the current buses need to be subjected to delay adjustment according to the physical distance of the minimum composition modules at the two ends corresponding to the buses in the physical layout.
It should be noted that the first logical interconnection information refers to logical interconnection information composed of a module corresponding to the initiator, a module corresponding to the receiver, and at least one bus corresponding to the initiator module and the receiver module. Other modules can be nested in each module, wherein the modules are also interconnected by buses, only the minimum component unit is generated by writing RTL codes, and the modules at other layers or the modules and the minimum component unit are interconnected by high-level buses, so that the RTL codes of chip design can be generated automatically, and the modules are reconfigurable and configurable. It is understood that the original logical interconnection information is the original interconnection relationship without delay adjustment.
Step S2, at Se i Inserting Pi group delay information, wherein the delay information comprises bus type identification, delay progression and clock domain identification, and each bus type identification corresponds to a delayModule (Repeater) type and a delay unit (Repeater Module) type, Pi being Se i And Re i Pi is less than or equal to Ni.
The delay progression in the delay information refers to the number of default delay units corresponding to the delay module type corresponding to the bus type identifier, and the clock domain identifier refers to the default clock domain identifier corresponding to the delay module type corresponding to the bus type identifier. And only the delay information is inserted at the initiating end, so that the delay has directivity, and the disorder is avoided. The delay information may further include user identification (Owner) information and Comment information (Comment), and the clock periods corresponding to the clock signals in the same clock domain are the same. The user identification may specifically refer to a developer identification.
Step S3 based on Bundle n i The corresponding bus type identification determines the corresponding delay stage number, clock domain identification, delay module type and delay unit type, and generates the corresponding type of delay module WR n The delay progression is according to Bundle n i And determining the corresponding target physical distance. Bundle n i The corresponding target physical distance is referred to as Bundle n i And the minimum composition units connected at the two ends have corresponding physical distances in the physical layout wiring of the chip.
Step S4, WR n Insert Bundle n i Establishing WR n And Se i And Re i Interconnection between, based on WR n And Se i And Re i Interconnection between them, and corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; the delay progression is WR n The number of corresponding delay cells in; the clock domain identification is used to determine WR n A connected clock signal; each type of delay unit is configured with a corresponding RTL code.
It will be appreciated that the latency profile information includes at least WR n Corresponding delay progression, clock domain identification, and may also include WR n And the corresponding initiating terminal identification and the receiving terminal identification.
It can be understood that, after the delay module is added to the first logic interconnection information and the initiator and the receiver, a new interconnection relationship, that is, the second logic interconnection information, is generated. It should be noted that the second logical interconnection relationship is a newly generated top-level interconnection relationship, and determines which buses need to be inserted into the delay module, and the specific details of the delay module are generated based on the delay units therein, and after subsequent connection, if the current delay module needs to be adjusted, the delay units therein and the stage number of the delay units are directly adjusted, so that the top-level interconnection relationship is not affected. In addition, the checking (review) and the adjustment of the delay adjustment can be facilitated by generating the delay configuration file information, namely, the checking is carried out based on the generated delay configuration file information, the delay adjustment is realized directly by adjusting the field in the delay configuration file information, the RTL code does not need to be directly changed, and the method is also suitable for large-scale chip design, wherein the format of the delay configuration file information is XML, JSON, YMAL or CSV.
In step S5, the WR is acquired by analyzing the delay profile information n Corresponding delay cell type and delay stage number, at WR n In the method, a plurality of delay units corresponding to the delay stages are generated, and after all the delay units are connected in series, one end of each delay unit is connected to the WR n One end of the input terminal is connected to the WR n Thereby establishing a WR n Interconnection of the middle delay units. Based on WR n Interconnection of middle delay units and RTL codes corresponding to the delay units automatically generate Bundle n i Corresponding WR n The RTL code of (1).
As an example, the delay unit may be embodied as a Flip-Flop (Flip-Flop). A schematic diagram of a set of an initiating terminal and a receiving terminal after inserting the delay module is shown in fig. 2.
It should be noted that, based on the delay profile information, it may be determined that there is a bus that needs to be added to the delay module, and the delay module is added to a corresponding position. The detail information of the delay module is generated based on the corresponding delay unit. The process can automatically generate the RTL codes of the delay module and the delay unit, does not need to compile a large number of delay RTL codes manually, greatly saves delay adjustment time and workload, and has chip delay adjustment efficiency.
The corresponding RTL code may be Verilog code, System Verilog code, VHDL code, or the like.
As an embodiment, the bus requiring delay adjustment refers to a bus in which a target physical distance between two minimum constituent units connected to two ends of the bus is greater than a preset physical distance threshold. The target physical distance refers to a physical distance between two minimum constituent units in a corresponding chip physical place and route.
The preset distance threshold is determined according to specific chip design parameters, but it can be understood that when the target physical distance corresponding to the bus is greater than the preset distance threshold, it indicates that delay adjustment is required, otherwise, the time sequence between the two interconnection modules is affected, and when the target physical distance corresponding to the bus is less than or equal to the preset distance threshold, delay adjustment is not required, that is, a corresponding delay module is not required to be inserted. Therefore, in the buses in the same set of the initiating terminal and the receiving terminal, a part of the buses may need to be inserted with the delay module, a part of the buses do not need to be inserted with the delay module, and the delay modules inserted by each bus may be different. The bus may include multiple bit (bits) signals or may be a single bit (bit) signal, such as a reset signal. As an example, in step S4, the WR is based on n And Se i And Re i Interconnection between them, and corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information;
step S41 based on WR n And Se i And Re i The interconnection between the two determines whether the user-defined delay progression and the user-defined clock domain identification exist:
if the self-defined delay progression exists, the Bundle is used n i Setting the delay progression in the corresponding delay configuration file information as a user-defined delay progression, or else, setting the delay progression in the delay information;
if the user-defined clock domain identification exists, the Bundle is used n i Corresponding delay configuration file letterAnd setting the clock domain identifier in the message as a user-defined clock domain identifier, otherwise, setting the clock domain identifier in the delay information.
Based on the step S41, flexible configuration of delay progression information and clock domain identification information is realized, and for a large batch of instances of the default delay module that include the specified delay progression information, batch generation can be directly performed to realize inheritance, and in addition, when the implementation details of the design part need to be changed, implementation can be directly realized by changing the type of the delay module.
As an embodiment, the delay progression in the delay information is a default delay progression value or a default preset delay progression range. In step S41, Bundle is inserted n i The delay progression in the corresponding delay configuration file information is set as the delay progression in the delay information:
step S411, if the delay progression in the delay information is the default delay progression value, the Bundle is added n i The delay progression in the corresponding delay configuration file information is set as a corresponding default delay progression numerical value; this case can be used in the chip design phase. If the delay information is in a preset delay progression range, randomly selecting a value from the preset delay progression range as a Bundle n i And the corresponding delay progression in the delay configuration file information. This case may be applicable to the chip verification stage. Different delay stage information setting modes ensure the flexibility of design and can be applied to different stages of chip design.
In order to avoid missing the addition of the delay module and facilitate subsequent delay adjustment, in the process of generating the delay configuration file information, the method further comprises the following steps:
step S10, for any bus Bundle which does not need to be adjusted in time delay currently k The value range of K is 1 to K, K is the current bus number without delay adjustment, and the Bundle is divided into k And (4) regarding the bus to be subjected to delay adjustment, generating corresponding delay configuration file information according to the modes from the step S1 to the step S4, and setting the corresponding delay progression to be 0. Thus, if it is subsequently necessary to add delay to the bus to which no delay information is currently addedDuring time information, the information is directly modified based on the delay configuration file information, and top-layer interconnection information does not need to be changed. In addition, the method can also be used for Bundle k And generating prompt information, and identifying the currently configured bus which is not subjected to delay adjustment so as to prompt an engineer to check and confirm. In addition to this, the present invention is,
the logical interconnection is well established, physical interconnection can be performed after the delay information is added, and in the physical interconnection process, the minimum composition units are recombined according to the physical layout and wiring of the chip, but it can be understood that the logical interconnection connection relationship between the minimum composition units is unchanged. As an embodiment, the step S5 is followed by: step S6, establishing physical interconnection based on the second logical interconnection information, specifically including:
step S61, obtaining splitting information { W) corresponding to the delay module 1 n ,W 2 n },W 1 n Number of delay units, W, for module reassembly following an initiator during physical interconnection establishment 2 n Number of delay units, W, for performing module reassembly following a receiving end in establishing physical interconnection 1 n +W 2 n ＝W n ，W n The total number of delay units in the delay module;
step S62, delaying W in the module 1 n The delay unit and the initiating terminal are taken as an integral module, and W in the delay module 2 n The delay units and the receiving end are physically interconnected with other modules as a whole module.
Note that, { W 1 n ,W 2 n The specific values of the units are set based on physical layout and wiring, recombination (regrouping) is involved in physical implementation, and in order to improve the clock between the initiating terminal and the receiving terminal and keep balance, the number of delay units which follow the initiating terminal or the receiving terminal to perform physical layout is determined according to the load between the initiating terminal and the receiving terminal and the tightness degree of the clock. For example, a delay module including 10 stages of delay units is inserted between the module a and the module B, and when physical interconnection is performed, 3 delay units are connected with the module BThe module A is physically interconnected with other modules as a whole, and the 7 delay units are physically interconnected with the module B as a whole. However, it is understood that the total number of delay units between the modules a and B is not changed, i.e. after the physical layout and routing are completed, 10 delay units still pass between the modules a and B.
After the physical layout is completed, it may be detected whether the delay modules inserted between the initiating terminal and the receiving terminal of each group meet the requirements, and if some of the delay modules do not meet the requirements, further adjustment may be continued, as an embodiment, after step S6, if a delay adjustment instruction is received, the following steps are performed:
step S7, analyzing the originating terminal identification, the receiving terminal identification, the bus type identification field and the delay adjustment information from the delay adjustment instruction, wherein the delay adjustment information comprises the target delay progression information and/or the target splitting information { W } 1 n’ ,W 2 n’ }。
If the delay adjustment information includes the target delay progression information, the process returns to step S5, updates the corresponding delay progression information in the delay profile information, and then continues to execute the subsequent steps, so that the delay adjustment can be realized by directly changing the delay profile information.
If the delay adjustment information comprises target splitting information { W 1 n’ ,W 2 n’ When step S51 is executed, set W 1 n ＝W 1 n’ ,W 2 n ＝W 2 n’ And then continuing to execute the subsequent steps.
The embodiment does not need to realize the insertion of the delay module based on the RTL level processing, directly inserts the delay information at the initiating end, generates the delay configuration file information, and then analyzes the delay configuration file information to automatically generate the RTL code corresponding to the delay module, has good flexibility, high efficiency of adjusting delay, and is not easy to make mistakes, in addition, batch configuration and modification can be realized, the delay adjustment efficiency of the chip is improved, and the design efficiency of the chip is improved. It should be noted that the relevant technical details in the following other embodiments may also be applied to the relevant steps in this embodiment, and are not repeated herein.
It should be noted that, the first embodiment is applicable to a unidirectional transmission bus between a sending end and a receiving end, that is, signal transmission directions of all connecting lines in the bus are the same, however, in some application scenarios, a bidirectional interconnection bus may exist, that is, a set of buses exist, connecting lines in two directions, and based on such scenarios, two embodiments, that is, the second embodiment and the third embodiment, are further provided.
Example II,
An embodiment two provides a bidirectional interconnection bus delay adjustment method, as shown in fig. 3, which includes:
step C1, acquiring a bidirectional interconnection bus Bundle between a first module and a second module in chip design i ＝{L 1 i ，L 2 i ，…L iX i ，S 1 i ，S 2 i ，…S iY i I is one of 1 to N, N is the total number of buses between the first module and the second module, L x i The value range of x is 1 to iX, S y i The value of y is 1 to iY, wherein the value of y is the connection line of the yth connection line which takes the second module as the initiating end and the first module as the receiving end;
it should be noted that if a unidirectional transmission bus exists in the first module and the second module, the method described in the first embodiment may be directly adopted to perform the delay adjustment, and details are not described herein.
Step C2, inserting a bidirectional delay module between the first module and the second module, S in the first direction 1 i ，S 2 i ，…S iY i Setting a delay identifier, wherein the first direction is a direction from the first module to the second module; in the second direction, is L 1 i ，L 2 i ，…L iX i Setting a non-delayed flag, the secondThe second direction is a direction from the second module to the first module; when the first module transmits a first signal to the second module, the first signal follows L 1 i ，L 2 i ，…L iX i Communicating with the second module through the bi-directional delay module; when the second module transmits a second signal to the first module, the second signal follows S 1 i ，S 2 i ，…S iY i Communicating with the first module through the bi-directional delay module.
Note that Bundle i The corresponding target physical distance is greater than a preset distance threshold, and if the corresponding target physical distance is less than the preset distance threshold, the delay adjustment is not required.
In the embodiment, the bidirectional delay module is inserted into the bidirectional interconnection bus between the first module and the second module, so that the delay adjustment of the bidirectional interconnection bus is realized, and the disorder is avoided.
As an embodiment, the step C2 includes:
step C21, based on Bundle i Determining a corresponding clock domain identifier, and determining delay progression information based on the target physical distance;
as an embodiment, the delay progression information is based on Bundle for the user i The target physical distance of the minimum composition unit connected at the two ends in the chip physical layout wiring determines a specified value. This case can be used in the chip design phase. As another embodiment, the delay progression information may also be a random value in a range of delay progression information determined by a user based on a target physical distance, and this case may be applied to the chip verification stage.
Step C22, according to { L 1 i ，L 2 i ，…L iX i ，S 1 i ，S 2 i ，…S iY i Generating corresponding delay information contact by the corresponding clock domain identification and the corresponding delay stage number information i1 And extract i2 Wherein, in the step (A),
contract i1 includes Bundle i Identification, delay progression information, clock domain identification, and L 1 i ，L 2 i ，…L iX i Corresponding delay mark and S 1 i ，S 2 i ，…S iY i A corresponding non-delayed identity;
contract i2 comprises Bundle i Identification, delay progression information, clock domain identification, and L 1 i ，L 2 i ，…L iX i Corresponding non-delayed identity and S 1 i ，S 2 i ，…S iY i Corresponding delay marks;
through the setting of step C22, S is enabled to be transmitted to the second module when the first module transmits signals to the second module 1 i ，S 2 i ，…S iY i No delay adjustment is made, only the relevant L is adjusted 1 i ，L 2 i ，…L iX i . Similarly, L is the time when the second module transmits a signal to the first module 1 i ，L 2 i ，…L iX i The delay adjustment is not carried out, only the relevant S is adjusted 1 i ，S 2 i ，…S iY i 。
Step C23, extract i1 Inserting the first module to extract i2 Inserting the second module;
step C24, according to the contact i1 And extract i2 In Bundle i Generating a bidirectional delay module.
Fig. 4 is a schematic diagram of an architecture formed by a group of first modules and second modules after the bidirectional delay module is inserted.
As an embodiment, the step C24 further includes:
step C241, extract based on i1 And extract i2 Generating delay configuration file information;
it should be noted that the format of the delay configuration file information is XML, JSON, YMAL, or CSV, and the detailed generation process and the technical details about returning the delay configuration file information after physical interconnection to adjust the delay may refer to the first embodiment, and are not described herein again.
And step C242, automatically generating an RTL code corresponding to the bidirectional delay module based on the delay configuration file information.
As an example, step C241 includes:
step C2411, extract based on i1 And extract i2 Generating a bidirectional delay module WR i 。
Step C2422, WR i Insert Bundle i Establishing WR i And the interconnection between the first module and the second module.
Step C2423 based on WR i Interconnection between first and second modules, and contact i1 And extract i2 Generating Bundle by corresponding delay progression and clock domain identification i Corresponding delay configuration file information; the delay progression is determined according to the physical layout, and the delay progression is WR i The number of corresponding delay cells in; the clock domain identification is used to determine WR i A connected clock signal; each type of delay unit is configured with a corresponding RTL code.
The RTL code corresponding to the bidirectional delay module includes the bidirectional delay module and the RTL code of the bidirectional delay unit in the bidirectional delay module, and the detailed generation technical details may refer to the first embodiment, which is not described herein again. The RTL code may specifically be Verilog code, System Verilog code, VHDL code, or the like.
As an example, in step C242, if WR i If the specified delay progression information is included, the bidirectional delay module generates a bidirectional delay unit of the specified delay progression information, and if WR (write rate) is i If the delay series information is not specified, the bidirectional delay module generates a corresponding contact i1 And extract i2 And the bidirectional delay unit has a medium delay stage.
Based on the step C242, flexible configuration of delay stage information is realized, and for a large batch of instances of the default delay module that includes the specified delay stage information, batch generation may be performed directly, and in addition, when implementation details of the design portion need to be changed, implementation may be performed directly by changing the type of the delay module.
In the embodiment, the bidirectional delay module is inserted into the bidirectional interconnection bus between the first module and the second module, so that the delay adjustment of the bidirectional interconnection bus is realized, the disorder is avoided, the flexibility and the efficiency of the delay adjustment of the bidirectional interconnection bus are improved, and the chip design efficiency is improved. It should be noted that, the relevant technical details in the preamble embodiment and the following other embodiments may also be applicable to the relevant steps in this embodiment, and are not repeated herein.
In the second embodiment, the inserted bidirectional delay module can only divide W for the first module during physical interconnection 1 i A bidirectional delay unit for dividing W for the second module 2 n However, the results of the bidirectional delay units divided based on the first direction and the second direction are not necessarily the same, and are different in most cases, but only one group of bidirectional delay units is provided, so that the first module and the second module can be considered as far as possible to divide the bidirectional delay units, and the flexibility is poor.
Example III,
An embodiment three provides a method for adjusting a delay of a bidirectional interconnection bus, as shown in fig. 5, including:
step E1, acquiring a bidirectional interconnection bus Bundle between a first module and a second module in chip design i ＝{L 1 i ，L 2 i ，…L iX i ，S 1 i ，S 2 i ，…S iY i I is one of 1 to N, N is the total number of buses between the first module and the second module, L x i The xth connecting line which takes the first module as an initiating end and the second module as a receiving end has a value range of 1 to iX, S y i The value of y is 1 to iY, wherein the value of y is the connection line of the yth connection line which takes the second module as the initiating end and the first module as the receiving end;
it should be noted that if a unidirectional transmission bus exists in the first module and the second module, the method described in the first embodiment may be directly adopted to perform the delay adjustment, and details are not described herein.
Step E2, inserting a first delay module and a second delay module between the first module and the second module, when the first module transmits a first signal to the second module, the first signal is along L 1 i ，L 2 i ，…L iX i Communicating with the second module across the first delay module; when the second module transmits a second signal to the first module, the second signal follows S 1 i ，S 2 i ，…S iY i Communicating with the first module through the second delay module.
Note that Bundle i The corresponding target physical distance is greater than a preset distance threshold, and if the corresponding target physical distance is less than the preset distance threshold, the delay adjustment is not required.
As an embodiment, the step E2 includes:
step E21, based on Bundle i Determining a corresponding clock domain identifier, and determining delay progression information based on the target physical distance; wherein, the target physical distance refers to Bundle i The physical distance of the minimum composition unit connected at two ends in the physical layout wiring of the chip.
As an embodiment, the delay progression information specifies a value for the user to determine the delay progression information based on the target physical distance. This case can be used in the chip design phase. As another embodiment, the delay progression information is a random value in a delay progression information range determined by a user based on a target physical distance, and this case may be applied to the chip verification stage.
Step E22, according to { L 1 i ，L 2 i ，…L iX i Generating corresponding delay information contact by the corresponding clock domain identification and the corresponding delay stage number information i1 ’ ，contract i1 ’ Comprises Bundle i Logo, L 1 i ，L 2 i ，…L iX i Identification, delay progression information and clock domain identification;
according to { S 1 i ，S 2 i ，…S iY i Generating corresponding delay information contact by the corresponding clock domain identification and the corresponding delay stage number information i2 ’ ，contract i2 ’ Comprises Bundle i Logo, S 1 i ，S 2 i ，…S iY i Identification, delay progression information and clock domain identification;
through step E22, delay information may be generated based on two signal transmission directions of the first module and the second module, respectively, so as to generate independent delay modules.
Step E23, extract i1 ’ Inserting the first module to extract i2 ’ Inserting the second module;
step E24, according to the contact i1 ’ In Bundle i Generating a first delay module according to the contact i2 ’ In Bundle i Generating a second delay module.
Fig. 6 shows a schematic diagram of an architecture formed by a group of first and second modules inserted into the first and second delay modules.
As an embodiment, the step E24 further includes:
step E241, contact ij ’ Generating a piece of corresponding delay configuration file information, and storing the corresponding delay configuration file information to a corresponding delay configuration file, wherein the delay configuration file information comprises an initiating terminal identifier, a receiving terminal identifier, a bus identifier, an initiating terminal and receiving terminal connecting line identifier, delay progression information and a clock domain identifier, and j is 1 or 2;
when j is 1, the identification field of the initiating terminal in the corresponding delay configuration file information stores a first module identification, the identification field of the receiving terminal stores a second module identification, and the identification field of the connection between the initiating terminal and the receiving terminal stores L 1 i ，L 2 i ，…L iX i Identifying;
when j takes 2, the identification field of the initiating terminal in the corresponding delay configuration file information stores the second module identification, the identification field of the receiving terminal stores the first module identification, and the identification field of the connection between the initiating terminal and the receiving terminal stores S 1 i ，S 2 i ，…S iY i And (5) identifying.
It should be noted that the delay configuration file may be generated based on the delay configuration file information, the checking may be performed based on the generated delay configuration file, and the delay adjustment may be directly implemented by adjusting the field in the delay configuration file, without directly changing the RTL code, and is also applicable to large-scale chip design. For other technical details about the delay profile L document, reference may be made to embodiment one, and similar technical details are not described herein again.
As described in the first embodiment, logical interconnection is established, physical interconnection can be performed after delay information is added, and in the physical interconnection process, some modules are recombined according to physical layout and wiring, but it can be understood that the connection relationship between minimum constituent units is unchanged. In this embodiment, since two independent delay modules are established between the first module and the second module, when physical interconnection is implemented, the method is more flexible, and as an embodiment, after the step E24, the method further includes:
step E3, establishing physical interconnection based on logical interconnection between the first module and the second module, specifically including:
step E31, obtaining the splitting information { W } corresponding to the first delay module 11 i ,W 12 i And splitting information { W) corresponding to the second delay module 21 i ,W 22 i In which W 11 i Number of first delay cells, W, for re-assembly of modules following a first module in the process of establishing a physical interconnection 12 i Number of first delay units, W, for re-assembly of modules following a second module in the process of establishing a physical interconnection 21 i In the process of establishing physical interconnectionNumber of second delay units, W, for module reconfiguration following the first module 12 i Number of second delay units, W, for module reassembly following a second module in the process of establishing physical interconnection 11 i +W 12 i ＝W 21 i +W 22 i ＝W i ，W i The total number of the first delay units in the first module is also the total number of the second delay units in the second module;
step E32, W in the first delay module 11 i W in the first delay unit and the second delay module 21 i The second delay unit and the first module are used as an integral module to convert W in the first delay module 12 i W in the first delay unit and the second delay module 22 i The second delay unit and the second module are used as an integral module and are physically interconnected with other modules.
Note that, { W 11 i ,W 12 i }、{W 21 i ,W 22 i The specific value of the time delay unit is set based on the physical layout and wiring of the chip, and in order to improve the clock between the initiating terminal and the receiving terminal and keep balance during physical implementation, the number of the time delay units for physical layout following the initiating terminal or the receiving terminal is determined according to the load between the initiating terminal and the receiving terminal and the tightness degree of the clock. For example, a first delay module and a second delay module including 10 stages of delay units are inserted between a module a and a module B, and when physical interconnection is performed, 3 first delay units and 6 second delay units are physically interconnected with the module a as a whole and other modules, and 7 first delay units and 4 second delay units are physically interconnected with the module B as a whole and other modules. It is understood that the total number of the first delay unit and the second delay unit between the module a and the module B is not changed, that is, after the physical layout and wiring are completed, 10 first delay units and 10 second delay units still pass between the module a and the module B. According to the embodiment, the independent first extension is arrangedThe time delay module and the second time delay module enable the time delay in different signal transmission directions between the first module and the second module to be considered independently when physical interconnection is established, and time delay adjustment is more flexible.
After the physical layout wiring is completed, it may be detected whether the delay modules inserted between the initiating terminal and the receiving terminal of each group meet the requirements, and if some of the delay modules do not meet the requirements, the first delay module and the second delay module may be further adjusted, as an embodiment, after step E3, if a delay adjustment instruction is received, the following steps are performed:
step E4, analyzing the originating terminal identification, the receiving terminal identification, the bus type identification field and the delay adjustment information from the delay adjustment instruction, wherein the delay adjustment information includes the target delay progression information and/or the target splitting information { W of the first delay module 11 i’ ,W 12 i’ W and/or target splitting information of the second delay module 21 i’ ,W 22 i’ }。
If the delay adjustment information includes the target delay progression information, returning to the step S241, updating the delay progression information in the corresponding delay configuration file information, and then continuing to execute the subsequent steps.
If the delay adjustment information comprises { W 11 i’ ,W 12 i’ Before step E31 is executed, set W 11 i ＝W 11 i’ ,W 12 i ＝W 12 i’ And/or, if the delay adjustment information comprises { W } 21 i’ ,W 22 i’ Before performing step E31, set W 21 i ＝W 21 i’ ，W 22 i ＝W 22 i’ And then continuing to execute the subsequent steps.
The embodiment realizes the delay adjustment of the bidirectional interconnection bus by arranging the independent first delay module and the independent second delay module between the first module and the second module, avoids disorder, and can split the delay modules according to the specific conditions in each transmission direction when physical interconnection is carried out, thereby improving the flexibility of physical interconnection. It should be noted that, the relevant technical details in the preamble embodiment may also be applicable to the relevant steps in this embodiment, and are not repeated herein.
In the above embodiment, corresponding gate control signals may also be set for the delay module of the first embodiment, the bidirectional delay module of the second embodiment, and the first delay module and the second delay module of the third embodiment, and each gate control signal may be independent of each other. For example, if W clock gating signals need to be set to high level before valid data, and after the valid data is transmitted, Q clock cycles need to be maintained, and W and Q are configured according to specific timing requirements. The gated clock may integrally control the on and off of the first delay module, the second bidirectional delay module, or the first delay module and the second delay module of the first embodiment, and power consumption may be reduced by setting the gated clock.
It will be appreciated by a person skilled in the art that the same technical details in the different embodiments described above can be used with each other and that the technical features of the embodiments described above can be further combined and are within the scope of protection of the present application and will not be listed here.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor and configured to perform a method according to any one of the embodiments of the invention.
The embodiment of the invention also provides a computer-readable storage medium, and the computer instructions are used for executing the method of any embodiment of the invention.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for adjusting chip bus delay is characterized in that,
the chip comprises a plurality of groups of initiating terminals and receiving terminals, and each group of initiating terminals and receiving terminals are interconnected through at least one bus; the method comprises the following steps:
step S1, obtaining the i-th group of initiating terminals Se i And a receiving end Re i Bus information required to be adjusted in delay { Bundle } 1 i ，Bundle 2 i ，…Bundle Ni i }，Bundle n i Is Se i And Re i The nth bus needing delay adjustment, wherein the value range of n is 1 to Ni, and Ni is Se i And Re i With time delay adjustment betweenThe bus number, i ranges from 1 to M, and M is the total number of the initiating terminal and the receiving terminal;
step S2, at Se i Inserting Pi group of delay information, wherein the delay information comprises bus type identifiers, delay progression and clock domain identifiers, each bus type identifier corresponds to one delay module type and one delay unit type, and Pi is Se i And Re i Pi is less than or equal to Ni;
step S3 based on Bundle n i The corresponding bus type identification determines the corresponding delay stage number, clock domain identification, delay module type and delay unit type, and generates the corresponding type of delay module WR n The delay progression is according to Bundle n i Determining a corresponding target physical distance;
step S4, WR n Insert Bundle n i Establishing WR n And Se i And Re i Interconnection between, based on WR n And Se i And Re i Interconnection between them, and corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information; the delay progression is WR n The number of corresponding delay cells in; the clock domain identification is used to determine WR n A connected clock signal; each type of delay unit is configured with a corresponding RTL code;
step S5, analyzing the delay configuration file information and automatically generating Bundle n i Corresponding WR n The RTL code of (1).
2. The method of claim 1,
in step S4, WR-based processing n And Se i And Re i Interconnection between them, and corresponding delay progression and clock domain identification generation Bundle n i Corresponding delay configuration file information;
step S41 based on WR n And Se i And Re i The interconnection between the two determines whether a user-defined delay progression and a user-defined clock domain identifier exist:
if the self-defined delay progression exists, the Bundle is used n i Setting the delay progression in the corresponding delay configuration file information as a user-defined delay progression, or else, setting the delay progression in the delay information;
if the user-defined clock domain identification exists, the Bundle is used n i And setting the clock domain identifier in the corresponding delay configuration file information as a user-defined clock domain identifier, otherwise, setting the clock domain identifier in the delay information.
3. The method of claim 2,
the delay progression in the delay information is a default delay progression value or a default preset delay progression range.
4. The method of claim 3,
in step S41, Bundle is inserted n i The delay progression in the corresponding delay configuration file information is set as the delay progression in the delay information:
step S411, if the delay progression in the delay information is the default delay progression value, the Bundle is added n i The delay progression in the corresponding delay configuration file information is set as a corresponding default delay progression numerical value;
if the delay information is in a preset delay progression range, randomly selecting a value from the preset delay progression range as a Bundle n i And the corresponding delay progression in the delay configuration file information.
5. The method of claim 1,
the information format of the delay configuration file is XML, JSON, YMAL or CSV.
6. The method of claim 1,
in the process of generating the delay configuration file information, the method further comprises the following steps:
step S10, for any bus Bundle which does not need to be adjusted in time delay currently k The value range of K is 1 to K, K is the current bus number which does not need to be subjected to time delay adjustment, and Bundle is obtained k And (4) regarding the bus to be subjected to delay adjustment, generating corresponding delay configuration file information according to the modes from the step S1 to the step S4, and setting the corresponding delay progression to be 0.
7. The method of claim 1,
the delay information further includes user identification information and annotation information.
8. The method of claim 1,
each delay unit is implemented as a Flip-Flop.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer-readable storage medium having stored thereon computer-executable instructions for performing the method of any one of claims 1-8.
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