CN117764020B - Chip design adjustment method, electronic device and medium - Google Patents
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Abstract
The invention relates to the technical field of chips, in particular to a chip design adjustment method, electronic equipment and a medium, wherein the method comprises the following steps of S1, obtaining physical layer chip design configuration information; s2, generating physical layer chip design RTL codes based on the physical layer chip design configuration information and the RTL codes of each atomic unit, performing DFX test based on the design RTL codes, and generating a gate level netlist; s3, generating chip adjustment information based on the DFX test and/or the gate level netlist; s4, updating the physical layer chip design configuration information based on the chip adjustment information; and S5, generating an updated physical layer chip design RTL code based on the updated physical layer chip design configuration information and the RTL code of each atomic unit. The invention reduces the modification time of the chip design and improves the efficiency of the chip design.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip design adjustment method, an electronic device, and a medium.
Background
In the process of chip design, a logic layer chip design is required to be generated firstly to obtain an interconnection relation between a chip composition module of a logic layer and a chip composition module, then the chip composition module of the logic layer is recombined to generate a chip design of a physical layer based on physical layout, then the chip design of the physical layer is subjected to DFX test, the DFX test comprises a testability Design (DFT), a manufacturability Design (DFM), a reliability Design (DFR), a debugging design (DFD) and the like, and after the DFX test is passed, the chip design of the physical layer is comprehensively generated to form a gate-level netlist. During this process, problems may be found and adjustments to the chip design are required. However, the process from the logic layer to the physical layer of the chip design needs to undergo complex reorganization logic, and if the process returns to the logic layer for adjustment, huge amount of change is required, and a lot of time is required. If the chip design can be adjusted in the physical layer, the modification time of the chip design can be greatly reduced, and the efficiency of the chip design can be improved. Therefore, how to implement the adjustment of the chip design in the physical layer is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a chip design adjusting method, electronic equipment and medium, which reduce the modification time of the chip design and improve the efficiency of the chip design by adjusting the chip design in a physical layer.
According to a first aspect of the present invention, there is provided a chip design adjustment method, including:
Step S1, acquiring physical layer chip design configuration information {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},, wherein X n_Yn_PLn is the N-th group of physical layer chip interconnection design configuration information, the value range of N is 1 to N, N is the total group number of the physical layer chip design configuration information, X n、Yn is a chip composition module with interconnection relation in the physical layer chip design, the chip composition module is an atomic unit or a module formed by interconnection based on the atomic unit, each atomic unit is provided with a pre-generated RTL code, each chip composition module comprises a sub-module, port information interconnected with the sub-module and port information used for connecting the outside, and PL n is an interconnection port list of X n、Yn;
PLn={(PX1 n,PY1 n),(PX2 n,PY2 n),…,(PXi n,PYi n),…,(PXf(n) n,PYf(n) n)},(PXi n,PYi n) For the ith group of interconnection ports of X n、Yn, the value range of i is 1 to f (n), f (n) is the total number of interconnection ports between X n、Yn, PX i n=（PXTi n,PXWi n）,PXTi n is the ith port identification of X n, PXW i n is the signal direction information between PX i n、PYi n corresponding to X n, PY i n=（PYTi n,PYWi n）,PYTi n is the ith port identification of Y n, and PYW i n is the signal direction information between PX i n、PYi n corresponding to Y n;
BL is an unconnected port list, wherein the unconnected port list comprises unconnected port information in the physical layer chip design, and the unconnected port information comprises a port identifier and a port state;
S2, generating physical layer chip design RTL codes based on the physical layer chip design configuration information and the RTL codes of each atomic unit, performing DFX test based on the design RTL codes, and generating a gate level netlist;
step S3, generating chip adjustment information based on the DFX test and/or the gate level netlist, wherein the chip adjustment information comprises a newly added chip composition module, a deleted chip composition module, a replaced chip composition module and a modified port interconnection;
s4, updating the physical layer chip design configuration information based on the chip adjustment information;
And S5, generating an updated physical layer chip design RTL code based on the updated physical layer chip design configuration information and the RTL code of each atomic unit.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip design adjusting method, the electronic equipment and the medium provided by the invention can achieve quite technical progress and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:
the invention describes the physical layer chip design at a high level through the physical layer chip design configuration information, updates the physical layer chip design configuration information according to the chip adjustment information, realizes the adjustment of the chip design at the physical layer without returning to the logic layer to adjust the chip design, reduces the modification time of the chip design and improves the efficiency of the chip design.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a chip design adjustment method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a chip design adjustment method, as shown in fig. 1, comprising the following steps:
Step S1, acquiring physical layer chip design configuration information {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},, wherein X n_Yn_PLn is the interconnection design configuration information of the nth group of physical layer chips, N is 1 to N in the value range, N is the total number of the physical layer chip design configuration information, X n、Yn is a chip composition module with interconnection relation in the physical layer chip design, and the chip composition module is an atomic unit or a module formed by interconnection based on the atomic unit. The chip composition modules are arranged in a hierarchical mode, the top-layer chip composition module does not have a father module, the atomic unit does not have a child module, and any chip composition module except the top-layer module has only one father module. Each atomic unit is provided with a pre-generated RTL code, and each chip composition module comprises a sub-module, port information interconnected with the sub-module and port information used for connecting the outside, so that the composition structural relationship among the chip composition modules can be defined. PL n is the list of interconnect ports for X n、Yn.
PLn={(PX1 n,PY1 n),(PX2 n,PY2 n),…,(PXi n,PYi n),…,(PXf(n) n,PYf(n) n)},(PXi n,PYi n) The i-th group of interconnection ports of X n、Yn has a value range of 1 to f (n), and f (n) is the total number of interconnection ports between X n、Yn. PX i n=（PXTi n,PXWi n）,PXTi n is the i-th port identification of X n, and PXW i n is the signal direction information between PX i n、PYi n corresponding to X n. PY i n=（PYTi n,PYWi n）,PYTi n is the i-th port identification of Y n, and PYW i n is the signal direction information between PX i n、PYi n corresponding to Y n. The signals between PX i n,PYi n may be unidirectional signals or bi-directional signals.
BL is the list of the port that does not interconnect, the said list of port that does not interconnect includes port information that does not interconnect in the physical layer chip design, the port information that does not interconnect includes port identification and port state, the port state that does not interconnect may be unsettled, also may be to set up the fixed value 0 or set up the fixed value 1.
And S2, generating physical layer chip design RTL codes based on the physical layer chip design configuration information and the RTL codes of each atomic unit, performing DFX test based on the design RTL codes, and generating a gate level netlist.
It should be noted that, the physical layer chip design configuration information has explicitly set the interconnection relationship between the chip component modules, and each chip component module includes a sub-module, port information interconnected with the sub-module, and port information used for connecting with the outside, so that the composition structural relationship between the chip component modules can be made clear, and each atomic unit has previously set a corresponding RTL code, so that the physical layer chip design RTL code can be directly generated based on the physical layer chip design configuration information and the RTL code of each atomic unit. And then, performing DFX test based on the existing DFX test mode, and after the DFX test is passed, directly integrating RTL codes of the physical layer chip design based on the existing integration tool to generate a gate-level netlist, which is not repeated in the embodiment of the invention.
And S3, generating chip adjustment information based on the DFX test and/or the gate-level netlist, wherein the chip adjustment information comprises a newly added chip composition module, a deleted chip composition module, a replaced chip composition module and a modified port interconnection.
In the DFX test or ECO process for the gate netlist, corresponding chip adjustment information can be generated based on the found problem, and in general, only local adjustment of the chip design is required. In the prior art, the operation is directly based on RTL codes, so that the operation also needs to be returned to a logic layer, and a great deal of logic is influenced by local modification of the logic layer, so that the modification process is complex, and a great deal of time is consumed. The application is based on the high-level description of the configuration information, so that the chip design can be adjusted by modifying the configuration information of the physical layer chip design according to the information which needs to be adjusted.
And S4, updating the physical layer chip design configuration information based on the chip adjustment information.
And S5, generating an updated physical layer chip design RTL code based on the updated physical layer chip design configuration information and the RTL code of each atomic unit.
The following describes different modification scenarios in detail:
as an embodiment, if the chip adjustment information is a newly added chip composition module, the step S4 includes:
Step S41, obtaining a module identifier A of a chip to be newly added and an existing module identifier B of the chip to be newly added, wherein the existing module identifier B needs to establish a mapping relation with the module identifier A.
It should be noted that, if a chip component module needs to be locally added, connection needs to be generally established with other chip component modules, so that an existing chip component module identifier B that needs to establish a mapping relationship with a needs to be obtained at the same time.
And step S42, generating an interconnection port list of A and B based on the port interconnection relation of A and B.
It should be noted that, in the step S42, the interconnection port list of a and B may be generated according to the port interconnection relationship between a and B, specifically according to the structure of the interconnection port list described in the step S1, which is not described herein.
And S43, if the port which is not interconnected exists in the module formed by the chip A, adding the information of the port which is not interconnected and corresponds to the port A into the BL, and if the port which is B in the interconnected port list of the port A and the port B exists in the BL, deleting the port which is B in the interconnected port list of the port A and the port B from the BL.
It should be noted that, if there are some reserved ports of the a chip component module that are temporarily not interconnected, the information of the non-interconnected ports corresponding to a is added to the BL, and in the process of establishing interconnection with a, the non-interconnected ports of other chip component modules may be used, so that the ports of B in the interconnection port list of a and B need to be deleted from the BL.
As an embodiment, if the chip adjustment information is a delete chip composition module, the step S4 includes:
And C41, acquiring a module identifier E of the chip to be deleted.
And step C42, acquiring physical layer chip interconnection design configuration information containing E and non-interconnection port information corresponding to the E based on E query {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},.
And step C43, deleting the physical layer chip interconnection design configuration information containing E in {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, and deleting the non-interconnection port information corresponding to E in BL.
It should be noted that, if the module E is required to be partially deleted, the interconnection relationship corresponding to the module E and the related port information need to be deleted synchronously.
And C44, obtaining newly added non-interconnected port information after deleting the physical layer chip interconnection design configuration information containing E, and adding the newly added non-interconnected port information into the BL.
It should be noted that, after deleting the chip component module E and the corresponding interconnection information, new non-interconnection port information will appear, so the newly added non-interconnection port information needs to be added to the BL. After deleting the interconnection relation, the input port with the original interconnection relation can be specifically set to be 1 or 0 according to specific requirements, and the output port can be set to be in a suspended state.
As an embodiment, if the chip adjustment information is a replacement chip composition module, the step S4 includes:
And D41, acquiring a chip composition module identifier G to be replaced and a corresponding replaced chip composition module identifier H.
And step D42, acquiring physical layer chip interconnection design configuration information containing G and non-interconnection port information corresponding to G based on G query {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},.
And D43, deleting the physical layer chip interconnection design configuration information containing G in {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, and deleting the non-interconnection port information corresponding to G in BL.
It should be noted that, in the process of replacing the chip component module, the chip component module G to be replaced needs to be deleted first, and then the new replaced chip component module identifier H needs to be newly added, so that the configuration information corresponding to the chip component module G to be replaced needs to be deleted first, and the configuration information corresponding to the replaced chip component module identifier H needs to be newly added.
And D44, acquiring physical layer chip interconnection design configuration information containing H, and deleting the non-interconnection port information HR required to be deleted from the current BL and the non-interconnection port information HK required to be newly added in the BL after constructing the interconnection relation by the H.
And D45, adding the physical layer chip interconnection design configuration information containing H into {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, deleting HR in BL, and adding HK in BL.
It will be appreciated that in replacing the chip assembly module G with the chip assembly module H, the original non-interconnect port may be used, and a new non-interconnect port may also be present, so that the information in the BL needs to be updated synchronously.
As an embodiment, if the chip adjustment information is modification of port interconnection, the step S4 includes:
and E41, acquiring an interconnection port list corresponding to the port interconnection information to be modified.
It should be noted that, the chip adjustment information is to modify port interconnection, only the port interconnection information needs to be modified, and the chip composition module remains unchanged.
Step E42, updating a corresponding interconnection port list based on the port interconnection information to be modified, and acquiring the non-interconnection port information ER to be deleted from the current BL and the non-interconnection port information EK to be newly added in the BL after updating the interconnection port list.
And E43, deleting ER in the BL, and adding EK in the BL.
It will be appreciated that after the port interconnect information is adjusted, the original non-interconnect port may be used, and a new non-interconnect port may also appear, so that the information in the BL needs to be updated synchronously.
After synthesis, some timing sequences may be found to need to be adjusted, some registers may be locally added, or debugging may be locally performed, in order to avoid returning modification and improve chip design efficiency, some reserved modules may be newly added under the condition that the chip physical layout area allows, corresponding information is added in advance, so that subsequent direct use is facilitated, as an embodiment, if the chip physical layout still has residual physical area, the method further includes:
In step S6, a reserved chip composition module list VL is added to the physical layer chip design configuration information {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, vl= { V 1,V2,…,Vj,…,VJ},Vj is the J reserved chip composition module, the value range of J is 1 to J, J is the total number of reserved chip composition modules, V j includes a plurality of delay units, or includes a plurality of registers, or includes redundant logic for debugging, and the total area required by V 1,V2,…,Vj,…,VJ is smaller than the remaining physical area.
Each delay unit can delay the transmitted data for one period, so as to realize time sequence adjustment. After the reserved chip comprising the redundant logic for debugging forms a module, the local debugging of the chip can be realized, so that the return to the adjustment of the chip design is avoided, and the chip design efficiency is improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the physical layer chip design is described in a high level through the physical layer chip design configuration information, and the physical layer chip design configuration information is updated according to the chip adjustment information, so that the chip design is adjusted in the physical layer without returning to the logic layer, the modification time of the chip design is reduced, and the efficiency of the chip design is improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. A chip design adjustment method, comprising:
Step S1, acquiring physical layer chip design configuration information {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},, wherein X n_Yn_PLn is the N-th group of physical layer chip interconnection design configuration information, the value range of N is 1 to N, N is the total group number of the physical layer chip design configuration information, X n、Yn is a chip composition module with interconnection relation in the physical layer chip design, the chip composition module is an atomic unit or a module formed by interconnection based on the atomic unit, each atomic unit is provided with a pre-generated RTL code, each chip composition module comprises a sub-module, port information interconnected with the sub-module and port information used for connecting the outside, and PL n is an interconnection port list of X n、Yn;
PLn={(PX1 n,PY1 n),(PX2 n,PY2 n),…,(PXi n,PYi n),…,(PXf(n) n,PYf(n) n)},(PXi n,PYi n) For the ith group of interconnection ports of X n、Yn, the value range of i is 1 to f (n), f (n) is the total number of interconnection ports between X n、Yn, PX i n=（PXTi n,PXWi n）,PXTi n is the ith port identification of X n, PXW i n is the signal direction information between PX i n、PYi n corresponding to X n, PY i n=（PYTi n,PYWi n）,PYTi n is the ith port identification of Y n, and PYW i n is the signal direction information between PX i n、PYi n corresponding to Y n;
BL is an unconnected port list, wherein the unconnected port list comprises unconnected port information in the physical layer chip design, and the unconnected port information comprises a port identifier and a port state;
S2, generating physical layer chip design RTL codes based on the physical layer chip design configuration information and the RTL codes of each atomic unit, performing DFX test based on the design RTL codes, and generating a gate level netlist;
step S3, generating chip adjustment information based on the DFX test and/or the gate level netlist, wherein the chip adjustment information comprises a newly added chip composition module, a deleted chip composition module, a replaced chip composition module and a modified port interconnection;
s4, updating the physical layer chip design configuration information based on the chip adjustment information;
And S5, generating an updated physical layer chip design RTL code based on the updated physical layer chip design configuration information and the RTL code of each atomic unit.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
If the chip adjustment information is a newly added chip composition module, the step S4 includes:
step S41, acquiring a module identifier A of a chip to be newly added and an existing module identifier B of the chip to be newly added, wherein a mapping relation needs to be established with the module identifier A;
Step S42, generating an interconnection port list of A and B based on the port interconnection relation of A and B;
And S43, if the port which is not interconnected exists in the module formed by the chip A, adding the information of the port which is not interconnected and corresponds to the port A into the BL, and if the port which is B in the interconnected port list of the port A and the port B exists in the BL, deleting the port which is B in the interconnected port list of the port A and the port B from the BL.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
If the chip adjustment information is a deletion chip component module, the step S4 includes:
Step C41, obtaining a module identifier E formed by the chip to be deleted;
Step C42, acquiring physical layer chip interconnection design configuration information containing E and non-interconnection port information corresponding to E based on E inquiry {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},;
Step C43, deleting the physical layer chip interconnection design configuration information containing E in {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, and deleting the non-interconnection port information corresponding to E in BL;
and C44, obtaining newly added non-interconnected port information after deleting the physical layer chip interconnection design configuration information containing E, and adding the newly added non-interconnected port information into the BL.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
If the chip adjustment information is a replacement chip component module, the step S4 includes:
Step D41, acquiring a chip composition module identifier G to be replaced and a corresponding replaced chip composition module identifier H;
Step D42, acquiring physical layer chip interconnection design configuration information containing G and non-interconnection port information corresponding to G based on G query {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL},;
Step D43, deleting the physical layer chip interconnection design configuration information containing G in {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, and deleting the non-interconnection port information corresponding to G in BL;
Step D44, acquiring physical layer chip interconnection design configuration information containing H, and deleting the non-interconnection port information HR required to be deleted from the current BL and the non-interconnection port information HK required to be newly added in the BL after constructing the interconnection relation by the H;
And D45, adding the physical layer chip interconnection design configuration information containing H into {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, deleting HR in BL, and adding HK in BL.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
If the chip adjustment information is modification port interconnection, the step S4 includes:
Step E41, obtaining an interconnection port list corresponding to the port interconnection information to be modified;
step E42, updating a corresponding interconnection port list based on the port interconnection information to be modified, and acquiring the non-interconnection port information ER to be deleted from the current BL and the non-interconnection port information EK to be newly added in the BL after updating the interconnection port list;
and E43, deleting ER in the BL, and adding EK in the BL.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
If there is still remaining physical area in the chip physical layout, the method further includes:
In step S6, a reserved chip composition module list VL is added to the physical layer chip design configuration information {X1_Y1_PL1,X2_Y2_PL2,…,Xn_Yn_PLn,…,XN_YN_PLN,BL}, vl= { V 1,V2,…,Vj,…,VJ},Vj is the J reserved chip composition module, the value range of J is 1 to J, J is the total number of reserved chip composition modules, V j includes a plurality of delay units, or includes a plurality of registers, or includes redundant logic for debugging, and the total area required by V 1,V2,…,Vj,…,VJ is smaller than the remaining physical area.
7. An electronic device, comprising:
At least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.
8. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-6.
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