JPH10270564A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the logic simulation more easily when the macro having the different design rule is embedded. SOLUTION: This manufacturing method performs the logic simulation of a total logic circuit in accordance with the combined delay-time data, by combining the delay time data of the entire logic circuit and the delay time data in a macro obtained by the following processes: the characterizing process, which obtains the first delay parameters P1 for the input terminals in the macro connected to the input terminals of the macro 16 including a logic circuit therein and the second delay parameter P3 for the output terminals in the macro cell connected to the output terminals of the macro; and the process for obtaining the delay time data of the entire logic circuit in accordance with the delay parameter of the macro 16, wherein the first delay parameters P1 are made to be the delay parameters of input terminals IN and the second delay parameters P3 are made to be the delay parameters of the output terminals OUT, the delay parameters of a plurality of cells (20-35), and the net liest of the entire logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly, to a method of logic simulation in a design process performed before manufacturing a semiconductor wafer.

[0002]

2. Description of the Related Art Semiconductor integrated circuits are becoming ever more highly integrated. ASICs (Application Sp.) For gate arrays, embedded gate arrays, standard cells, etc.
ecificIntegrated Circuit) is becoming more complicated.

In a normal ASIC design, logical data of a plurality of cells and macro cells designed under a certain design rule and physical data such as pattern data corresponding to the logical data are made into a library, and cells or cells provided in advance in the library are used. Perform logic design using macro cells.
Therefore, in a delay time calculation process and a logic simulation process performed after the logic design, a calculation tool and a logic simulation tool provided under the design rule are used.

A semiconductor integrated circuit is designed by design automation using a data library and a program tool as described above, and its operation is confirmed. After that, an actual pattern for forming an actual chip is designed according to the design data, and the process proceeds to an actual manufacturing process for a semiconductor wafer.

[0005]

However, in recent years, an ASIC method has been proposed in which a large-scale macro designed under a design rule of a third party is embedded in a chip. In other words, not only cells and macro cells (large cells) in the provided library, but also ALUs designed based on completely different design rules,
In this method, a large-scale macro such as a CPU and an MPU is embedded and used in the same chip. Such a large-scale macro may be provided in the library together with the normal cell from the ASIC vendor, or may be provided by mixing a third-party macro obtained by the customer with the normal cell in the library. May be used.

[0006] Semi-standardized macros and the like that have received a certain evaluation in the market will be used rather frequently,
Even if they are not evaluated in the market, there is a demand to use existing macros or macros designed by third parties to save design man-hours for customers.

In that case, how to perform a logic simulation for confirming the operation of the entire chip is a major problem. In particular, in the process of calculating a delay time in a circuit network required for performing a logic simulation, how to merge (merge or merge) a macro with different design rules with a normal cell is a serious problem. .

[0008] As a simple method, a characterization step for obtaining delay parameters for all cells inside a third-party macro is performed from the beginning, and the characterized delay parameters are used to perform the characterization step.
It is conceivable to perform a process of calculating the delay time of the entire chip. However, for every cell in a large macro,
The method of performing the characterization step from step 1 requires tremendous man-hours, and is not compatible with the purpose of using an existing third-party macro. Therefore, a method for solving the above problem is expected.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a method of performing a logic simulation at a chip level of an ASIC having a macro with a small number of steps.

Further, an object of the present invention is to provide an A
It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit having a logic simulation step that can be performed on an SIC with a small number of steps.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device in which a macro having a logic circuit formed therein is embedded in a chip having a plurality of cells. Determining a first delay parameter for the input terminal of the macro cell connected to the input terminal of the macro and a second delay parameter for the output terminal of the macro cell connected to the output terminal of the macro. Characterization step, the first delay parameter as the delay parameter of the input terminal, the second delay parameter of the macro and the delay parameter of the output terminal, the delay parameter of the plurality of cells, According to the connection data of the whole logic circuit constituted by the plurality of cells and the macro, the delay time data of the whole logic circuit Obtaining the delay time data of the entire logic circuit and the delay time data in the macro, and performing a logic simulation of the entire logic circuit according to the combined delay time data. It is characterized by.

When a macro designed under a different design rule from a plurality of cells is embedded in a chip, the delay time data of the macro and the delay of the entire logic circuit obtained by regarding the macro as a normal cell are obtained. By combining the time data, the delay time data of the entire chip can be obtained with a small number of steps. Therefore, a logic simulation process using the same can be performed in a short turn. Even if the design rules are different, since the delay time data described in the SDF (Standard Delay Format) standardized by IEEE has compatibility, the above-described merging becomes possible. However, regarding the delay time at the input terminal and the output terminal of the macro, a delay parameter is obtained in the characterization step, and the delay time in the entire logic circuit is obtained by using the parameter.

More specifically, the first delay parameter is a parameter dependent on an input slew rate,
An input delay time is obtained from the input slew rate by the logic circuit and the first delay parameter.

The second delay parameter is a parameter dependent on the output load capacitance, and the output delay time is obtained from the load capacitance by the logic circuit and the second delay parameter.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to the embodiment.

FIG. 1 is a flow chart of a manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention. In this flowchart example, first, the logic of the entire chip is designed using cells and the like registered in advance in the logic library (S10). At this time, in the present embodiment, a macro provided by a third party is simultaneously used in addition to the normal cells in the logic library. This macro has already been designed to the level of the actual mask pattern through logic design and logic simulation. As a result of this logic design, a netlist for the network of the logic circuit is created.

Next, a delay time in the circuit network is calculated for the designed logic circuit (S11). The delay time includes, for example, a delay time at an input terminal of a cell provided in the network, a delay time of the cell itself, a delay time at an output terminal, and the like. Generally, the delay time at the input terminal is determined depending on the input slew rate determined by the driving capability and the wiring capacity of the preceding cell. Further, the delay time at the output terminal is determined depending on the driving capacity such as the load capacity of the wiring to the subsequent cell and the capacity of the input terminal of the cell. Therefore, a delay parameter indicating dependence on the input slew rate and a delay parameter indicating dependence on the output load are given to the cells registered in the logic library as characterization data.

Therefore, the delay time in the circuit network is calculated based on the net list and the delay parameter obtained in step S10 (S11). This delay time is preferably described in accordance with SDF (Standard Delay Format) standardized by IEEE. This SDF can express a delay time in a circuit network with a standardized delay time using a standardized syntax, even for a logic circuit formed by different design rules. Therefore, SD
Various logic simulation programs can be used for the delay time data described in accordance with F.

Next, the logical function of each cell (Function)
n), a logic simulation is performed using the delay time data and the test pattern by the SDF (S1).
2). In this logic simulation, it is confirmed that the operation of the logic circuit, such as whether an expected output pattern is output at an expected timing when a predetermined test pattern is input, is performed normally.

In the logic simulation step, if it is confirmed that the circuit operates normally as a logic circuit, a layout step is performed for each cell and wiring on the chip (S13).

Then, the delay time calculation (S14) and the logic simulation (S15) are performed again based on the layout, and the operation in the layout state on the chip is checked again. When this is completed, the process finally proceeds to the manufacturing process for a semiconductor wafer (S16).

The above is the outline of the manufacturing process of the semiconductor integrated circuit. Therefore, before describing the above-described delay time calculation for performing a logic simulation of an ASIC having a macro, a general normal cell characterization, a delay parameter, a normal cell data example, a logic circuit netlist and a delay The time calculation will be briefly described below.

[Example of Data of Normal Cell] FIG. 2 is a diagram showing an example of the data structure of a normal cell. In this example, the data structure of the cell X is shown. The attribute data of the cell X has at least the data of the logic function (Function) of the cell, the delay parameters P1, t2, P3, the capacity of the input terminal and the capacity of the output terminal. Here, the delay parameters P1, t2,
P3 will be described.

[Characterization of Normal Cell and Delay Parameter] FIG. 3 is a diagram for explaining characterization of a normal cell. FIG. 3 shows an example of the cell X. The logic function of the cell X is, for example, a flip-flop, a logical product, a logical sum, or an exclusive logical sum. The cell X has a delay time at the input terminal that depends on an input slew rate Tsin at the input terminal, a delay time t2 of the cell itself, a driving capability of the cell, and a load capacitance C to be driven.
The delay time at the output terminal depends on L.

The input slew rate Tsin is, for example, the rising slope of the input signal, and depends on the output driving capability of the preceding cell and the load capacity of the wiring and the like. If this slope is steep, the input slew rate is small, and the delay time at the input terminal is short. The load capacitance CL is a capacitance added to an output terminal and a wiring to a next cell.

The delay time at the input terminal of the cell X depends on the input slew rate Tsin described above. Generally, the shorter the input slew rate, the shorter the delay time. Thus, when a delay circuit P1 is given to the input terminal of the cell X to design a logic circuit and an input slew rate is given from the logic circuit, the delay time t1 at the input terminal is calculated from the delay parameter P1 and the input slew rate Tsin. Is required. Therefore, the delay parameter P1 is given as the attribute data of the cell X.

The delay time at the output terminal of cell X is
The delay time depends on the load capacitance CL described above. Generally, the larger the load capacitance CL, the longer the delay time. Therefore, when the delay parameter P3 is given to the output terminal of the cell X and a logic circuit is designed and the load capacitance CL is given from the logic circuit, the delay time t3 at the output terminal is obtained from the delay parameter P3 and the load capacitance CL. Desired.

FIG. 4 is a diagram for explaining that the delay time is obtained from the delay parameter, the input slew rate of the logic circuit, and the load capacitance. As described above, of the attribute data of the cell X, the delay parameters (P1, t2, P3) are extracted from the logic library, and the delay time t1, t1 of the input terminal is determined according to the input slew rate Tsin and the load capacitance CL given from the logic circuit. The delay time t2 of the cell itself and the delay time t3 of the output terminal are obtained. The obtained delay time is described according to the above-mentioned SDF.

The delay parameter described in FIG.
It is determined in the cell X characterization process. This characterization step is performed, for example, using Hsp manufactured by Metasoft.
This is performed by a spice simulator such as ice (trade name). In this simulator, the delay parameters P1 and P3 are obtained by providing a characteristic parameter of a transistor constituting a cell and a netlist indicating a connection relation of the transistor. More specifically, the delay parameter P1 of the input terminal is obtained from the delay time of the input terminal when the input slew rate Tsin is changed, based on the given transistor characteristic parameters and netlist. Further, the delay parameter P3 of the output terminal is obtained from the delay time of the output terminal when the load capacitance CL connected to the output terminal is changed.

Normally, when a cell is registered in a logic library, a delay parameter (P1, t2, P3) is obtained by a spice simulator by giving a transistor characteristic parameter and a netlist for the cell in advance. This delay parameter is given as cell attribute data as described above.

[Net List] FIG. 5 is a diagram showing an example of a logic circuit. FIG. 6 is a diagram showing an example of a netlist of the logic circuit shown in FIG. In the example of the logic circuit shown in FIG. 5, a cell X and a cell Y are connected as shown between input terminals A and B and an output terminal C of the logic circuit. The cell X has an input terminal (port) a and an output terminal b, and the cell Y has input terminals a and b and an output terminal c. Then, these are connected by wirings Net-1 to Net-4.

With respect to the example of the logic circuit shown in FIG. 5, the net list is described, for example, as shown in FIG. That is,
The ports (Port) of the input terminal and the output terminal are A, B,
The ports pA, pB, and pC, and the input and output terminals of each cell are described as Xpa, Ypb, and the like. Then, each of the wirings Net-1 to Net-
4 are described as shown. In this example, port names at both ends of each wiring are described. This netlist becomes attribute data of the logic circuit when the logic design (S10 in FIG. 1) is completed.

As can be understood from the above description, first, a delay parameter is obtained by a cell characterization step, and the obtained delay parameter is registered as cell attribute data. Then, as a result of the logic design, a netlist of the logic circuit is formed. The input slew rate and the load capacity are obtained for each cell from the netlist. Then, the delay time of the logic circuit is obtained from the delay parameter and their input slew rate and load capacity. Then, a logic simulation is performed based on the data of the logic function of the cell and the delay time (SDF format) obtained above.

[ASIC with Macro] FIG. 7 is a diagram showing an example of the configuration of an entire ASIC chip with a macro. In this example, a gate array block SOG
(Sea of Gates) 14, a memory cell 12, and a macro 16 provided by a third party are formed. A plurality of input / output cells 18 are provided around the chip 10.

As described above, when the macro 16 provided by a third party is mixed in the chip, how to calculate the delay time necessary for the above-described logic simulation process becomes a problem. That is, in a macro created based on a different design concept, it is not possible to obtain delay parameters for the cells in the macro. Therefore, the delay parameter of each cell and the input slew rate and load capacity from the macro netlist are calculated. The used delay time calculation cannot be performed.

FIG. 8 is a diagram showing a configuration in which macros and normal cells are mixed for explaining the logic simulation process according to the present embodiment. In this example, the macro 16 has internal cells 161, 162, and 163 connected to the macro input terminals IN1, IN2, and IN3, respectively. Also, macro output terminals OUT4, OUT5, O
Internal cells 164 and 16 respectively connected to UT 6
5,166. Further, the macro 16 has internal cells 167, 168, and 169. The solid line and the broken line shown in FIG. 8 are connection examples. Next, normal cells 20 to 35 are provided in the gate array 14. The dashed lines connecting these are merely examples.

The configuration shown in FIG. 8 is obtained at the time when the overall logic design step (S10) in FIG. 1 is completed. Therefore, this configuration is described by a netlist including the macro 16.

As described above, the cell 1 in the macro 16
Knowing the characterized delay parameters for 61-169 is usually not possible. Therefore, it is conceivable to characterize all the internal cells using a Spice simulator using the characteristic parameters of the transistors of each cell and a netlist. As a result, for example, as shown in FIG. 9, the cells 161 to 169 in the macro 16 and the cells 20 to 35 in the gate array 14 are set to the same level, and their delay parameters and the netlist of all cells are set. , The delay time in the chip 10 can be obtained by calculation. However, since the macro 16 itself has an enormous number of cells, characterization of all the cells 161 to 169 inside the macro requires an enormous number of man-hours, which is not practical.

Therefore, in this embodiment, the macro 16
Is regarded as a black box, and the macro 16 is treated as a cell equivalent to a normal cell, thereby greatly reducing the man-hour of the operation process of the delay time required for the logic simulation.

Since the macro is provided by a third party, it is not possible to obtain the delay parameter of the cell inside the macro. Even if the delay parameter can be obtained, the delay parameter is data under different design rules, and there is no consistency with the delay parameter of a normal cell. However, the operation of the macro has already been confirmed by logic simulation,
This is a kind of LSI completed up to the mask pattern. Therefore, a delay time according to the SDF can be provided as attribute data of the macro.

By combining or merging the data of the delay time by the SDF of this macro with the data of the delay time by the SDF calculated from the logic circuit of the normal cell in the gate array 14, the whole chip necessary for the logic simulation is obtained. In this case, the number of man-hours for calculating the delay time can be greatly reduced.

FIG. 10 is a diagram showing an example of macro attribute data. In this example, the netlist in the macro, the data describing the delay time of the circuit network in the macro based on the SDF, the logical function (Function) of the internal cell, the data of the transistor in the internal cell, and the actual pattern of the macro As attribute data. The data of the delay time according to the SDF matches the data describing the delay time of the normal circuit in the logic circuit according to the SDF. This S
This is because the DF is standardized by the IEEE as a delay time description format.

Accordingly, the delay time due to the SDF in the macro 16 and the S of the logic circuit of the normal cell in the gate array 14
The delay time by the DF is combined. In such a case, as shown in FIG.
, The input terminal IN of the macro 16
The input slew rate Tsin to 1, IN2 and IN3 is
This cannot be obtained unless the logic circuit of the entire chip is designed. That is, the input slew rate depends on the load capacity of the preceding cells 20, 21, 22 and the wiring between them. Similarly, the load capacitance CL to the output terminals OUT4 to OUT6 of the macro 16 cannot be obtained unless the logic circuit of the entire chip is designed. That is, the load capacitance CL of the output terminal depends on the wiring length between the output cell and the subsequent cell.

Therefore, since the delay time at the input terminal and the output terminal of the macro 16 depends on the logic circuit in the gate array, the data of the delay time by the SDF given as the attribute data of the macro cannot be used as it is. .

Therefore, in this embodiment, the macro 16
Only the delay parameters of the input terminals 161 a to 163 a and the output terminals 164 b to 166 b of the cells 161 to 166 connected to the input terminal and the output terminal among the cells in
Determined by a characterization process using a ce simulator. Only the delay parameters of the input terminals of the cells 161 to 163 on the input side are sufficient, and it is not necessary to calculate the delay time of the cells 161 to 163 and the delay parameter of the output. Similarly, only the delay parameters of the output terminals of the output cells 164 to 166 are required. Therefore, these characterization steps do not require much man-hour.

The input-side cells 161 to 161 thus obtained
The delay parameter of the input terminal 163 is given as the delay parameter of the input terminals IN1 to IN3 of the macro 16.
Similarly, the delay parameters of the output terminals of the cells 164 to 166 on the output side are given as the delay parameters of the output terminals OUT4 to OUT6 of the macro 16.

FIG. 11 is a diagram showing a logic circuit in a chip when the macro 16 is handled as a cell. As described above, the input terminals IN1 to IN3 and the output terminal OUT of the macro 16
4 to 6, delay parameters P11, P12, P13, P3
4, P35 and P36 are given to make the inside a black box. Then, in the normal cells 20 to 35 in the gate array 14, delay parameters P1 and P3 are respectively extracted from the logic library. In the configuration of such a logic circuit, the input slew rate Tsin and the capacitance load CL are obtained from the net list, and the delay time t1 at the input terminal and the delay time t3 at the output terminal of each cell are calculated by a predetermined delay time calculation program. Can be requested.

Then, the delay time data in the entire chip can be obtained by merging the delay time data in the chip and the delay time data in the macro. However, at that time, the input terminal I of the macro 16 obtained above
It is necessary to give the delay times at N1 to N3 again as the delay times at the input terminals 161a to 163a of the cells 161 to 163 on the input side of the macro 16. Similarly, the delay times at the output terminals OUT4 to OUT6 of the macro 16 determined above are given as the delay times at the output terminals 164b to 166b of the cells 164 to 166 on the output side of the macro 16 again. That is, the data of the delay time is added to the data of the delay time by the SDF of the macro 16.

Therefore, it should be noted that the macro 16
In the process of generating the delay time data by the DF, it is necessary to calculate the input slew rate Tsin for the input terminals 161a to 163a of the cells 161 to 163 of the input stage to zero. Similarly, cells 164 to 164 of the output stage
It is necessary that the load capacitance CL for the output terminals 164b to 166b of 166 is also set to zero and the calculation is performed in advance. That is, the data of the delay time of the cells 161 to 163 of the input stage is (0, t2, t3), for example, and the cell 1 of the output stage is
The data of the delay time of 64-166 is, for example, (t1,
t2,0).

In this way, the delay times t11, t12, t13, t34, t34,
t35 and t36 are set to the input terminals 161a to 161a of the corresponding cell.
Even if the delay time is given as the delay time between the output terminal 163a and the output terminals 164b to 166b, the delay time can be prevented from overlapping. That is, the data of the delay time of the cells 161 to 166 is, for example, cell 161 = (t11, t2, t3) cell 162 = (t12, t2, t3) cell 163 = (t13, t2, t3) cell 164 = (t1) , T2, t34) Cell 165 = (t1, t2, t35) Cell 166 = (t1, t2, t36)

FIG. 12 is a flowchart showing steps up to the above-described logic simulation of a logic circuit of a chip having a macro. That is, it is a flowchart from step S10 to step S12 in FIG. Alternatively, it is also a flowchart of steps S14 and S15 in FIG.

First, the logic of the entire chip in which the macro is embedded is designed (S20). 9 is a design of the logic circuit shown in FIG. 8. As a result, a netlist of the logic circuits in the chip is created. The logic functions and delay parameters of the normal cells 20 to 35 are registered in the logic library in advance. Further, the data of the macro 16 is provided together with the macro. This data includes S shown in FIG.
It has delay time data by DF. However, it is preferable that the delay time data is obtained assuming that the input slew rate is zero at the input terminal of the cell on the input side. Further, it is preferable that the delay time data is obtained assuming that the load capacitance is zero at the output terminal of the cell on the output side.

Next, in order to handle the macro 16 in the same manner as a normal cell, the minimum necessary input / output terminal characterization is performed (S21). That is, the delay parameter P1 regarding the input slew rate dependence of the input terminal IN and the output terminal O
Delay parameter P3 for UT load capacitance CL dependence
And ask. In this characterization step, delay parameters are obtained by a Spice simulator for the input terminals of the internal cells 161 to 162 connected to the input terminals, and further, the internal cells 164 to 1 connected to the output terminals are determined.
For the output terminals 66, the delay parameter is obtained by a Spice simulator.

Then, the internal structure of the macro 16 is made into a black box, and the above-mentioned obtained delay parameters P1 and P3 are given to the input / output terminals, and the macro 16 is handled in the same manner as other normal cells. The delay time is calculated (S22). As a result, delay time data according to the SDF is obtained. The calculation of the delay time is performed using a netlist of the logic circuit of the entire chip, a registered delay parameter of a normal cell, a delay parameter of an input / output terminal of the macro 16, and the like.

Next, at step S23, the delay time data of the macro input / output terminal obtained at step S22 is added to the delay time data of the macro 16 by the SDF, and the delay time of the input terminals of the internal cells 161 to 163 on the input side. It is given as the time and the delay time of the output terminals of the internal cells 164 to 166 on the output side. Then, the delay time data based on the SDF of the entire chip and the delay time data based on the SDF of the macro are merged (S24).

Thereafter, a logic simulation is performed by using the netlist of the entire chip, the logic function of the normal cell, the netlist in the macro, the logic function of the internal cell, and the combined delay time data (S25). . This logic simulation is performed, for example, by using Verilog-XLL.
(CADENCE product name) or the like.

In step S24, the delay time data of the embedded macro and the delay time data of the logic circuit of the normal cell in the chip by the SDF are merged.
However, there are cases where the design process of the macro provided by the third party is completed and cases where it is not completed. In particular, when the design process of some macros is not completed, the delay time data in the macro is not given until the design process of the macro is completed.

In this case, if the logic simulation process of the whole chip is made to wait until the delay time data of all the macros is given, the whole manufacturing process eventually takes a long time. Therefore, when calculating the delay time data in the macro, and when the actual layout is completed,
The delay time data obtained according to the actual layout is used. For a macro for which the actual layout is not completed, the delay time data obtained according to the virtual wiring is used. As a result, the macro designing process and the entire chip designing process can be performed in parallel, and the manufacturing process can be shortened.

Further, when the delay time data by the SDF of a plurality of macros embedded in a chip is obtained at a predetermined specified power supply voltage, a different power supply voltage is applied to the macro in a state of being embedded in the chip. May be In such a case, the delay time data at the power supply voltage in the chip can be obtained by multiplying the delay time data at the specified power supply by a coefficient corresponding to the ratio of the power supply voltage. When the frequency of the internal clock is different besides the power supply voltage, similarly, the SDF given together with the macro
It is desirable to correct the delay time data due to.

FIG. 13 is an overall configuration diagram of the above-described LSI design system. Using this design system, Figure 1
2 are performed. Alternatively, each of the steps S10 to S15 in FIG. 1 is executed.

In this system, a file 11 storing a logical library, a file 12 storing a physical library, a file 13 storing designed circuit data, and a file 1 storing a test pattern are stored in the CPU 10.
4, and a file 15 in which layout data is stored
Is connected. Further, a Spice simulator program for characterizing, a delay time calculation program, a logic simulation program, a layout program, and the like are stored in the file 16 as a design tool.

In the physical library 11, attribute data such as logic functions of normal cells and macro cells, respective delay parameters, and respective terminal capacities are registered. In the physical library 12,
The circuit pattern of each cell is registered. When a logic circuit is designed using the cells registered in the logic library, the designed circuit data such as a netlist is stored in the file 14. The test pattern is a pattern of input data used in the logic simulation and output data thereof.

The layout of the actual circuit in the chip can be designed using the layout data having the mask data.

[0064]

As described above, according to the present invention, in an ASIC such as a gate array which embeds macros having different design rules provided by a third party, the macro S
By using the delay time data according to the DF, the logic simulation can be performed with a small number of steps.

[Brief description of the drawings]

FIG. 1 is a flowchart of a manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a data structure of a normal cell.

FIG. 3 is a diagram for explaining characterization of a normal cell.

FIG. 4 is a diagram illustrating that a delay time is obtained from a delay parameter, an input slew rate of a logic circuit, and a load capacitance;

FIG. 5 is a diagram illustrating an example of a logic circuit.

6 is a diagram illustrating an example of a netlist of the logic circuit illustrated in FIG. 5;

FIG. 7 is a diagram illustrating a configuration example of an entire ASIC chip with a macro;

FIG. 8 is a diagram illustrating a configuration in which macros and normal cells are mixed for explaining a logic simulation process according to the embodiment;

FIG. 9 is a diagram illustrating a configuration in which macros and normal cells are mixed for describing a logic simulation process according to the embodiment;

FIG. 10 is a diagram illustrating an example of attribute data of a macro.

FIG. 11 is a diagram showing a logic circuit in a chip when the macro 16 is handled as a cell.

FIG. 12 is a flowchart showing steps up to logic simulation of a logic circuit of a chip having a macro.

FIG. 13 is an overall configuration diagram of an LSI design system.

[Explanation of symbols]

 10 chip 14 plural cell areas 16 macro P1, P3 delay parameter t1, t3 delay time IN macro input terminal OUT macro output terminal

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device in which a macro having a logic circuit formed therein is embedded in a chip having a plurality of cells, wherein an input terminal of a cell in the macro connected to an input terminal of the macro is provided. Characterizing a first delay parameter and a second delay parameter for the output terminal of the macro cell connected to the output terminal of the macro; and And the delay parameter of the macro with the second delay parameter as the delay parameter of the output terminal, the delay parameter of the plurality of cells, and the connection data of the entire logic circuit configured by the plurality of cells and the macro. Therefore, a step of obtaining the delay time data of the entire logic circuit; The method of manufacturing a semiconductor integrated circuit device characterized by a step of performing a logic simulation of the entire logic circuit united with the delay time data in the macro, according to the combined delay time data. 2. The method according to claim 1, wherein the first delay parameter is a parameter dependent on an input slew rate, and an input delay time is obtained from the input slew rate and the first delay parameter by a logic circuit. A method for manufacturing a semiconductor integrated circuit device, comprising: 3. The method according to claim 1, wherein the second delay parameter is a parameter dependent on an output load capacity, and an output delay time is obtained from the load capacity and the second delay parameter by a logic circuit. A method for manufacturing a semiconductor integrated circuit device, comprising: 4. A method of manufacturing a semiconductor integrated circuit device in which a macro in which a logic circuit is formed inside a chip having a plurality of cells and to which internal delay time data is given is embedded, wherein the macro is connected to an input terminal of the macro. A first delay parameter depending on the input slew rate of the input terminal of the input side macro cell, and a second delay parameter depending on the output load capacity of the output terminal of the output side macro cell connected to the output terminal of the macro. A characterization step of obtaining a second delay parameter; and the macro delay parameter, wherein the first delay parameter is a delay parameter of the input terminal, and the second delay parameter is a delay parameter of the output terminal. The delay parameters of the plurality of cells and the connection data of the entire logic circuit constituted by the plurality of cells and the macro. Obtaining the delay time data of the entire logic circuit including the delay time data of the input terminal and the output terminal of the macro and the delay time data of the plurality of cells; Providing the input terminal and output terminal delay time data as the input terminal delay time data of the input-side macro cell and the output terminal delay time data of the output-side macro cell, respectively. A semiconductor integrated circuit comprising: a step of combining delay time data of a circuit and delay time data in the macro; and a step of performing a logic simulation of the entire logic circuit according to the combined delay time data. Device manufacturing method. 5. The system according to claim 4, wherein the delay time data in the macro and the delay time data of the entire logic circuit are both SDF (Standard Delay Format).
A method for manufacturing a semiconductor integrated circuit device described according to (t). 6. The delay time data in the macro according to claim 4, wherein an input slew rate to an input terminal of the input-side macro cell is zero, and a load to an output terminal of the output-side macro cell is set. A method for manufacturing a semiconductor integrated circuit device, wherein a capacity is obtained as zero and is given to the macro in advance. 7. The method according to claim 4, wherein, in the step of obtaining the delay time, the plurality of cells have at least a first delay parameter dependent on an input slew rate and a second delay parameter dependent on an output capacitance load. Then, the delay time of the input terminal of the cell and the macro is obtained from the input slew rate according to the entire logic circuit, the first delay parameter of the cell, and the delay parameter of the input terminal of the macro. A method of manufacturing a semiconductor integrated circuit device, comprising: determining a delay time of an output terminal of a cell and a macro from a load capacitance, a second delay parameter of the cell, and a delay parameter of an output terminal of the macro. 8. The apparatus according to claim 4, wherein said plurality of macros are provided, and delay time data given to each macro is corrected in accordance with a power supply voltage of said macro in said overall logic circuit. A method for manufacturing a semiconductor integrated circuit device. 9. The method according to claim 4, wherein the macro and the plurality of cells are logically designed according to different design rules.