CN117573551A - Multi-stage control method based on chip function coverage rate, electronic equipment and medium - Google Patents
Multi-stage control method based on chip function coverage rate, electronic equipment and medium Download PDFInfo
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Abstract
The invention relates to the technical field of chips, in particular to a multi-level control method, electronic equipment and medium based on the coverage rate of chip functions, wherein the method comprises the following steps of S1, acquiring a chip function characteristic list and a chip composition module list; step S2, each F is processed n Splitting the chip into a plurality of sub-functional features, and dispersing the plurality of sub-functional features of each chip functional feature into a plurality of chip component modules; step S3, based on all F n Sub-feature of (a) respectively constructs the whole chip and each M k A corresponding multi-level control table; step S4, based on the whole chip and each M k The corresponding multi-stage control table generates a chip function coverage rate verification code. The invention improves the verification efficiency of the functional coverage rate of the chip.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip function coverage rate-based multi-level control method, an electronic device, and a medium.
Background
In the process of developing a chip, after developing a chip product, a series of parallel developed chip products are usually required to be quickly and iteratively derived, the derived chip products are usually only partially changed based on the functional characteristics of the originally developed chip products, and the chip verification process also only needs to partially adjust the chip codes for partially verifying the functional coverage rate of the chip. However, the existing chip has a large scale and a large number of functional features (features), and the existing technology cannot directly make local adjustment based on the chip code of the verification chip functional coverage of the originally developed chip product. Usually, a great deal of time is required to be spent, and related codes are compiled based on the function feature list of the derivative product to re-compile and verify the chip function coverage rate, so that the chip function coverage rate verification of the derivative product is realized, the chip function coverage rate verification efficiency is low, the chip development period is long, the development efficiency is low, and the cost is high.
Disclosure of Invention
The invention aims to provide a chip function coverage rate-based multi-stage control method, electronic equipment and medium, which improve the chip function coverage rate verification efficiency.
According to a first aspect of the present invention, there is provided a chip function coverage rate-based multi-stage control method, including:
step S1, obtaining a chip function feature list { F } 1 ,F 2 ,…,F n ,…,F N Sum chip composition module list { M } 1 ,M 2 ,…,M k ,…,M K }, wherein F n The value range of N is 1 to N, N is the total number of the functional characteristics of the chip, M k For the kth chip forming module, the value range of K is 1 to K, K is the total number of the chip forming modules, all the chip forming modules are arranged in a hierarchical manner to form a tree structure, M 1 Is a top layer module.
Step S2, each F is processed n Splitting the module into a plurality of sub-functional features, and dispersing the sub-functional features of each chip functional feature into a plurality of chip component modules, wherein one of the sub-functional features is arranged in a top layer module, and if other component modules other than the top layer module are provided with one of the sub-functional features, a father module of the component module is necessarily provided with one of the sub-functional features.
Step S3, based on all F n Sub-feature of (a) respectively constructs the whole chip and each M k Corresponding multi-stage controlThe multi-level control table comprises first-level control information, second-level control information and third-level control information, wherein the control level of the first-level control information is sequentially reduced, the first-level control information is used for controlling a switch for verifying the coverage rate of the whole chip function, the second-level control information is used for respectively controlling a switch for verifying the coverage rate corresponding to each chip function feature or sub-function feature, and the third-level control information is used for controlling a coverage rate verification feature corresponding to each function feature or sub-function feature.
Step S4, based on the whole chip and each M k The corresponding multi-stage control table generates a chip function coverage rate verification code.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip function coverage rate-based multi-stage control method, the electronic equipment and the medium can achieve quite technical progress and practicality, and have wide industrial utilization value, and the chip function coverage rate-based multi-stage control method at least has the following beneficial effects:
the invention divides each chip functional characteristic into a plurality of sub-functional characteristics which are respectively arranged in corresponding chip composition modules to construct the whole chip and each M k Corresponding multi-level control table based on the whole chip and each M k Corresponding multistage control standard flexibly controls configuration information of chip function coverage rate verification based on the whole chip and each M k The corresponding multi-stage control table generates a chip function coverage rate verification code.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a multi-stage control method based on chip function coverage rate according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a chip function coverage rate-based multi-stage control method, which is shown in fig. 1 and comprises the following steps:
step S1, obtaining a chip function feature list { F } 1 ,F 2 ,…,F n ,…,F N Sum chip composition module list { M } 1 ,M 2 ,…,M k ,…,M K }, wherein F n The value range of N is 1 to N, N is the total number of the functional characteristics of the chip, M k For the kth chip forming module, the value range of K is 1 to K, K is the total number of the chip forming modules, all the chip forming modules are arranged in a hierarchical manner to form a tree structure, M 1 Is a top layer module.
The top-layer modules are constituent modules without father modules and with only child modules, and the non-top-layer modules are all provided with father modules. The Chip generally comprises an SOC (System-on-a-Chip) module, the SOC module comprises a IP (Intellectual Property) module, the large-scale IP module may further comprise a small-scale IP module or subsystem (Sub System) module, the small-scale IP module may further comprise a Block module, it is understood that the SOC module is a top-layer module, the non-top-layer follow-up module may be an SOC module, an IP module, a Sub System module, a Block module, and the hierarchical relationship of each component module is known, that is, a parent-child module of each component module is known, and a sibling module is also known.
Step S2, each F is processed n Splitting the module into a plurality of sub-functional features, and dispersing the sub-functional features of each chip functional feature into a plurality of chip component modules, wherein one of the sub-functional features is arranged in a top layer module, and if other component modules other than the top layer module are provided with one of the sub-functional features, a father module of the component module is necessarily provided with one of the sub-functional features.
Step S3, based on all F n Sub-feature of (a) respectively constructs the whole chip and each M k The corresponding multi-stage control table comprises first-stage control information, second-stage control information and third-stage control information, wherein the control level of the first-stage control information, the second-stage control information and the third-stage control information is sequentially reduced, the first-stage control information is used for controlling a switch for verifying the coverage rate of the whole chip function, the second-stage control information is used for respectively controlling a switch for verifying the coverage rate corresponding to each chip function feature or sub-function feature, and the third-stage control information is used for controlling a coverage rate verification feature corresponding to each function feature or sub-function feature.
Step S4, based on the whole chip and each M k The corresponding multi-stage control table generates a chip function coverage rate verification code.
As an embodiment, step S2 includes:
step S21, obtaining a chip function feature list { F 1 ,F 2 ,…,F n ,…,F N }, wherein F n The value range of N is 1 to N, and N is the total number of the functional features of the chip.
Step S22, F n Splitting into g (n) sub-functional features { F 1 n ,F 2 n ,…,F x n ,…,F g(n) n }，F x n Is F n Is the x th sub-functional feature of (2)Wherein x is in the range of 1 to g (n), and g (n) is F n The total number of sub-functional features of (C) and g (n) is more than or equal to 1.
It should be noted that when n takes different values, the value of g (n) may also be different, i.e. each F n The number of sub-functional features partitioned may not be the same. Each sub-feature is implemented by a corresponding chip composition module, if one F n Without resolution, g (n) =1.
Step S23, establishing F 1 n And M is as follows 1 Corresponding relation of M 1 Is a top layer module.
The top-layer modules are constituent modules without father modules and with only child modules, and the non-top-layer modules are all provided with father modules.
Step S24 is F y n Setting corresponding M i ,F y n Is F n Y has a value ranging from 2 to g (n), M i For the ith chip to form a module, the value of i ranges from 2 to K, each of which is equal to F y n M for setting corresponding relation i The parent module must be identical to one of F x n And establishing a corresponding relation.
It should be noted that each F needs to be implemented in the top module n Each F is a sub-functional feature of n In addition to the sub-features already implemented by the top-level module, may be distributed among other non-top-level modules, but one non-top-level module is provided with F n If the sub-functional feature of the module is not the top-level module, F is set in the parent module corresponding to the tree structure constructed by the chip composition module n Is a sub-functional feature of (a). After the setting is completed, a plurality of different F's can be set in one chip composition module n Is a sub-functional feature of (c).
As an embodiment, the parameter information corresponding to the sub-functional feature includes fixed parameter information, first type variable parameter information and second type variable parameter information. The fixed parameter information is parameter information which always needs to exist and does not need to be changed, such as a functional characteristic identifier.
The first type of variable parameter information comprises a first identifier and a second identifier; when the first type variable parameter information is set as a first identifier, the corresponding sub-function feature is indicated to be valid; and when the first type variable parameter information is set as the second identifier, the corresponding sub-function feature is invalid, and the first type variable parameter information is set as the first identifier by default. By switching the first identifier and the second identifier of the first type variable parameter information, the setting of the corresponding sub-functional feature can be controlled, namely, when a certain sub-functional feature does not need to be realized, only the identifier information of the corresponding first type variable parameter information is changed in the configuration file.
The second type of variable parameter information comprises adjustable parameters, and parameters corresponding to the sub-functional features are set by adjusting the numerical value or the range of the adjustable parameters. It should be noted that, for one variable parameter, corresponding second type variable parameter information may be set.
As an embodiment, the first-level control information includes a chip function coverage rate switch identifier, and when the chip function coverage rate switch identifier is set to be an openable identifier, the first-level control information indicates that a chip function coverage rate verification code needs to be generated; when the chip function coverage rate switch identifier is set to be a closing identifier, the fact that the chip function coverage rate verification code is not required to be generated is indicated, and the second-level control information and the third-level control information are all set to be in a closing state. The generation of the whole chip functional coverage rate code can be controlled through the first-level control information.
As one embodiment, the second level control information includes a feature control list, and the second level control information of the multi-level control list corresponding to the whole chip includes all F n Each F n Corresponding switch identification, M k The second level control information of the corresponding multi-level control table comprises M k All corresponding sub-function identifiers and switch identifiers corresponding to each sub-function feature; when F n Corresponding switch identification or M k F when the switch mark corresponding to the corresponding sub-functional feature is set as the closing mark n Corresponding switch identification or M k The third-level control information corresponding to the corresponding sub-functional feature is all set to the off state. Needs to be as followsIllustratively, the second level control information sets all F n Can be selected from F n Is controlled at the level of F n When the corresponding switch is marked as being in the off state, when M k Middle F of corresponding multi-stage control table n The switch identification corresponding to the corresponding sub-function is correspondingly closed. In addition, can also be from M k Is a layer of the above-mentioned (a). By M k The second-stage control information of the corresponding multi-stage control table controls the switch of each sub-functional feature, so that the multi-dimensional flexible control is realized.
Wherein the coverage verification feature is a functional coverage verification feature or an Assertion (Assertion) verification feature.
As an embodiment, if the coverage verification feature is a functional coverage verification feature, the third level control information is divided into 3.1 level control information, 3.2 level control information and 3.3 level control information with control levels sequentially reduced, wherein the 3.1 level control information includes each F n Or the coverage group corresponding to the sub-functional characteristics and the coverage group switch identification, and each F is controlled through the coverage group switch identification n Or opening and closing of the coverage group corresponding to the sub-functional feature. The 3.2-level control information comprises a coverage point corresponding to each coverage group and a coverage point switch identifier, and the corresponding coverage points in each coverage group are controlled to be opened and closed through the coverage point switch identifier. The 3.3-level control information comprises a bin corresponding to each coverage point and a switch identification of the bin, each bin is realized through the switch identification of the bin, and the opening and closing of the bin corresponding to each coverage point are controlled through the switch identification. When the coverage group switch is in an off state, the coverage group is at a coverage point corresponding to the 3.2-level control information, and all bins corresponding to all coverage points of the coverage group in the 3.3-level control information are all set in the off state. When the coverage point switch is in the off state, all bins corresponding to the coverage point in the 3.3 level control information are all set to the off state.
For the scene with the cross coverage point, as an embodiment, the third level control information further includes 3.4 level control information, the 3.4 level control information includes the cross coverage point and a cross coverage point switch identifier, the cross coverage point is a cross item formed by two coverage points in the 3.2 level control information, and when any one coverage point of the cross coverage point is set to be in a closed state in the 3.2 level control information, the corresponding cross coverage point is also set to be in the closed state.
As an embodiment, the step S3 includes:
step S10, the first generated whole chip and each M k The corresponding multi-level control table serves as an initial multi-level control list.
Step S20, acquiring the update configuration information of the chip functional coverage rate, wherein the update configuration information of the chip functional coverage rate comprises the functional feature identifiers required to be updated and the coverage rate configuration information corresponding to the functional feature identifiers required to be updated.
It should be noted that, the functional feature identifier may be updated according to a specific application scenario, only the coverage rate configuration information corresponding to the functional feature identifier may be updated, or the functional feature identifier and the coverage rate configuration information corresponding to the functional feature identifier may be updated at the same time, and may be updated flexibly according to a specific application scenario.
And step S30, updating the initial multilevel control list based on the functional characteristic identifiers required to be updated and coverage rate configuration information corresponding to the functional characteristic identifiers required to be updated.
It should be noted that, based on the functional feature identifier to be updated and the coverage rate configuration information corresponding to the functional feature identifier to be updated, the corresponding information in the initial multi-stage control list is directly updated.
And S40, generating updated chip function coverage rate verification codes based on the updated initial multi-stage control list.
The functional feature configuration file can be expanded, configured and reused by locally updating the functional feature configuration file.
As an embodiment, when the functional feature needs to be deleted, the step S4 further includes:
a1, acquiring a to-be-closed function feature identifier, and if the to-be-closed function feature identifier is { F } 1 ,F 2 ,…,F n ,…,F N Elements in } based on F to be closed n Executing step A2, if the feature to be turned off is { F } 1 n ,F 2 n ,…,F x n ,…,F g(n) n Elements in } based on F to be closed x n Step A3 is performed.
Step SA2, when F is to be closed n M corresponding to each sub-functional feature of (C) k F to be closed in the corresponding functional characteristic configuration file n The first type variable parameter information corresponding to each sub-functional feature is set as the second identifier.
It will be appreciated that when a F needs to be deleted n When F is needed n All corresponding sub-functions are deleted.
Step SA3, to-be-closed F x n Corresponding F n Is set as to-be-processed F n To be closed F x n Corresponding M k Corresponding offspring node composition module and F to be processed n The composition module of the offspring node corresponding to the child function characteristics of the server is determined as the offspring node to be processed; at the position to be closed F x n Corresponding M k F to be closed in the corresponding functional characteristic configuration file x n Setting the corresponding first type variable parameter information as a second identifier; in the functional characteristic configuration file corresponding to the component modules of the offspring node to be processed, F to be processed n The first type of variable parameter information of the sub-functional feature of (a) is set to the second identification.
It can be understood that when a certain sub-functional feature needs to be deleted, the sub-functional feature and the constituent module of the descendant node corresponding to the sub-functional feature are also provided with F corresponding to the sub-functional feature n The same sub-feature is deleted together. In the tree structure, offspring nodes of a node refer to all child nodes of the node, and all child nodes of the node until leaf nodes, wherein each node corresponds to a composition module.
As can be seen from the step A1-the step A3, the deletion of the functional features or the sub-functional features can be flexibly controlled by controlling the identification of the first type of the third information.
As an embodiment, when the new functional feature is needed, the step S4 further includes:
step B1, obtaining the functional characteristic F to be added r ，r>N。
Step B2, F r Splitting into g (r) sub-functional features { F 1 r ,F 2 r ,…,F z r ,…,F g(r) r }，F z r Is F r The z-th sub-feature of (2), the value of z ranges from 1 to g (r), and g (r) is F r The total number of sub-functional features of the system, g (r) is more than or equal to 1.
Step B3, establishing F 1 r And M is as follows 1 Corresponding relation of F p r Setting corresponding M i ,F p r Is F r P-th sub-feature of (2) and p ranges from 2 to g (r), M i For the ith chip to form a module, the value of i ranges from 2 to K, each of which is equal to F p r M for setting corresponding relation i The parent module must be identical to one of F z r And establishing a corresponding relation.
Step B4, at each F z r Corresponding M k Adding F to the functional feature configuration file of (1) z r Is provided with sub-function feature identification and parameter information corresponding to the sub-function feature.
Adding a certain functional feature to the chip can be achieved through steps B1-B4.
As an embodiment, in addition to adding functional features corresponding to the chip, sub-functional features may be added to the existing functional features, and the step S4 further includes:
step C1, obtaining the sub-functional feature F to be added g(n)+1 n 。
Step C2, slave { M 1 ,M 2 ,…,M k ,…,M K Select F in } g(n)+1 n Corresponding M i 。
Step C3, at F g(n)+1 n Corresponding M i Adding F to corresponding functional feature configuration files g(n)+1 n Is provided with sub-function feature identification and parameter information corresponding to the sub-function feature.
It should be noted that the step C1 to the step C3 can realize the step of adding F to the existing F n When the newly added sub-functional features are needed, the steps C1-C3 can be respectively implemented for the newly added sub-functional features.
As an embodiment, when the sub-functional feature needs to be adjusted, the step S4 further includes:
step D1, obtaining the sub-functional characteristic F to be adjusted x n The corresponding target adjustment parameters.
Step D2, adjusting the sub-function characteristic F x n M corresponding to i In the corresponding functional feature configuration file, the corresponding adjustable parameter in the second type of variable parameter information is updated to be the target adjustment parameter.
It should be noted that, the values or ranges of the adjustable parameters of the sub-functional features to be adjusted can be adjusted through the steps D1-D2.
F can be updated by locally updating the functional feature configuration file n Corresponding sub-feature based on all F after updating n And corresponding to the sub-functional features, executing the step S10-and the step S40, and generating updated chip functional coverage rate verification codes.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
The embodiment of the invention splits each chip functional characteristic into a plurality of sub-functional characteristics, and respectively sets the sub-functional characteristics in corresponding chip composition modules to construct a whole chip and each M k Corresponding multi-level control table based on the whole chip and each M k Corresponding multistage control standard flexibly controls configuration information of chip function coverage rate verification based on the whole chip and each M k The corresponding multi-stage control table generates a chip function coverage rate verification code.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (9)
1. The multi-stage control method based on the chip function coverage rate is characterized by comprising the following steps of:
step S1, obtaining a chip function feature list { F } 1 ,F 2 ,…,F n ,…,F N Sum chip composition module list { M } 1 ,M 2 ,…,M k ,…,M K }, wherein F n The value range of N is 1 to N, N is the total number of the functional characteristics of the chip, M k For the kth chipsetForming modules, wherein the value range of K is 1 to K, K is the total number of the chip forming modules, all the chip forming modules are arranged in a hierarchical manner to form a tree structure, M 1 Is a top layer module;
step S2, each F is processed n Splitting the module into a plurality of sub-functional features, and dispersing the plurality of sub-functional features of each chip functional feature into a plurality of chip component modules, wherein one of the sub-functional features is arranged in a top layer module, and if other component modules other than the top layer module are provided with one of the sub-functional features, a father module of the component module is necessarily provided with one of the sub-functional features;
step S3, based on all F n Sub-feature of (a) respectively constructs the whole chip and each M k The control system comprises a corresponding multi-stage control table, a control module and a control module, wherein the multi-stage control table comprises first-stage control information, second-stage control information and third-stage control information, the control level of the first-stage control information is sequentially reduced, the first-stage control information is used for controlling a switch for verifying the coverage rate of the whole chip function, the second-stage control information is used for respectively controlling a switch for verifying the coverage rate corresponding to each chip function feature or sub-function feature, and the third-stage control information is used for controlling a coverage rate verification feature corresponding to each function feature or sub-function feature;
step S4, based on the whole chip and each M k The corresponding multi-stage control table generates a chip function coverage rate verification code.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the first-level control information comprises a chip function coverage rate switch identifier, and when the chip function coverage rate switch identifier is set as an openable identifier, the first-level control information indicates that a chip function coverage rate verification code needs to be generated;
when the chip function coverage rate switch identifier is set to be a closing identifier, the fact that the chip function coverage rate verification code is not required to be generated is indicated, and the second-level control information and the third-level control information are all set to be in a closing state.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the second-level control information comprises a characteristic control list, and the second-level control information of the multi-level control list corresponding to the whole chip comprises all F n Each F n Corresponding switch identification, M k The second level control information of the corresponding multi-level control table comprises M k All corresponding sub-function identifiers and switch identifiers corresponding to each sub-function feature;
when F n Corresponding switch identification or M k F when the switch mark corresponding to the corresponding sub-functional feature is set as the closing mark n Corresponding switch identification or M k The third-level control information corresponding to the corresponding sub-functional feature is all set to the off state.
4. The method of claim 3, wherein the step of,
the coverage verification feature is a functional coverage verification feature or an assertion verification feature.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
if the coverage verification feature is a functional coverage verification feature, the third level control information is divided into 3.1 level control information, 3.2 level control information and 3.3 level control information, the control level of which is sequentially reduced, wherein,
the level 3.1 control information includes each F n Or a coverage group corresponding to the sub-functional feature, and a coverage group switch identifier;
the 3.2-level control information comprises a coverage point corresponding to each coverage group and a coverage point switch identifier;
the 3.3-level control information comprises a bin corresponding to each coverage point and a switch identification of the bin;
when the switch of the coverage group is in a closed state, the coverage group is at a coverage point corresponding to the 3.2-level control information, and all bins corresponding to all coverage points of the coverage group in the 3.3-level control information are all set to be in the closed state;
when the coverage point switch is in the off state, all bins corresponding to the coverage point in the 3.3 level control information are all set to the off state.
6. The method of claim 5, wherein the step of determining the position of the probe is performed,
the third-level control information further comprises 3.4-level control information, the 3.4-level control information comprises a cross coverage point and a cross coverage point switch mark, the cross coverage point is a cross item formed by two coverage points in the 3.2-level control information, and when any one coverage point of the cross coverage points is set to be in a closed state in the 3.2-level control information, the corresponding cross coverage point is also set to be in the closed state.
7. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S3 includes:
step S10, the first generated whole chip and each M k The corresponding multi-level control list is used as an initial multi-level control list;
step S20, acquiring the update configuration information of the chip functional coverage rate, wherein the update configuration information of the chip functional coverage rate comprises the functional characteristic identifiers required to be updated and the coverage rate configuration information corresponding to the functional characteristic identifiers required to be updated;
step S30, updating the initial multi-stage control list based on the functional characteristic identifiers to be updated and coverage rate configuration information corresponding to the functional characteristic identifiers to be updated;
and S40, generating updated chip function coverage rate verification codes based on the updated initial multi-stage control list.
8. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-7.
9. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-7.
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