CN113792520A - Layout wiring method, layout wiring device, synchronous circuit and integrated circuit chip - Google Patents
Layout wiring method, layout wiring device, synchronous circuit and integrated circuit chip Download PDFInfo
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Abstract
The method distributes a clock gating unit and a corresponding second register to a preset area of a layout by physical constraints configured on the clock gating unit and the corresponding second register in advance in a layout stage; and then, performing clock tree comprehensive processing on the first register, the clock gating unit and the second register to enable a time sequence path of the first register and a clock path of the clock gating unit to be respectively inserted into a multi-stage buffer so as to compensate the difference of the lengths of the clock paths of the clock gating unit and the first register. Therefore, the time sequence from the first register to the clock gating unit in the synchronous circuit can be effectively improved, and the time sequence convergence is facilitated.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for layout and routing, a synchronization circuit, and an integrated circuit chip.
Background
With the development of very large scale Integrated circuits, a Clock Gating unit (Integrated Clock Gating) is usually added in a synchronous circuit in a low power consumption design of a digital circuit to dynamically turn off a Clock path of a post-stage register, so as to reduce power consumption. However, as the operating frequency and complexity of the circuit are increased, the timing convergence of the synchronous circuit is more difficult, and particularly, the Clock from the previous register to the Clock gating unit has a larger Clock delay Skew (Clock Skew), so that the timing convergence of the previous register and the Clock gating unit is difficult.
Disclosure of Invention
The embodiment of the application provides a layout and wiring method, a layout and wiring device, a synchronous circuit and an integrated circuit chip, which can effectively solve the technical problem of difficult time sequence convergence between a preceding stage register and a clock gating unit.
In a first aspect, an embodiment of the present application provides a method for laying out and routing a chip, where the chip includes a synchronization circuit, and the synchronization circuit includes: the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end. The method comprises the following steps:
distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
and performing clock tree comprehensive processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a timing path of the first register and a clock path of the clock gating unit to compensate for the difference of the lengths of the clock paths of the clock gating unit and the first register.
Further, the physical constraints are configured according to the following steps:
determining the number of second registers connected with the clock gating unit and the layout area of a single second register;
determining dimensions of the physical constraints based on the number and the layout area;
configuring physical constraints on the clock gating cells and the respective second registers based on the determined dimensions.
Further, the determining dimensions of the physical constraint based on the number and the layout area includes:
obtaining a reference layout area according to the number and the layout area;
and multiplying the reference layout area by a preset coefficient to obtain the area of the preset region, and distributing the dimensionality of the physical constraint based on the area of the preset region, wherein the preset coefficient is greater than 1 and less than or equal to 2.
Further, the preset area is a square area.
In a second aspect, an embodiment of the present application further provides a device for laying out and routing a chip, where the chip includes a synchronization circuit. The synchronization circuit includes: the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end. The device comprises:
the constraint module is used for distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
and the clock tree synthesis module is used for performing clock tree synthesis processing on the first register, the clock gating unit and the second register so that a multi-level buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the length difference of the clock paths of the clock gating unit and the first register.
In a third aspect, an embodiment of the present application further provides a synchronization circuit, including:
a first register having a clock terminal connected to a source clock terminal of the synchronization circuit,
the clock gating unit is connected with the source clock end through a clock end, and the enabling end is connected with the output end of the first register;
a second register having a clock terminal connected to the output terminal of the clock gating unit and integrated with the clock gating unit in a predetermined region of the IC chip, an
And the multi-stage buffers are respectively inserted into the clock path of the first register and the clock path of the clock gating unit and are used for compensating the difference of the lengths of the clock paths of the clock gating unit and the first register.
Further, the area of the preset region is a preset multiple of a reference layout area, wherein the reference layout area is an area required by layout of all second registers connected to the clock gating unit, and the preset multiple is greater than 1 and less than or equal to 2.
Further, the number of the second registers to which the clock gating unit is connected is greater than or equal to 1 and less than or equal to 100.
Further, the preset area is a square area.
In a fourth aspect, an embodiment of the present application further provides an integrated circuit chip, including the synchronization circuit described in the third aspect.
In the chip layout and wiring method provided by the embodiment of the application, the physical constraints are set on the clock gating unit and the second register at the later stage in the layout stage, so that the physical distance between the clock gating unit and the second register at the later stage is reduced, the insertion position of the buffer during the execution of the clock tree synthesis step is changed, and the buffer which is originally inserted between the clock gating unit and the second register due to the overlong wiring of the clock gating unit and the second register is inserted into the clock path of the clock gating unit. Therefore, the clock path lengths of the clock gating unit and the first register are close to each other while the clock arrival time of the first register and the clock arrival time of the second register are kept consistent, and the clock delay deviation between the clock gating unit and the clock of the first register is reduced, so that the time sequence from the first register to the clock gating unit is effectively improved, and the time sequence convergence is facilitated.
The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a schematic diagram of an exemplary synchronization circuit;
FIG. 2 shows a schematic diagram of another exemplary synchronization circuit;
FIG. 3 is a flow chart illustrating a method for placing and routing provided by an embodiment of the present specification;
FIG. 4 illustrates a schematic diagram of a synchronization circuit provided by embodiments of the present description;
FIG. 5 is a block diagram illustrating a placement and routing apparatus provided by an embodiment of the present specification;
fig. 6 is a schematic diagram illustrating a structure of an integrated circuit chip provided in an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In an Integrated Circuit (IC) chip, a synchronous Circuit, i.e., a synchronous sequential logic Circuit, is mostly required. In order to realize a low power consumption design, a clock gating unit GCLK is usually inserted in the synchronous circuit, as shown in fig. 1, so as to turn off its clock when the post-stage registers DFF1, DFF2, and DFF3 are in an idle state, thereby reducing power consumption. However, this also causes a large clock delay deviation between the clock of the previous stage register DFF0 and the clock gating cell GCLK in the synchronous circuit, which causes a timing problem, especially a problem of establishing a timing, such that it is difficult to converge the timing between the previous stage register DFF0 and the clock gating cell GCLK.
In view of the above problems, the inventors have conducted long-term studies and found that in the layout and routing stage of the synchronous circuit, the physical distance between the clock gating cell and its subsequent register is usually relatively far after layout. After Clock tree synthesis, because the register and the subsequent register usually belong to the same Clock domain, an Electronic Design tool such as EDA (Electronic Design Automation) uses the Clock ends of the previous register and the subsequent register as a sink to perform Clock delay Balance (Clock delay Balance) processing. Because the output end of the clock gating unit is physically far away from the clock input end of the next register, a multi-stage Buffer (Buffer) is inserted between the output end of the clock gating unit and the clock input end of the next register in order to avoid the problem of long lines, and the like, as shown in fig. 1, so that the clock stability is ensured, and the clock arrival times of the front register DFF0 and the next register DFF1, DFF2 and DFF3 are balanced. However, this results in a relatively long clock path between the front register DFF0 and the rear registers DFF1, DFF2 and DFF3 and a relatively short clock path between the clock gating cell GCLK and the front register DFF0, which causes a large clock delay deviation from the clock of the clock gating cell GCLK, making it difficult to converge the timing of the front register DFF0 to the clock gating cell GCLK.
In this regard, the inventors have considered optimizing the timing of the preceding register DFF0 to the clock gating cell GCLK by placing timing constraints on the paths of the preceding register DFF0 and the clock gating cell GCLK, such as adding additional timing margins or intentionally adding negative delays to the clock of the clock gating cell GCLK during the layout phase. However, these are all data path optimization perspectives, and the ability to actually optimize timing is limited.
In addition, the inventors have considered delaying the clock of the clock gating cell GCLK after the clock tree synthesis to reduce the clock skew. However, it is found that, after the clock tree is synthesized, the clock of the clock gating unit GCLK is delayed, as shown in fig. 2, a buffer is inserted into the clock path of the clock gating unit GCLK to push the clock backward, so that although the clock delay deviation between the clocks of the front register DFF0 and the clock gating unit GCLK can be reduced, and the timing problem of the front register DFF0 to the clock gating unit GCLK is optimized, the clocks of the rear registers DFF1, DFF2 and DFF3 are equal to the clock of the front register DFF0, and the clock path of the clock gating unit GCLK is inserted with a buffer, so that the clock delay of the rear registers DFF1, DFF2 and DFF3 is increased, and one clock gating unit GCLK usually connects a plurality of rear registers, which causes many timing problems of the rear registers.
In view of this, the inventor proposes a technical solution provided in the embodiments of the present disclosure, and sets physical constraints on the clock gating unit and the subsequent register in the layout stage, so as to reduce the physical distance between the clock gating unit and the subsequent register, thereby being able to change the insertion position of the buffer when performing the clock tree synthesis step, and insert the buffer, which would be inserted between the clock gating unit and the subsequent register due to the overlong wiring of the clock gating unit and the subsequent register, into the clock path of the clock gating unit. Therefore, the clock arrival time of the front-stage register and the clock arrival time of the rear-stage register are kept consistent, the clock path lengths of the clock gating unit and the front-stage register are close, and the clock delay deviation between the clock gating unit and the clock of the front-stage register is reduced, so that the time sequence from the front-stage register to the clock gating unit is improved, and the time sequence convergence is realized.
The following describes in detail specific implementations provided by the embodiments of the present disclosure.
The chip layout and wiring method provided by the embodiment of the specification is applied to the physical realization of a synchronous circuit contained in a chip in the back end design of an integrated circuit. Specifically, the synchronization circuit includes: the clock gating unit comprises a first register, a clock gating unit and a second register. The output end of the first register is connected with the clock end of the corresponding second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end. The first register is a preceding stage register of the clock gating unit and is used for outputting an enabling signal of the clock gating unit; the second register is a post-stage register of the clock gating unit and is used for storing data or controlling a next-stage circuit; the clock gating unit is used for controlling the clock input of the corresponding second register, and can close the clock of the second register when the second register is in an idle state so as to reduce redundant logic inversion of the second register along with clock inversion and reduce power consumption. It should be noted that, in this embodiment, the number of the clock gating units, the first registers, and the second registers included in the synchronization circuit is not limited, and each clock gating unit and the corresponding first register and second register in the synchronization circuit may be physically implemented according to the layout and routing method shown in fig. 3.
Fig. 3 shows a flowchart of a method for placing and routing according to an embodiment of the present disclosure. As shown in fig. 3, the method includes:
step S301, based on the physical constraints configured on the clock gating unit and the corresponding second register in advance, the clock gating unit and the corresponding second register are distributed to a preset area of the layout.
It is understood that in the back-end design of an integrated circuit, the implementation of the circuit physical design is often referred to as place-and-route (P & R), which includes a preparation phase, a placement phase, a clock tree synthesis phase, and a routing phase, in turn, and the gate-level netlist provided by the front-end is physically implemented into a layout (layout). The layout stage is to assign physical locations to the devices on the layout.
By configuring physical constraints (Bound) on the clock gating unit and the controlled second register in advance, in a layout stage, when the layout step is executed, the clock gating unit and the controlled second register are placed in a preset area with a specified area and a specified shape based on the physical constraints, so that the clock gating unit and the controlled second register are close to each other, and the condition that a buffer needs to be inserted between the clock gating unit and the controlled second register due to an overlong connecting line in a subsequent clock tree synthesis stage to ensure clock stability is avoided.
The preset region is the region corresponding to the configured physical constraint. For example, when configuring physical constraints, the constraint region can be set as a square region with dimensions { a, b }, and then the clock gating unit and the controlled second register are placed in the square region with width a and height b when layout is performed.
As shown in fig. 4, it is assumed that the synchronization circuit includes: first registers 100a, 100b, and 100 c; combinational logic circuits 140a, 140b, and 140 c; clock gating cells 110a, 110b, and 110 c; second registers 121a, 122a, and 123a controlled by the clock gating cell 110 a; second registers 121b, 122b and 123b controlled by the clock gating cell 110b and second registers 121c, 122c and 123c controlled by the clock gating cell 110 c. Then in the layout phase, the clock gating cell 110a and the second registers 121a, 122a and 123a are laid out in the constrained square area a, the clock gating cell 110B and the second registers 121B, 122B and 123B are laid out in the constrained square area B, and the clock gating cell 110C and the second registers 121C, 122C and 123C are laid out in the constrained square area C. The dashed-line frame area in fig. 4 indicates a preset area.
It should be noted that, the 3 clock gating units listed in fig. 4 and each clock gating unit has 3 subsequent registers, which are only used as examples and are not limited, and the specific number of the clock gating units and the subsequent registers in the synchronous circuit needs to be determined according to the actual application scenario. In addition, the preset region may be a region having another shape than the square region, and is not limited herein.
In a specific implementation process, the size of the preset region is determined by the dimension of the physical constraint, and may be determined according to the number of the second registers corresponding to the clock gating unit and the layout area of each second register, and it is necessary to avoid that the buffer needs to be inserted due to an excessively long distance between the clock gating unit and the controlled second register while the clock gating unit and the corresponding second register can be sufficiently placed. The dimensionality of physical restraint is reasonably set, the density of local units can be effectively controlled, and the problem of difficult subsequent winding is avoided.
In an alternative embodiment, the process of configuring the physical constraints may include: firstly, determining the number of second registers connected with a clock gating unit and the layout area of a single second register; then, determining the dimensionality of the physical constraint needing to be configured based on the determined number and the layout area; physical constraints may then be configured for the clock gating cell and the corresponding second register based on the determined dimensions.
In an alternative embodiment, the determining the dimension of the physical constraint based on the determined number and the layout area may include: obtaining a reference layout area according to the determined quantity and the layout area; and multiplying the reference layout area by a preset coefficient to obtain the area of the preset region, and distributing the dimensionality of the physical constraint based on the area of the preset region. The preset coefficients and the specific dimension distribution rules can be predetermined according to the layout rules and the multiple tests of the integrated circuit.
It can be understood that the area of the predetermined area needs to be large enough but not too large, and therefore, a certain degree of expansion needs to be performed on the basis of the layout area required by all the second registers corresponding to the clock gating cell, so as to serve as the layout space and the routing space of the clock gating cell. For example, the preset coefficient may take a value greater than 1 and less than or equal to 2, such as 1.5 or 2. When the preset coefficient is 2, the area of the preset region is twice of the layout area required by all the second registers corresponding to the clock gating unit.
For example, if the layout area required by a single second register is 1 square micron, and a clock gate unit has 32 second registers, the 32 second registers need to be laid down at least 32 square microns; further, when the preset coefficient is 2, the obtained reference area is 64 square micrometers, and at this time, the dimension of the corresponding physical constraint may be set to {8, 8}, and the unit is micrometer.
Alternatively, in other embodiments of the present description, the dimensions of the physical constraints may be determined in other ways. For example, the chip process, the number of the second registers, and the mapping relationship between the layout area of a single second register and the dimension of the physical constraint may be obtained in advance according to a plurality of tests; in specific implementation, according to the mapping relationship, the corresponding physical constraint dimension is determined according to the actually adopted chip process, the number of second registers controlled by the clock gating unit and the layout area of a single second register.
In addition, it should be noted that, in consideration of the fact that the number of registers in the synchronous circuit is usually large, in order to avoid that the subsequent wiring is affected due to too high local unit density caused by setting physical constraints on the clock gating units and the subsequent registers, in the synchronous circuit designed according to the layout and wiring method provided in the embodiments of the present specification, the number of the subsequent registers of each clock gating unit cannot be too large. For example, the number of second registers connected to each clock gating cell may be greater than or equal to 1 and less than or equal to 100, for example, 32, 64, or 100, etc.
After the layout phase is completed, step S302 may be executed to perform clock tree synthesis, so as to achieve clock delay balance.
Step S302, perform clock tree synthesis on the first register, the clock gating unit, and the second register, so that a multi-stage buffer is inserted into the timing path of the first register and the clock path of the clock gating unit, respectively, to compensate for the difference in clock path length between the clock gating unit and the first register.
The first register and the second register belong to the same clock domain, and the clocks of the first register and the second register need to be processed in equal length. Because the physical distance between the clock gating unit and the second register is short, the clock path is short, the time delay caused by the short clock path can be ignored, and the stability of the clock can be ensured. Therefore, when the clock tree is synthesized, the clock gating unit and the second register are considered as a whole, so that a multi-stage buffer is inserted between the first register and the source clock end and between the clock gating unit and the source clock end instead of inserting a buffer between the clock gating unit and the second register, and the clock tree is constructed so that the clock gating unit and the first register have similar clock path lengths. As shown in fig. 4, after clock tree synthesis, a multi-stage buffer 130 is inserted in the clock paths of the first registers 100a, 100b, and 100c and the clock gating units 110a, 110b, and 110c, respectively, and no buffer is inserted between the clock gating units 110a, 110b, and 110c and the controlled second register.
Therefore, the clock delay balance of the first register and the second register can be realized, the clock delay deviation between the clock gating unit and the first register can be reduced, the time sequence from the first register to the clock gating unit is optimized, and the time sequence convergence of the synchronous circuit is facilitated.
In addition, because the clock gating unit is usually used for controlling a plurality of second registers arranged in parallel, compared with the method that a buffer is inserted between the clock gating unit and each second register to realize clock delay balance of the first register and the second register, the use number of the buffers can be reduced by inserting the buffers on the clock path of the clock gating unit, so that the utilization rate of an IC chip is improved, and the manufacturing cost is effectively reduced.
It should be noted that the whole layout and routing flow of the synchronous circuit includes other steps besides the above steps S301 and S302, such as a preparation step and a routing step, and specific reference may be made to implementation details related to the layout and routing, which is not described in detail in this embodiment.
In order to verify the time sequence improvement effect of the technical scheme provided by the embodiment of the specification, under the condition that other experimental conditions are the same, time sequence simulation experiments are respectively carried out on the synchronous circuit layouts obtained by setting physical constraints and not setting the physical constraints, so that the influence of the setting of the physical constraints on the time sequence from the first register to the clock gating unit is verified by comparing the experimental results. The timing results of the first register to the clock gating cell measured by the comparative experiment are shown in table 1. It can be seen from table 1 that wns (last Negative slack), i.e., the worst slack value, of the timing is reduced from-0.76 ns to-0.24 ns after the physical constraint is set, and the number of timing violations (synchronization number) is reduced from 980 to 370, and the timing is significantly improved, compared to the case where the physical constraint is not set.
TABLE 1
| WNS(ns) | Violation number | |
| Bound is not set | -0.76 | 980 |
| Setting Bound | -0.24 | 370 |
In summary, in the layout and routing method provided in the embodiments of the present disclosure, physical constraints are set on the clock gating unit and the second register at the subsequent stage in the layout stage, and the buffer that would be inserted between the clock gating unit and the second register due to too long routing of the clock gating unit and the second register is inserted into the clock path of the clock gating unit, so that clock delay deviation between clocks of the clock gating unit and the preceding register is reduced, which is beneficial to improving the timing sequence from the preceding register to the clock gating unit, so as to implement timing convergence, and at the same time, the number of buffers is also reduced, thereby improving the utilization rate of the IC chip and effectively reducing the manufacturing cost.
Based on the same inventive concept, the embodiment of the present specification further provides a layout and wiring device of a chip, which is applied to physical implementation of the above-mentioned synchronous circuit included in the chip. As shown in fig. 5, the placement and routing apparatus 50 includes:
a constraint module 501, configured to allocate the clock gating unit and the corresponding second register to a preset region of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
a clock tree synthesis module 502, configured to perform clock tree synthesis on the first register, the clock gating unit, and the second register, so that a multi-level buffer is respectively inserted into a timing path of the first register and a clock path of the clock gating unit to compensate for a difference in clock path lengths between the clock gating unit and the first register.
In an alternative embodiment, the above-mentioned wire laying and routing device 50 further includes: a constraint configuration module comprising:
the parameter determination submodule is used for determining the number of second registers connected with the clock gating unit and the layout area of a single second register;
a dimension determination submodule for determining a dimension of the physical constraint based on the number and the layout area;
a configuration submodule to configure physical constraints on the clock gating cell and the corresponding second register based on the determined dimensions.
In an optional embodiment, the dimension determination sub-module is configured to:
obtaining a reference layout area according to the number and the layout area;
and multiplying the reference layout area by a preset coefficient to obtain the area of the preset region, and distributing the dimensionality of the physical constraint based on the area of the preset region, wherein the preset coefficient is greater than 1 and less than or equal to 2.
In an alternative embodiment, the predetermined area is a square area.
It should be noted that, the layout and routing apparatus 50 provided in the embodiment of the present specification, the specific manner in which each module performs the operation has been described in detail in the above method embodiment, and will not be described in detail here.
Based on the same inventive concept, the embodiment of the present specification further provides a synchronous circuit obtained by the method for laying out and routing provided by the above method embodiment. As shown in fig. 4, the synchronization circuit includes: first registers (e.g., 100a, 100b, and 100c shown in fig. 4), clock gating units (e.g., 110a, 110b, and 110c shown in fig. 4), second registers (e.g., 121a, 122a, 123a, 121b, 122b, 123b, 121c, 122c, and 123c shown in fig. 4), and a multi-stage buffer 130 inserted in a clock path of the first registers and a clock path of the clock gating units, respectively.
The clock terminal of the first register is connected to the source clock terminal CLK0 of the synchronization circuit. The source clock terminal CLK0 may be a clock output terminal of a clock generation circuit inside the IC chip, or a clock may be provided outside the IC chip, and in this case, the source clock terminal CLK0 may also be a clock input terminal of the IC chip.
The clock gating cell has a clock terminal connected to the source clock terminal CLK0 and an enable terminal connected to the output terminal of the first register. The enable signal is output by the first register, enabling the clock gating cell to gate off the clock signal transmitted to the second register.
The output end of the clock gating unit is connected with the clock end of the controlled second register so as to control the clock input of the second register. The clock gating unit and the connected second register are integrated in the preset area of the IC chip together, so that the physical distance between the clock gating unit and the second register is close enough, and the stability of clock transmission is ensured. In a specific implementation, the area of the preset region may be a preset multiple of a reference layout area, where the reference layout area is an area required by all second registers connected to the layout clock gating unit, and the preset multiple is greater than 1 and less than or equal to 2. Reference may be made in particular to the description relating to the method embodiments described above.
In an alternative embodiment, to avoid excessive local unit density, the number of second registers connected to each clock gating unit may be greater than or equal to 1 and less than or equal to 100, for example, 32, 64, or 100, etc.
The multi-level buffers inserted into the clock paths of the first register and the clock gating unit form a clock tree, and the length difference of the clock paths between the clock gating unit and the first register can be effectively compensated while the clock arrival time of the first register and the clock arrival time of the second register are consistent, so that the clock delay deviation between the clock gating unit and the first register is reduced, and the time sequence convergence from the first register to the clock gating unit is facilitated.
It should be noted that the synchronization circuit provided in this embodiment of the present disclosure may further include other circuit structures besides the first register, the clock gating unit, the second register, and the buffer, which are specifically designed according to the needs of the actual application scenario, and this embodiment is not limited thereto. For example, as shown in fig. 4, the synchronization circuit may further include a combinational logic circuit (e.g., 140a, 140b, and 140c shown in fig. 4), and the output terminal of the first register is connected to the enable terminal of the clock gating cell through the combinational logic circuit. The specific circuit structure of the combinational logic circuit can be set according to the needs of the practical application scenario, for example, the combinational logic circuit can be an adder, the enable signal output by the first register and another control signal are added to obtain the final enable signal and output to the enable end of the clock gating unit,
based on the same inventive concept, the present specification further provides an IC chip, as shown in fig. 6, where the IC chip 60 includes the synchronization circuit 601. It should be noted that the IC chip 60 may be any chip including the synchronization circuit 601, such as a memory chip, and the present embodiment is not limited thereto.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The term "plurality" means more than two, including two or more.
While preferred embodiments of the present specification have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all changes and modifications that fall within the scope of the specification.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present specification without departing from the spirit and scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalents, the specification is intended to include such modifications and variations.
Claims (10)
1. A method for laying out and routing a chip, wherein the chip comprises a synchronization circuit, and the synchronization circuit comprises: the method comprises the following steps that an output end of the first register is connected with a clock end of the corresponding second register through the clock gating unit, and clock ends of the first register and the clock gating unit are connected with the same source clock end, and the method comprises the following steps:
distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
and performing clock tree comprehensive processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a timing path of the first register and a clock path of the clock gating unit to compensate for the difference of the lengths of the clock paths of the clock gating unit and the first register.
2. The place and route method of claim 1, wherein the physical constraints are configured in accordance with the steps of:
determining the number of second registers connected with the clock gating unit and the layout area of a single second register;
determining dimensions of the physical constraints based on the number and the layout area;
configuring physical constraints on the clock gating cells and the respective second registers based on the determined dimensions.
3. The method of claim 2, wherein determining the dimensions of the physical constraints based on the number and the layout area comprises:
obtaining a reference layout area according to the number and the layout area;
and multiplying the reference layout area by a preset coefficient to obtain the area of the preset region, and distributing the dimensionality of the physical constraint based on the area of the preset region, wherein the preset coefficient is greater than 1 and less than or equal to 2.
4. The method according to claim 1, wherein the predetermined area is a square area.
5. A device for laying out and routing a chip, wherein the chip comprises a synchronization circuit, the synchronization circuit comprising: the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end, the device comprises:
the constraint module is used for distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
and the clock tree synthesis module is used for performing clock tree synthesis processing on the first register, the clock gating unit and the second register so that a multi-level buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the length difference of the clock paths of the clock gating unit and the first register.
6. A synchronization circuit, comprising:
a first register having a clock terminal connected to a source clock terminal of the synchronization circuit,
the clock gating unit is connected with the source clock end through a clock end, and the enabling end is connected with the output end of the first register;
a second register having a clock terminal connected to the output terminal of the clock gating unit and integrated with the clock gating unit in a predetermined region of the IC chip, an
And the multi-stage buffers are respectively inserted into the clock path of the first register and the clock path of the clock gating unit and are used for compensating the difference of the lengths of the clock paths of the clock gating unit and the first register.
7. The synchronous circuit of claim 6, wherein the area of the predetermined region is a predetermined multiple of a reference layout area, wherein the reference layout area is an area required for layout of all second registers to which the clock gating cell is connected, and the predetermined multiple is greater than 1 and less than or equal to 2.
8. The synchronization circuit of claim 6, wherein the number of second registers to which the clock gating cell is connected is greater than or equal to 1 and less than or equal to 100.
9. The synchronization circuit of claim 6, wherein the predetermined area is a square area.
10. An integrated circuit chip comprising the synchronization circuit of any of claims 6-9.
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