CN103019303A - Adjusting device and method of retention time on time sequence path - Google Patents
Adjusting device and method of retention time on time sequence path Download PDFInfo
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- CN103019303A CN103019303A CN2012105731930A CN201210573193A CN103019303A CN 103019303 A CN103019303 A CN 103019303A CN 2012105731930 A CN2012105731930 A CN 2012105731930A CN 201210573193 A CN201210573193 A CN 201210573193A CN 103019303 A CN103019303 A CN 103019303A
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Abstract
The invention relates to an adjusting device and method for the retention time on a time sequence path. The time sequence path is the same time sequence path among different chips in a system on a chip. The adjusting device of the retention time comprises a retention time delay device and retention time verifying devices, wherein the retention time delay device is arranged on one of the chips and selectively adds different time delays on a data path in the time sequence path; and the retention time verifying devices are arranged on other chips in all the chips, and the retention time verifying devices are used for verifying whether the retention time of the time sequence path meets a correct time sequence demand by using out-of-order logic. The retention time delay device adjusts the time delay till the correct time sequence demand is met on the basis of verifying results of the retention time verifying devices. The adjusting device and method disclosed by the invention have the advantages of high cost performance, stability in data transmission and the like.
Description
Technical field
The invention relates to regulating device and the method for retention time on the timing path, particularly regulating device and the method for retention time on the same timing path of different chip chambers.
Background technology
Because mimic channel can not dwindling and scaled down along with the integrated circuit fabrication process size; so when integrated circuit fabrication process is more and more advanced, more and more do not optimize on the contrary with the cost that same process mixes SOC (system on a chip) in same chips realization digital-to-analogue.
For addressing this problem, a kind of method is based on chip-stacked technology the digital logic unit in the SOC (system on a chip) and mimic channel is separated, wherein area can dwindle and the digital logic unit of scaled down is implemented on the advanced small size processing chip along with process, area can not dwindle and the mimic channel of scaled down is implemented on the complete and cheap large scale processing chip of depreciation along with process, then makes this two chips of pin interconnection stacked on top of the microcontroller standard system bus.
For making two chips on the different layers can carry out normal data communication, need to guarantee on the different layers on the same timing path of chip chamber that the retention time is accurate, this also is a major issue that hinders at present chip-stacked technical development.
Summary of the invention
One object of the present invention is to provide adjusting gear and the method for retention time on the timing path of SOC (system on a chip), and it can make retention time on the same timing path of different chip chambers satisfy the requirement of correct sequential.
The invention provides the adjusting gear of retention time on a kind of timing path, this timing path is the same timing path of different chip chambers in the SOC (system on a chip).The adjusting gear of retention time comprises and is arranged at the retention time time-delay mechanism on the one in these chips, and this retention time time-delay mechanism is selected to adding different time-delays on the data routing in the timing path; And being arranged at the retention time calibration equipment on other person in these chips, this retention time calibration equipment uses the retention time of out of order logic verify timing path whether to satisfy correct sequential needs.The retention time time-delay mechanism is delayed time until satisfy correct sequential needs based on the check results adjustment of retention time calibration equipment.
Among the present invention, the host microcontroller kernel of retention time time-delay mechanism and SOC (system on a chip) is arranged on the same chip.The retention time time-delay mechanism comprises a MUX, and this MUX is arranged on the described time series data path, and between the input and output pin and combinational logic of chip.The selecting side of MUX is connected to the output terminal of the retention time delay selection special function register of described SOC (system on a chip), and data input pin 0-n (n 〉=2) connects respectively the delay unit of 1 to n+1 series connection.When check results showed that the retention time is not satisfied correct sequential needs, retention time delay selection special function register was from increasing 1.The maximum delay of retention time is the minimum time-delay that the maximum delay of clock path in the timing path deducts data routing in the timing path.The retention time calibration equipment is arranged on the different chips from the host microcontroller kernel of SOC (system on a chip).The retention time calibration equipment comprises at least two read-write out of order logical consequence special function registers and forms, and at least two out of order logical consequence special function registers share a power-on reset signal; The clock input of each special function register is connected to the output of an out of order logic input clock special function register on the described SOC (system on a chip), and the data input is connected to respectively logical zero or logical one.
The present invention also provides the method for adjustment of retention time on a kind of timing path, and this timing path is the same timing path of different chip chambers in the SOC (system on a chip).The inventive method is contained in to be selected on the one in the chip to adding different time-delays on the data routing in the timing path, and other person is upper in chip uses the retention time of out of order logic verify timing path whether to satisfy correct sequential needs; And adjust time-delay until satisfy correct sequential.
Among the present invention, use a retention time time-delay mechanism to apply described time-delay, described retention time time-delay mechanism comprises a MUX, and this MUX is arranged on the described time series data path, and between the input and output pin and combinational logic of chip.
Among the present invention, the selecting side of described MUX is connected to the output terminal of the retention time delay selection special function register of described SOC (system on a chip), and the data input pin 0-n of described MUX (n 〉=2) connects respectively the delay unit of 1 to n+1 series connection.When described check results showed that the described retention time is not satisfied correct sequential needs, retention time delay selection special function register was from increasing 1.The maximum delay of described retention time is the minimum time-delay that the maximum delay of clock path in the described timing path deducts data routing in the described timing path.
Method of adjustment of the present invention uses a retention time calibration equipment to carry out described verification.Described retention time calibration equipment comprises at least two read-write out of order logical consequence special function registers and forms, and described at least two out of order logical consequence special function registers share a power-on reset signal; The clock input of each out of order logical consequence special function register is connected to the output of an out of order logic input clock special function register on the described SOC (system on a chip), and the data input is connected to respectively logical zero or logical one.
Method of adjustment of the present invention further comprises: power on to SOC (system on a chip), described out of order logic input clock special function register overturns; Whether the output valve that detects out of order logical consequence special function register equals the value of its input end.
Compared to prior art, the adjusting gear of retention time of the present invention is adjusted the retention time on the same timing path of different chip chambers until it satisfies the requirement of correct sequential from the method capable of dynamic, thereby guarantees the correctness of data transmission.Corresponding stacking SOC (system on a chip) has high performance-price ratio and stable data transmission.
Description of drawings
Fig. 1 is the structural representation of system on a pile lamination;
Fig. 2 is the structural drawing of the system clock tree when top layer chip and bottom chip are carried out data communication in the stacking SOC (system on a chip) among Fig. 1;
Fig. 3 is data routing and the clock path synoptic diagram that data are transmitted based on the input and output serial clock between layers of chips;
Fig. 4 is the sequential chart that data are transmitted based on the input and output serial clock between top layer and bottom chip;
Fig. 5 uses the data of retention time time-delay mechanism according to an embodiment of the invention based on the data routing of input and output serial clock transmission and the synoptic diagram of clock path;
Fig. 6 is the structural representation of retention time calibration equipment according to an embodiment of the invention;
Fig. 7 is the method for regulating according to an embodiment of the invention the retention time.
Embodiment
For understanding better spirit of the present invention, below in conjunction with part preferred embodiment of the present invention it is described further.
Fig. 1 is the structural representation of system 10 on a pile lamination.As shown in Figure 1, in this stacking SOC (system on a chip) 10, what realize in top layer (top die) chip 12 is high-speed module, for example clock 124, standard system bus 125 on SRAM120, nonvolatile memory 121, digital peripherals 122, CPU or GPU 123, the sheet.And what realize in bottom (bot die) chip 14 is some low-speed module, for example interrupt management 140, power management 141, analog peripheral 142, input and output PAD 143, standard system bus 144.The connection that top layer chip 12 is connected with bottom chip is to interconnect up and down by the input and output pin one 6 of being made by the microcontroller standard system bus.
Fig. 2 is the structural drawing of system clock tree (the clock tree) 20 when top layer chip 12 and bottom chip 14 are carried out data communication in the stacking SOC (system on a chip) 10 among Fig. 1.Module on the top layer chip 12 is faster module of travelling speed ratio mostly, and Embedded microprocessor cores (CPU or GPU) also is arranged on top layer chip 12.So, system clock source 22 is placed on can make things convenient in the top layer chip 12 directly by microcontroller kernel access high-speed module uses.The clock waveform that system clock source 22 produces is transferred to the timing unit 24 that needs clock by Clock Tree 20.Bottom chip 14 all is a little low speed peripheral modules, the clock waveform that system clock source 22 produces, through behind the Clock dividers 26, produce the input and output serial clock, its interface by top layer chip 12 (such as PAD1) 128 passes on the interface (such as PAD2) 148 of bottom chip 14.And these two interfaces are to connect by Bonding (wire bonding) or silicon through hole technology (TSV).The input and output serial clock is the synchronizing clock signals when upper and lower chip chamber carries out data communication, the input and output serial clock of top layer chip 12 is by top layer interface (PAD1) 128 and connecting lead wire, be transferred to bottom chip 14, by the Clock Tree 20 of bottom, be transferred to the timing unit 24 that needs clock signal again.
Fig. 3 is data routing 21 and clock path 23 synoptic diagram that data are transmitted based on input and output serial clock 18 between layers of chips.As shown in Figure 3, data routing 21 is as follows: after input and output serial clock (IO_MUX_clk1) 18 triggers the clock port 128 of a sequential logic 210 in the top layer chip 12, output terminal (Q1) 211 reaches the input and output pin one 6 on the top layer chip 12 after combinational logic 212 time-delays of (t0) through after a while, such as IO_PAD1, the internal delay time of IO_PAD1 is time t2.Then be transferred to input and output pin one 6 on the bottom chip 14 through the lead-in wire of 10 of stacked chips, such as IO_PAD2, the internal delay time of IO_PAD2 is t3, and the time-delay of passing through again afterwards the combinational logic 212 of t1 time reaches the FPDP 213 of bottom sequential logic 212, such as D2.23 of clock paths are as follows: input and output serial clock 18 is the impact damper 231 of t4 through internal delay time, then reach the input and output pin one 6 on the top layer chip 12, such as IO_PAD3, its internal delay time is t6, be connected to input and output pin one 6 on the bottom chip 14 by lead-in wire, on the IO_PAD4, its internal delay time is t7, again through the clock port 233 of time-delay for another impact damper 231 arrival bottom sequential logics 212 of t5, such as clk2.
Fig. 4 is that top layer and bottom chip 12,14 data are based on the sequential charts of input and output serial clock 18 transmission.As shown in Figure 4, as t0+t2+t3+t1＞t4+t6+t7+t5, bottom data port 213, the data on the D2 can not latched at clock edge edge0 by sequential logic 212, and sequential is correct.Yet as t0+t2+t3+t1＜t4+t6+t7+t5, the data of D2 can be collected by sequential logic 212 at clock edge edge0, cause the retention time mistake.Direct result be exactly in the stack SOC (system on a chip) 10 the different layers chip chamber can't carry out normal data communication.
Regulating device and method according to the retention time on the same timing path of different chip chambers of the embodiment of the invention can address the above problem.The regulating device of this retention time and method capable of dynamic are regulated the retention time on the different chip chamber same timing paths, until should the retention time correct, thus normally carrying out of different chip chamber data communication guaranteed.In one embodiment, the regulating device of this retention time comprises and is arranged at the retention time time-delay mechanism on system's one chip on a slice and is arranged at retention time time delay calibration device on other chip that is different from this chip.
Fig. 5 uses the data of retention time time-delay mechanism 30 according to an embodiment of the invention based on the data routing 21 of input and output serial clock 18 transmission and the synoptic diagram of clock path 23.As shown in Figure 5, input and output pin one 6 at top layer chip 12, as a MUX 32 is set before the IO_PAD1, the selecting side of MUX 32 (sel) connects the output of " the retention time delay selection special function register (SFR) " of SOC (system on a chip) 10.The microcontroller kernel of this special function register and SOC (system on a chip) 10 is arranged on the identical chip such as the host microcontroller kernel, such as top layer chip 12.For obtaining the demand of different retention times, MUX 32 can have 0 to n input end, and n 〉=2 need to consider the chip area problem when specifically selecting, and n is larger, and area occupied is larger, but the dynamic adjustments accuracy rate is higher.Each input end connects at least one delay unit 36, and the time-delay between each input end and combinational logic 212 outputs is different to obtain the different retention times.Specifically can be chosen in for " retention time delay selection special function register " with different values by the tax of microcontroller kernel and apply the requirement that the retention time on the different chip chamber same timing paths is satisfied in different time-delays on the data routing 21.For example in the present embodiment, delay unit Del0-1 of first input end 0 front connection, second input end delay unit Del1-1 of 1 front connection and a delay unit Del1-2, Del1-1 connects with Del1-2.By that analogy, connect n+1 delay unit that is cascaded before n+1 input end n, be respectively Deln-1, Deln-2 ... Deln-(n+1).The other end of Del0-1, Del1-1, Del2-1......Deln-1 is linked respectively in the output of top layer combinational logic 212.Namely to each input end, increase successively the quantity of the delay unit 36 of its connection, the delay unit 36 that connects same input end is cascaded; Thereby so that top layer combinational logic 212 to each input end of multichannel selector switch 32 has different time-delays.Wherein at an input and output pin one 6 of top layer, maximum delay such as adding between IO_PAD1 and the top layer combinational logic 212 is Tsssss (t4+t6+t7+t5)-Tfffff (t0+t2+t3+t1), Tsssss is that two chips 12,14 are under the worst condition, and namely t4+t6+t7+t5 reaches maximum; Tfffff is that two chips are under the best-case, and namely t0+t2+t3+t1 reaches minimum.
Fig. 6 is the structural representation of retention time calibration equipment 40 according to an embodiment of the invention.As shown in Figure 6, this retention time time delay calibration device 40 is one to be located at an out of order logic module 40 on the bottom chip 14, and namely this out of order logic module 40 is arranged on the different chips from the host microcontroller kernel of SOC (system on a chip) 10.This out of order logic module 40 comprises an out of order logic input clock 400, is the output of an out of order logic input clock special function register (not shown) on the SOC (system on a chip) 10.Equally, this special function register is located on the different chips from the microcontroller kernel of SOC (system on a chip) 10, is accessed based on chip chamber input and output serial transmission clock 18 by the microcontroller kernel.Out of order logic input clock 400 further connects n input end of clock that shares the out of order logical consequence special function register 402 of a power-on reset signal, and each 402 ones of out of order logical consequence special function register has a fixed value (fixed_value) input end.Default when this fixed value is SOC (system on a chip) 10 design, can be logical zero or " 1 ".Accordingly, each out of order logical consequence special function register 402 can output one out of order logical consequence.
Fig. 7 is the method for regulating according to an embodiment of the invention the retention time.In conjunction with Fig. 6,7, in step 50, after SOC (system on a chip) 10 electrification resets, the out of order logical consequence section of out of order logical consequence special function register 402 outputs is set as entirely " 0 " or entirely " 1 ", or a specific value (reset_value), and guarantee that reset_value is not equal to default fixed value and gets final product.In step 52, the out of order logic input clock special function register 402 that overturns is read out of order logical consequence.For example, when out of order logic input clock 400 receives an efficient clock signal, the output of each out of order logical consequence special function register 402 will be overturn, become respectively fixed_value_n, fixed_value_n-1 ..., fixed_value_2, fixed_value_1, the microcontroller kernel of SOC (system on a chip) 10 can read the value in this out of order logical consequence special function register 402.In step 54, detect the value whether out of order logical consequence equals to expect.If the retention time is regulated correct, out of order logical consequence just can be exported the value identical with the expection fixed value.In step 56, SOC (system on a chip) 10 can satisfy the follow-up data transmission of continuation under the condition of retention time so.Otherwise, when out of order logical consequence can not be exported and the value of expecting that fixed value is identical, the adjusting that then means the retention time is incorrect, cause out of order logic input clock special function register correctly not accessed, or out of order logical consequence special function register 402 can not correctly be accessed.Need to readjust the retention time in step 58, namely the delay selection special function register adds " 1 " automatically the retention time, until SOC (system on a chip) microcontroller kernel can be read the out of order logical consequence value identical with the expection fixed value.The value bit wide of the out of order logical consequence special function register 402 of operated by rotary motion, namely the value of n can be 32,64 or 96, even higher.The bit wide that out of order logical consequence is read special function register 402 is larger, and then the probability of makeing mistakes will be less the dynamic adjustments retention time.
It should be noted that; the above embodiment of the present invention only is used for example and unrestricted; for example pile system of the present invention can comprise more multi-layered chip fully, and other embodiment that those skilled in the art have done according to instruction of the present invention and enlightenment is all at the row of protection of the present invention.
Claims (16)
1. the adjusting gear of retention time on the timing path is characterized in that described timing path is the same timing path of different chip chambers in the SOC (system on a chip); The adjusting gear of described retention time comprises:
Be arranged at the retention time time-delay mechanism on the described chip; This retention time time-delay mechanism is selected to adding different time-delays on the data routing in the described timing path; And
Be arranged at the retention time calibration equipment on the described chip; Described retention time calibration equipment uses the retention time of the described timing path of out of order logic verify whether to satisfy correct sequential needs, and described retention time time-delay mechanism is adjusted described time-delay based on the check results of described retention time calibration equipment until satisfy correct sequential needs.
2. adjusting gear as claimed in claim 1 is characterized in that, the host microcontroller kernel of described retention time time-delay mechanism and described SOC (system on a chip) is arranged on the same chip.
3. adjusting gear as claimed in claim 1 is characterized in that, described retention time time-delay mechanism comprises a MUX, and this MUX is arranged on the described time series data path, and between the input and output pin and combinational logic of chip.
4. adjusting gear as claimed in claim 3, it is characterized in that, the selecting side of described MUX is connected to the output terminal of the retention time delay selection special function register of described SOC (system on a chip), and the data input pin 0-n of described MUX connects respectively the delay unit of 1 to n+1 series connection; Wherein, n 〉=2.
5. adjusting gear as claimed in claim 4 is characterized in that, when described check results showed that the described retention time is not satisfied correct sequential needs, retention time delay selection special function register was from increasing 1.
6. adjusting gear as claimed in claim 1 is characterized in that, the maximum delay of described retention time is the minimum time-delay that the maximum delay of clock path in the described timing path deducts data routing in the described timing path.
7. adjusting gear as claimed in claim 1 is characterized in that, described retention time calibration equipment is arranged on the different chips from the host microcontroller kernel of described SOC (system on a chip).
8. adjusting gear as claimed in claim 1, it is characterized in that, described retention time calibration equipment comprises at least two read-write out of order logical consequence special function registers and forms, and described at least two out of order logical consequence special function registers share a power-on reset signal; The clock input of each special function register is connected to the output of an out of order logic input clock special function register on the described SOC (system on a chip), and the data input is connected to respectively logical zero or logical one.
9. the method for adjustment of retention time on the timing path is characterized in that this timing path is the same timing path of different chip chambers in the SOC (system on a chip); The method of adjustment of described retention time comprises:
On described chip, select to adding different time-delays on the data routing in the described timing path;
On described chip, use the retention time of the described timing path of out of order logic verify whether to satisfy correct sequential needs; And adjust described time-delay until satisfy correct sequential.
10. method of adjustment as claimed in claim 9, it is characterized in that, it uses a retention time time-delay mechanism to apply described time-delay, described retention time time-delay mechanism comprises a MUX, this MUX is arranged on the described time series data path, and between the input and output pin and combinational logic of chip.
11. method of adjustment as claimed in claim 10, it is characterized in that, the selecting side of described MUX is connected to the output terminal of the retention time delay selection special function register of described SOC (system on a chip), and the data input pin 0-n of described MUX (n 〉=2) connects respectively the delay unit of 1 to n+1 series connection.
12. method of adjustment as claimed in claim 11 is characterized in that, when described check results showed that the described retention time is not satisfied correct sequential needs, retention time delay selection special function register was from increasing 1.
13. method of adjustment as claimed in claim 9 is characterized in that, the maximum delay of described retention time is the minimum time-delay that the maximum delay of clock path in the described timing path deducts data routing in the described timing path.
14. method of adjustment as claimed in claim 9 is characterized in that, it uses a retention time calibration equipment to carry out described verification.
15. method of adjustment as claimed in claim 14, it is characterized in that, described retention time calibration equipment comprises at least two read-write out of order logical consequence special function registers and forms, and described at least two out of order logical consequence special function registers share a power-on reset signal; The clock input of each out of order logical consequence special function register is connected to the output of an out of order logic input clock special function register on the described SOC (system on a chip), and the data input is connected to respectively logical zero or logical one.
16. method of adjustment as claimed in claim 15 is characterized in that, further comprises:
Described SOC (system on a chip) powers on;
Described out of order logic input clock special function register overturns;
Whether the output valve that detects described out of order logical consequence special function register equals the value of its input end.
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| CN104900260A (en) * | 2014-03-07 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Time-delay selector |
| CN106383793A (en) * | 2016-09-05 | 2017-02-08 | 邦彦技术股份有限公司 | External device access method and system on chip |
| CN110018654A (en) * | 2019-03-19 | 2019-07-16 | 中科亿海微电子科技（苏州）有限公司 | Fine granularity programmable timing sequence control logic module |
| US10381330B2 (en) | 2017-03-28 | 2019-08-13 | Silicon Storage Technology, Inc. | Sacrificial alignment ring and self-soldering vias for wafer bonding |
| CN117368698A (en) * | 2023-11-01 | 2024-01-09 | 上海合芯数字科技有限公司 | Chip circuit and testing method thereof |
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| CN101592976A (en) * | 2009-04-16 | 2009-12-02 | 苏州国芯科技有限公司 | A kind of with the method for on-chip emulator clock synchronization to the microprocessor clock territory |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104900260A (en) * | 2014-03-07 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Time-delay selector |
| CN106383793A (en) * | 2016-09-05 | 2017-02-08 | 邦彦技术股份有限公司 | External device access method and system on chip |
| WO2018040128A1 (en) * | 2016-09-05 | 2018-03-08 | 邦彦技术股份有限公司 | Access method and system-on-chip for external device |
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| CN110018654A (en) * | 2019-03-19 | 2019-07-16 | 中科亿海微电子科技（苏州）有限公司 | Fine granularity programmable timing sequence control logic module |
| CN110018654B (en) * | 2019-03-19 | 2021-09-14 | 中科亿海微电子科技（苏州）有限公司 | Fine-grained programmable sequential control logic module |
| CN117368698A (en) * | 2023-11-01 | 2024-01-09 | 上海合芯数字科技有限公司 | Chip circuit and testing method thereof |
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