JP2012150656A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it hard to generate any waste in a storage capacity in a data buffer for communication, and to reduce the bus traffic of communication data.SOLUTION: A bridge circuit for communication is adopted for interfacing a communication circuit having a plurality of communication channels to an internal bus, and a buffer memory to which communication channel buffer areas corresponding to the communication channels one to one are assigned is adopted to the bridge circuit for communication, and the buffer memory is interfaced via the bus interface circuit to the internal bus on one side, and the buffer memory is interfaced via a communication channel interface circuit to the communication circuit on the other side. The communication channel interface circuit is configured to perform control for reading transmission data to be applied to the corresponding communication channel from the communication channel buffer area, and for writing reception data to be applied from the communication channel in the corresponding communication channel buffer area on the basis of the definition information of the communication channel buffer area set in a register circuit via the internal bus.

Description

  The present invention relates to a transmission / reception data buffer control technique in a semiconductor device having a plurality of communication channels, for example, a technique effective when applied to a microcomputer having a communication function.

  In a microcomputer having a plurality of communication channels as peripheral functions of the central processing unit (CPU), communication is performed when setting communication conditions by the CPU for the communication channel, writing transmission data to the communication channel, and reading received data by the communication channel. The CPU accesses the communication channel via an internal bus to which the channels are commonly connected, or a direct memory access controller (DMAC) must control data transfer between the communication channel and the data memory. When communication using a plurality of communication channels is performed in parallel, the amount of data transfer on the bus increases significantly. Patent Document 1 shows an example of such a microcomputer that is applied to an on-chip debug emulator, which includes a plurality of serial communication circuits as communication channels, each of which includes a dedicated transmission buffer and a dedicated transmission buffer. A reception buffer is provided.

JP 2008-226083 A

  The present inventor has examined the access by the CPU and DMAC to the transmission / reception data buffers in a plurality of communication channels and found the following problems.

  This is a point related to data traffic of a bus to which a plurality of communication channels are commonly connected and a buffer capacity of the communication channel. When each communication channel has a buffer for transmission / reception data, the individual storage capacity is relatively small so that the circuit scale does not become unnecessarily large. When the CPU performs processing such as compare or search on the received data of a communication channel such as a serial communication interface (SCIF), the CPU must receive and process a huge amount of received data sequentially via the bus. Even when receiving data is sequentially stored in a large-capacity data memory, data is sequentially transferred from the buffer of the communication channel to the memory. Even if a DMA transfer control channel is provided for each data transfer channel, the point Will not change. This is because the buffer of each communication channel cannot have a storage capacity enough to temporarily reduce bus data traffic. Conversely, if the capacity of the data buffer of each communication channel is increased, the waste of storage areas that are not used increases.

  If the status information of received data must also be read and managed from the buffer for each communication channel, the process of reading data from the buffer of the communication channel, the determination process of the read data, and the determination process result are reflected in the subsequent process. Operation becomes necessary, and the processing by the CPU or the like related to data reception becomes complicated.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that is unlikely to waste storage capacity in a communication data buffer and can reduce bus traffic for communication data.

  Another object of the present invention is to provide a semiconductor device capable of reducing the processing load of a central processing unit for communication data.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a communication bridge circuit is employed to interface a communication circuit having a plurality of communication channels to the internal bus. A CPU is connected to the internal bus. The communication bridge circuit employs a buffer memory in which a communication channel buffer area corresponding to the communication channel is assigned one-to-one. Via the communication circuit. The communication channel interface circuit reads the transmission data to be given to the corresponding communication channel from the communication channel buffer area based on the definition information of the communication channel buffer area set in the register circuit via the internal bus, and receives from the communication channel. Control to write data to the corresponding communication channel buffer area.

  Since the communication channel buffer area can be defined for each communication channel according to the definition information, communication channels with a large amount of communication can be used without wasteful storage capacity compared to the case where a dedicated buffer is provided for each communication channel. A large buffer area can be used. It is possible to control the bus traffic of communication data on the bus according to the setting of the size of the channel buffer area. For example, if the channel buffer area is set large, the primary holding period of received data can be lengthened, so that the data output interval from the buffer area to the bus can be lengthened accordingly, and the bus traffic can be reduced. It becomes possible. This leads to a reduction in processing load on the central processing unit for communication data in terms of processing speed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is difficult to waste storage capacity in the communication data buffer, and it is possible to reduce communication data bus traffic.

  In addition, the processing load on the central processing unit for communication data can be reduced.

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention. FIG. 2 is a block diagram showing a specific example of a communication bridge circuit. FIG. 3 is a timing chart illustrating details of the transmission operation and the reception operation. FIG. 4A is an explanatory diagram illustrating an array of transmission data in a transmission processing operation in which part of the same data is repeatedly transmitted. FIG. 4B is an explanatory diagram of operation timing when transmission data is sequentially set in a buffer such as a temporary transmission data buffer without using a variable capacity buffer memory for the array data of FIG. 4A and transmission is performed each time. . FIG. 4C is an explanatory diagram of the transmission operation timing in the case of the present embodiment using a buffer memory having a variable capacity for the array data of FIG. 4A. FIG. 5 is an operation explanatory diagram illustrating a procedure for writing communication data to the buffer memory by the CPU when 6-byte data including partially fixed data is repeatedly transmitted as shown in FIG. 4C. FIG. 6 is a block diagram showing a specific example of the communication bridge circuit according to the second embodiment of the present invention. FIG. 7 is an explanatory diagram illustrating a compare operation based on register settings by the bus interface circuit. FIG. 8 is a block diagram showing a specific example of the communication bridge circuit according to the third embodiment of the present invention. FIG. 9 is a flowchart illustrating the operation of the transfer control circuit in the extended reception mode. FIG. 10 is a timing chart illustrating the timing of the data reception operation based on the sequence of FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Mapping variable capacity communication buffer for multiple communication channels in memory>
A semiconductor device (1) according to a representative embodiment of the present invention includes an internal bus (28), a central processing unit (25) connected to the internal bus, and a communication circuit (11) having a plurality of communication channels. And a communication bridge circuit (10) for connecting the communication circuit to the internal bus. The communication bridge circuit includes a bus interface circuit (31, 31A, 31B) connected to the internal bus, and a buffer memory to which a communication channel buffer area connected to the bus interface circuit and corresponding to the communication channel is assigned one-to-one. (32), and a communication interface circuit (33, 33B) for controlling transmission data read from the communication channel buffer area to the corresponding communication channel and writing received data given from the communication channel to the corresponding communication channel buffer area And a register circuit (30, 30A, 30B) for providing the communication interface circuit with definition information in which the definition information of the communication channel buffer area is set and set via the bus interface circuit.

  Since the communication channel buffer area can be defined for each communication channel according to the definition information, communication channels with a large amount of communication can be used without wasteful storage capacity compared to the case where a dedicated buffer is provided for each communication channel. A large buffer area can be used. It is possible to control the bus traffic of communication data on the bus according to the setting of the size of the channel buffer area. If the channel buffer area is set large, the primary retention period of received data can be lengthened, so the data output interval from the buffer area to the bus can be lengthened accordingly, and bus traffic can be reduced. become. This leads to a reduction in processing load on the central processing unit for communication data in terms of processing speed.

[2] <Address register and communication status register of register circuit>
2. The semiconductor device according to item 1, wherein the communication interface circuit controls communication channel interface circuits (CHIF0 to CHIF4) corresponding to the communication channel on a one-to-one basis, and data transfer between the communication channel interface circuit and the buffer memory. Transfer control circuit (40, 40B). The register circuit includes, for each communication channel, a start address register (BSAREG) that defines a start address of a corresponding communication channel buffer area and an end address register (BEAREG) that defines an end address, and the corresponding communication channel interface circuit And a status register (STREG) which is set with communication status status information and can be referred to by the central processing unit.

  The central processing unit can directly refer to the status information set in the status register without reading the communication channel buffer area reception data and determining the communication state. It is possible to read and process only. In this respect also, it is possible to contribute to reduction of bus traffic and reduction of processing load on the central processing unit.

[3] <Interrupt request logic>
In the semiconductor device according to Item 2, the register circuit further includes an interrupt request logic (50, 50A, 50B) for outputting an interrupt request to the central processing unit in accordance with status information held in the status register.

  The central processing unit can refer to the status information after waiting for the generation of an interrupt request. It is also possible to start necessary processing such as reading received data in accordance with the cause of the interrupt request without referring to the status information.

[4] <DMA transfer request logic>
The semiconductor device according to Item 2, comprising a direct memory access controller connected to the internal bus,
The register circuit further includes data transfer request logic (51, 51A, 51B) for outputting a data transfer request to the direct memory access controller in accordance with the status information held in the status register.

  A process of transferring necessary received data to a data memory or the like can be performed by starting a direct memory access after waiting for a data transfer request without performing a data transfer process by the central processing unit.

[5] <Transmission trigger for communication channel interface circuit>
In the semiconductor device according to Item 2, when the write address for the buffer memory matches the start address set in the register circuit, the bus interface circuit transmits to the communication channel interface circuit corresponding to the matched start address. The start of transmission is instructed by a start trigger signal (TRSTR).

  A transmission start trigger for the communication interface circuit can be generated by simple logic.

[6] <Communication channel buffer access by communication channel interface circuit>
In the semiconductor device according to Item 3, the communication channel interface circuit includes a reception address counter (RACUNT) and a transmission address counter (TACUNT) that generate an access address for the buffer memory, and an address count value by the reception address counter. A temporary reception buffer (RDBUF) for holding communication data, and a temporary transmission buffer (TDBUF) for holding transmission data for each address count value by the transmission address counter. The transfer control circuit writes data from the temporary reception buffer to the corresponding communication channel buffer based on the value of the reception address counter, and from the corresponding communication channel buffer based on the value of the transmission address counter. Controls reading of data into the temporary transmission buffer. The reception address counter and the transmission address counter are initialized with a start address from the register circuit, and the value of the reception address counter is updated each time data is written from the temporary reception buffer to the corresponding communication channel buffer. The value of the transmission address counter is updated each time data is read from the communication channel buffer to the temporary transmission buffer.

  Address point control for buffer memory access by the communication channel interface circuit according to the allocation of the communication channel buffer area can be easily realized.

[7] <Time slot access timing slot control to buffer memory by transfer control circuit>
In the semiconductor device according to item 6, the transfer control circuit assigns timing slots for writing data from the temporary reception buffer to the buffer memory in correspondence with all communication channels in a time-sharing manner, and transfers data from the buffer memory to the temporary transmission buffer. A timing control circuit (60, 60B) that performs control for sequentially assigning data read timing slots to all communication channels in a time-sharing manner and a write timing slot assigned by the timing control circuit correspond to the arrival. When the temporary reception buffer of the communication channel interface circuit is in the data holding state, the reception data input from the temporary reception buffer is received and written to the buffer memory, and assigned by the timing control circuit. A transfer protocol logic circuit (61) that controls to read the transmission data from the buffer memory and transfer it to the corresponding temporary transmission buffer when the temporary transmission buffer of the corresponding communication channel interface circuit is empty when the read timing slot arrives. 61B).

  When the operation speed of the communication bridge circuit is much higher than the data transmission / reception speed by the communication circuit, the timing to write the received data supplied from the communication circuit to the temporary receive buffer in the corresponding communication channel buffer area is time-shared. Similarly, the timing for writing the transmission data supplied to the communication circuit from the corresponding communication channel buffer area to the corresponding temporary transmission buffer can be easily controlled by the time-divided default slot. can do.

[8] <Sequential address update operation of address counter>
In the semiconductor device of Item 7, the communication channel interface circuit sequentially updates the value of the transmission address counter every time the transmission data is read from the corresponding communication channel buffer area to the temporary transmission buffer, and changes from the start address to the end address. Each time reception data is written from the temporary reception buffer to the corresponding communication channel buffer area, the value of the reception address counter is sequentially updated to change from the start address to the end address.

  It is possible to simplify the point address generation logic of buffer memory access for reading transmission data from the communication channel buffer area to the temporary transmission buffer and writing reception data from the temporary reception buffer to the communication channel buffer.

[9] <Update skip for partially identical data in repeated transmission>
In the semiconductor device according to Item 8, when the central processing unit repeatedly transmits data in the communication channel buffer area defined by the register circuit, the transmission data is written in all areas of the communication channel buffer area in the first transmission. Transmission is instructed, and in subsequent transmission, only transmission data in a part of the communication channel buffer area is updated and transmission is instructed.

  To reduce the trouble of the central processing unit writing the fixed code to the buffer memory each time when a fixed code indicating the beginning or end of the packet is added each time transmission data is repeatedly transmitted in units such as packets. I can do it.

[10] <Bus interface with compare function for received data>
In the semiconductor device according to item 1, the bus interface circuit (31A) compares the received data stored in the buffer memory with the comparison target data, accumulates the comparison results, and can refer to the accumulated comparison results to the central processing unit. To.

  Even if the CPU does not refer to all the received data stored in the buffer memory, it can read and process only the necessary received data by referring to the comparison result accumulated by the bus interface circuit, and the central processing This can contribute to reducing the burden on the apparatus, reducing the bus traffic, and improving the data processing efficiency for the received data.

[11] <Compare data, compare address area and comparison result register>
In the semiconductor device according to Item 10, the control register circuit (30A) sets a compare data register (CMPDREG) in which the comparison target data is set, and an address area on a buffer memory of received data to be compared with the comparison target data. Compare address area designation registers (CMOSAREG, CMPEAREG) and a compare result register (CMPRSLTREG) in which the comparison results are stored.

  The range of received data to be compared with the comparison target data can be easily made variable.

[12] <Register holding the number of comparisons>
In the semiconductor device according to Item 11, the control register circuit further includes a competition account register (CMPCOUNTREG) that holds the number of comparison matches of the comparison result.

  It is possible to easily cope with a case where attention is paid to a state where a specific code repeatedly appears.

[13] <Interrupt request logic>
In the semiconductor device of item 12, the register circuit further includes an interrupt request logic (50A) for requesting an interrupt to the central processing unit when the number of comparison matches held by the comparison account register reaches a predetermined number.

  The central processing unit can wait for the generation of an interrupt request, refer to the compare result register, etc., or start interrupt processing according to the number of comparison matches held in the comparison account register.

[14] <DMA transfer request logic>
Item 12. The semiconductor device according to Item 12, comprising a direct memory access controller connected to the internal bus,
The register circuit further includes a data transfer request logic (51A) for outputting a data transfer request to the direct memory access controller when the number of comparison matches held by the competition account register reaches a predetermined number.

  A process for transferring necessary received data to the data memory can be performed by starting the direct memory access after waiting for the data transfer request without performing the data transfer process by the central processing unit.

[15] <Communication channel interface with compare function for received data>
In the semiconductor device according to Item 1, the communication interface circuit (33B) includes a communication channel interface circuit (CHIF0 to CHIF4) corresponding to the communication channel on a one-to-one basis, and data between the communication channel interface circuit and the buffer memory. A transfer control circuit (40B) for controlling transfer. The communication channel interface circuit includes a reception address counter (RACUNT) and a transmission address counter (TACUNT) for generating an access address for the buffer memory, and a temporary address for holding communication data for each address count value by the reception address counter. A reception buffer (RDBUF) and a temporary transmission buffer (TDBUF) for holding transmission data for each address count value by the transmission address counter. The transfer control circuit writes data from the temporary reception buffer to the corresponding communication channel buffer based on the value of the reception address counter, and from the corresponding communication channel buffer based on the value of the transmission address counter. Controls reading of data into the temporary transmission buffer. The transfer control circuit further compares the received data received in the temporary reception buffer with the comparison target data, transitions to a write operation to the communication channel buffer area according to the comparison result, and the transition of the transitioned write operation The result can be referred to the CPU.

  The received data input to the temporary receive buffer can be checked in advance based on the comparison result with the comparison target data, and only the necessary received data can be transferred to the communication channel buffer. It is not necessary to transfer all received data to the corresponding communication channel buffer. Furthermore, in order to arrange unnecessary received data in advance, the burden on the central processing unit is reduced, bus traffic is reduced, and further reception is performed. It can contribute to improvement of data processing efficiency for data.

[16] <Communication channel interface with compare function for received data>
In the semiconductor device according to Item 15, the control register circuit (30B) responds to a compare data register (CMPRDREG) in which comparison target data to be compared with reception data is set, and a comparison result between the reception data and the comparison target data. A compare point memory address register (CMPMAREG) in which a memory address to which received data is written is set, and a branch condition setting register (DVGCNDREG) in which an operation mode for received data is set in the temporary reception buffer according to the comparison result And a plurality of sets. The transfer control circuit (40B) has an extended reception mode in which required reception data is selected from reception data and stored in the buffer memory in accordance with setting values set in the plurality of sets of registers.

  By freely using a plurality of sets of registers for each communication channel, it is possible to variably set the processing sequence for the received data input to the temporary reception buffer.

[17] <Interrupt request logic>
16. The semiconductor device according to Item 16, wherein the register circuit further includes the central processing unit when the transfer control circuit completes writing of received data to an address set by a predetermined compare point memory address register according to the setting of the branch condition setting register. It has an interrupt request logic (50B) for requesting an interrupt to the processing device.

  The central processing unit can refer to the received data written in the buffer memory after waiting for the generation of the interrupt request, or can start the interrupt processing corresponding to the interrupt factor corresponding to the interrupt request.

[18] <DMA transfer request logic>
Item 16. The semiconductor device according to Item 16, further comprising a direct memory access controller connected to the internal bus. The register circuit further requests a data transfer request to the direct memory access controller when the transfer control circuit completes writing received data to an address set by a predetermined compare point memory address register according to the setting of the branch condition setting register. Has a data transfer request logic (51B).

  A process for transferring necessary received data to the data memory can be performed by starting the direct memory access after waiting for the data transfer request without performing the data transfer process by the central processing unit.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1]
FIG. 1 illustrates a microcomputer according to an embodiment of the present invention. The microcomputer 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a CMOS integrated circuit manufacturing technique.

  The microcomputer 1 (MCU) includes an internal bus 28, a central processing unit (CPU) 25 connected to the internal bus 28, a communication circuit 11 having a plurality of communication channels, and the communication circuit 11 connected to the internal bus 28. And a communication bridge circuit (COMBRDG) 10 connected to. For example, a plurality of communication devices (COMDEV) 2 and 3 as external devices are connected to the communication circuit 11. Although the communication circuit 11 is not particularly limited, the communication circuit 11 includes a serial communication interface circuit having a plurality of serial communication interface (SCI) channels (CH0 to CHn) as communication channels. The CPU 25 sequentially fetches the instructions described in the program, decodes the fetched instructions, and executes the instructions by performing an address operation or a data operation according to the decoding result.

  In addition to the internal bus 28, there are other direct memory access controllers (DMAC) 20 and 22, a data transfer controller (DTC) 22, an interrupt controller (INTC) 21, a timer (TMR) 27, a random area used for a work area of the CPU 25, and the like. It has an access memory (RAM) 24, a read only memory (ROM) 26 for storing programs executed by the CPU 25, data, and the like, an external bus interface (EXIF) 12, and a memory controller (MCNT) 13.

  In the DMAC 20, control data (transfer source address, transfer destination address, transfer word number, etc.) for data transfer control is set in advance by the CPU 25, and for example, a DMA transfer request signal DREQ is supplied from the communication bridge circuit 10. Data transfer is started according to the transfer conditions specified by the transfer control data.

  When the interrupt request signal IRQ is supplied from the communication bridge circuit 10 or the like, the interrupt controller 21 performs arbitration according to the interrupt priority level or the interrupt mask level and outputs the interrupt signal INT to the CPU 25. When the interrupt signal INT is supplied, the CPU 25 ends the instruction execution, saves the internal state for recovery, and branches the program flow to a process corresponding to the interrupt factor of the interrupt request.

  A large capacity synchronous dynamic random access memory (SDRAM) 4 is connected to the memory controller 13 although not particularly limited.

  The SCI channels CH0 to CHn included in the communication circuit 11 are circuits that perform serial data communication in an asynchronous manner that synchronizes in character units. For example, one character has a bit configuration having a start bit (ST) at the beginning, a stop bit (ST) at the end, and 8-bit data therebetween.

  The communication bridge circuit 10 includes a bus interface circuit (BUSIF) 31 connected to the internal bus 28, and a buffer connected to the bus interface circuit 31 and assigned with a communication channel buffer area corresponding to the communication channels CH0 to CHn. A memory (MRY) 32; a communication interface circuit (COMIF) 33 for controlling transmission data read from the communication channel buffer area to the corresponding communication channel and writing received data given from the communication channel to the corresponding communication channel buffer area; The communication channel buffer area definition information is set via the bus interface circuit 31, and a register circuit (CREG) 30 for supplying the set definition information to the communication interface circuit 33. The buffer memory 32 is constituted by a RAM having a dual port. The dual port may be either a dual port that can be accessed in parallel or a dual port that can be accessed in time division.

  FIG. 2 shows a specific example of the communication bridge circuit 10.

  The SCI channels CH0 to CHn (in this case, n = 4) of the communication circuit 11 are not particularly limited, but receive transmission data in parallel in character units from the communication interface circuit 33 and synchronize with the serial clock SCICLK to the serial output terminal SOUT. A transmission register circuit TREG for serial output and a reception register circuit RREG for receiving received data in character units from the serial input terminal SIN in synchronization with the serial clock SCICLK and outputting the data to the communication interface 33 in parallel.

  The communication interface circuit 33 includes communication channel interface circuits CHIF0 to CHIF4 that correspond one-to-one with the communication channels CH0 to CH4, and a transfer control circuit that controls data transfer between the communication channel interface circuits CHIF0 to CHIF4 and the buffer memory 32. (TRCNT) 40.

  Each of the communication channel interface circuits CHIF0 to CHIF4 holds communication data for each address count value by the reception address counter RACUNT and transmission address counter TACUNT for generating an access address for the buffer memory 32, and the reception address counter RACUNT. A temporary reception buffer RDBUF; and a temporary transmission buffer TDBUF for holding transmission data for each address count value by the transmission address counter TACUNT. The communication channel interface circuits CHIF0 to CHIF4 are operated in synchronization with the system clock SYSCLK. The system clock signal SYSCLK has a frequency several times higher than that of the serial clock signal SCICLK.

  The transfer control circuit 40 controls writing of data from the temporary reception buffer RDBUF to the corresponding communication channel buffer on the buffer memory 32 based on the value of the reception address counter RACUNT, and also transmits the transmission address. Based on the value of the counter TACUNT, data reading control from the corresponding communication channel buffer on the buffer memory 32 to the temporary transmission buffer TDBUF is performed. The reception address counter RACUNT and the transmission address counter TACUNT are initially set with a start address from the register circuit 30. Each time data is written from the temporary reception buffer RDBUF to the corresponding communication channel buffer, the reception address counter RACUNT The value is updated, and the value of the transmission address counter TACUNT is updated every time data is read from the communication channel buffer to the temporary transmission buffer TDBUF.

  The register circuit 30 corresponds to each of the communication channels CH0 to CH4, a start address register BSAREG that defines a start address of a corresponding communication channel buffer area, an end address register BEAREG that defines an end address, and the corresponding communication A status register STREG in which status information of the communication state is set by the channel interface circuits CHIF0 to CHIF4 is separately provided for transmission and reception. These registers are arranged in the address space of the CPU 25, and the CPU 25 can arbitrarily set data via the bus interface circuit 31. The communication channel buffer area grasped by the CPU 25 and the communication interface circuit 33 in accordance with the definition information of the registers BSAREG and BEAREG is allocated separately for transmission and reception for each communication channel as illustrated in FIG. For example, CHBUF0_R is a communication channel buffer for received data assigned to the communication channel CH0, and CHBUF0_T is a communication channel buffer for transmission data assigned to the communication channel CH0. CHBUF4_R is a communication channel buffer for received data assigned to the communication channel CH4, and CHBUF4_T is a communication channel buffer for transmission data assigned to the communication channel CH4. It goes without saying that the sizes of the reception buffer area and the transmission buffer area do not have to be the same.

  The register circuit 30 further includes an interrupt request logic (IRQLGC) 50 that outputs an interrupt request signal IRQ that requests a predetermined interrupt process to the CPU 25 according to the status information held in the status register STREG, and the status register STREG. A data transfer request logic (DREQLGC) 51 that outputs a data transfer request signal DREQ to the DMAC 20 according to the status information is included.

  For example, the interrupt request logic 50 asserts an interrupt request signal when the reception completion status is set in the status register STREG, and enables the CPU 25 to refer to the interrupt factor due to the reception completion and the communication channel number in which the factor has occurred. Therefore, the CPU 25 can refer to the status information after waiting for the occurrence of the interrupt request, and also needs a process of reading the received data from the communication channel buffer area according to the cause of the interrupt request without referring to the status information. Processing can be started. The data transfer request logic 51 asserts the data transfer request signal DREQ when the reception completion status is set in the status register STREG, and the DMAC 20 starts DMA transfer in accordance with preset data transfer control conditions. The received data is transferred to the SDRAM 4 or the like. In the figure, one interrupt request signal IRQ and one data transfer request signal DREQ are representatively shown. However, a plurality of interrupt request signal output functions are adopted within the allowable range of the interrupt controller 21, and the DMAC 20 It is also possible to employ a function of outputting a plurality of data transfer request signals according to the number of DMA transfer channels.

  The CPU 25 can arbitrarily refer to the contents of the status register STREG by polling or the like.

  The bus interface circuit 31 has a function of interfacing the buffer memory 32 and the register circuit 30 to the CPU 25 and the like via the internal bus 28 so that read access and write access are possible. In particular, in this embodiment, when the write address to the buffer memory 32 via the internal bus 28 matches the start address preset in the start address register BSAREG of the register circuit 30, the communication corresponding to the matched start address The channel interface circuits CHIF0 to CHIF4 are instructed to start transmission by a transmission start trigger signal TRSTR. For example, when the CPU 25 sequentially writes the transmission data in the communication channel buffer area CHBUF_T corresponding to the communication channel CH0 and finally writes the transmission data to the head address of the communication channel buffer area CHBUF_T, the address is stored in the communication channel CH0. By matching with the address of the corresponding buffer start address register BSAREG, the bus interface circuit 31 activates the transmission start trigger signal TRSTR. In response, the transfer control circuit 40 reads transmission data in character units from the communication channel buffer area CHBUF0_T into the temporary transmission data buffer TDBUF starting from the initial address of the transmission address counter TACUNT of the communication channel interface circuit CHIF0, Is applied to the circuit TREG. The transmission register circuit TRREG serially outputs transmission data to the terminal SOUT in synchronization with the serial clock SCICLK. The transfer control circuit 40 repeats this operation until the address value of the transmission address counter TACUNT reaches the memory address held by the buffer end address register BEAREG corresponding to the transfer channel CH0. The transmission start trigger signal TRSTR is positioned as a signal provided for each communication channel interface circuit. Thereby, a trigger for starting the transmission processing operation for the transfer control circuit 40 can be generated by simple logic.

  On the other hand, in the reception operation, for example, when reception data is input in character units to the reception register circuit RREG of the communication channel CH0, the reception data for one character is stored in the temporary reception data buffer RDBUF of the corresponding channel interface circuit CHIF0. The state is transferred, and this state is notified to the transfer control circuit 40. When the value held in the reception address counter RACUNT corresponding to the temporary reception data buffer RDBUF matches the address value held in the reception start address register corresponding to the transfer channel CH0, the transfer control circuit 40 responds to this. The received data is written in the communication channel buffer area CHBUF0_R in character units from the temporary received data buffer RDBUF starting from the initial address of the received address counter RACUNT of the communication channel interface circuit CHIF0. The transfer control circuit 40 repeats this operation until the address value of the reception address counter RACUNT reaches the memory address held by the reception buffer end address register BEAREG corresponding to the transfer channel CH0. Thereby, the trigger for starting the reception processing operation for the transfer control circuit 40 can be generated by simple logic.

  FIG. 3 illustrates a detailed timing chart of the transmission operation and the reception operation. Here, it is assumed that eight communication channels CH0 to CH7 (n = 7) are provided, and a case where timing slot control is performed in time division access to the buffer memory 32 by the transfer control circuit 40 will be described.

  As illustrated in FIG. 2, the transfer control circuit 40 controls the timing control circuit (TMGC) 60 that assigns timing slots and whether or not the buffer memory 32 is accessed in the assigned timing slots. A transfer protocol logic circuit (PRTCL) 61. More specifically, the timing control circuit 60 assigns a timing slot for writing data from the temporary reception buffer RDBUF to the buffer memory 32 in correspondence with all the communication channels CH0 to CH7 in a time-sharing manner and also transmits temporary transmission from the buffer memory 32. Control is performed in which the timing slot for reading data to the buffer TDBUF is sequentially assigned to all the communication channels CH0 to CH7 in time division. The transfer protocol logic circuit 61 receives the data received from the temporary reception buffer RDBUF when the temporary reception buffer RDBUF of the corresponding communication channel interface circuit is in the data holding state when the write timing slot assigned by the timing control circuit 60 arrives. Is received and written to the buffer memory 32, and when the read timing slot assigned by the timing control circuit 60 arrives, the transmission data from the buffer memory 32 is transmitted when the temporary transmission buffer TDBUF of the corresponding communication channel interface circuit is empty. Is read out and transferred to the corresponding temporary transmission buffer TDBUF.

  The premise of the timing slot control is that the access speed of the buffer memory 32 by the communication interface circuit 33 is much faster than the serial transmission / reception speed by the communication circuit 11. In the example of FIG. 3, in any period of serial reception operation and serial transmission operation for one character, the period of the write timing slot from COMIF 33 to MRY 32 and the read timing from MRY 32 to COMIF 33 for all communication channels of CH0 to CH7. The slot period can be secured. Specifically, each character is divided into 16 timings at the time of receiving and transmitting 1-byte data for one character, and the first to eighth divisions are assigned to the write timing slots in the buffer memory 32, and the ninth to Up to 16 divisions are assigned to read timing slots from the buffer memory 32. Thus, the COMIF 33 can always acquire the access right for writing and reading with respect to the buffer memory 32 once during serial communication for one character by each communication channel. In order to satisfy this, the quotient obtained by dividing the frequency of the system clock signal SYSCLK by the sum of the number of communication channels performing the transmission operation and the number of communication channels performing the reception operation is larger than the clock signal frequency of the serial clock signal SCICLK. Should be satisfied.

  FIG. 4A and FIG. 4C show an example of a transmission processing operation in which partly the same data is repeatedly transmitted. For example, as illustrated in FIG. 4A, a case will be described in which fixed transmission data AA, fixed transmission data BB, arbitrary transmission data data0, arbitrary transmission data data1, fixed transmission data CC, and fixed transmission data DD are repeatedly transmitted. Even in such a transmission process in which the same data is repeatedly transmitted, the transmission data is sequentially transmitted to a buffer such as a temporary transmission data buffer without using a variable capacity buffer memory as in this embodiment. In the case of a configuration in which the transmission is performed each time it is set, as shown in FIG. 4B, the completion of the previous transmission is confirmed in character units and the next transmission data is written in a buffer such as a temporary transmission data buffer. Processing must be written every time for all 6 bytes of data including fixed data AA, BB, CC, DD. On the other hand, in the case of the present embodiment, as illustrated in FIG. 4C, in the first 6 bytes transmission, transmission data is written in all areas of the required communication channel buffer area of the buffer memory 32 and transmitted. In the subsequent transmission, it is only necessary to update the transmission data in the part of the variable data data0 and data1 in the communication channel buffer area and instruct the transmission. Data serially output from the communication channel buffer area via the communication interface circuit 33 is AA, BB, data0, data1, CC, DD for the first 6-byte data and the next 6-byte data.

  When transmission data is repeatedly transmitted in units such as packets, when a fixed code indicating the transmission source or transmission destination of the packet is added every time, the CPU 25 reduces the trouble of writing the fixed code to the buffer memory 32 each time. I can do it.

  FIG. 5 illustrates a procedure for writing communication data into a required communication channel buffer area of the buffer memory 32 by the CPU 25 when 6-byte data including partially fixed data is repeatedly transmitted as shown in FIG. 4C. It is assumed that 6-byte data AA, BB, data0, data1CC, DD are stored in addresses A0 to A5 of the communication channel buffer area CHBUS0_T for transmission. In this case, the CPU 25 writes the data in the address A0 to A5 in the communication channel buffer area CHBUS0_T for transmission, and addresses A1, A2, A3, A4, A5 for the first transfer (first packet). Data BB, data0, data1, CC, DD, and AA are written in the order of A0. Finally, the start of transmission is instructed by the transmission start trigger signal TRSTR by writing to the head address A0 (address matching the set value of BSAREG) of the buffer area CHBUS0_T, and the transfer address counter TACUNT of the transfer channel interface circuit CHIF0 Data from the initial value A0 to the sequential address A5 is sequentially read from the buffer area CHBUS0_T to the temporary transmission buffer TDBUF, and the data AA, BB, data0, data1, CC, DD are sequentially transmitted to the outside. For the second time (second packet transmission), only variable data data0 and data1 are written in the order of addresses A2, A3 and A0. Finally, when writing to the head address A0 (address matching the setting value of BSAREG) of the buffer area CHBUS0_T is performed, the transmission start is instructed by the transmission start trigger signal TRSTR as in the first time, and the transfer channel interface The data from the initial value A0 of the transfer address counter TACUNT of the circuit CHIF0 to the sequential address A5 is sequentially read from the buffer area CHBUS0_T to the temporary transmission buffer TDBUF, and the data AA, BB, data0, data1, CC, DD are sequentially transferred to the outside. Sent. The third and subsequent times (third packet transmission) are the same as the second time, and it is only necessary to repeat the writing to the variable data data0, data1 and the address A0 as a transmission trigger as necessary.

  According to the first embodiment, the following operational effects can be obtained. That is, since the communication channel buffer area (CHBUF0_T, CHBUF0_R...) Can be defined for each of the communication channels CH0 to CHn according to the information defined in the register circuit 30, compared to the case where a buffer is dedicated for each communication channel. A large capacity buffer area can be used for a communication channel with a large communication volume without wasting storage capacity. It is possible to control the bus traffic of communication data on the bus according to the setting of the size of the channel buffer area. If the channel buffer area is set large, the primary retention period of received data can be lengthened, so the data output interval from the buffer area to the bus can be lengthened accordingly, and bus traffic can be reduced. become. This leads to a reduction in processing load on the CPU 25 for communication data in terms of processing speed.

  Since the CPU 25 can directly refer to the status information set in the status register STREG without reading the received data in the communication channel buffer area and determining the communication state, only the necessary reception data according to the communication state can be obtained. Can be processed by reading. Similarly, by providing an output function of an interrupt request signal IRQ and a data transfer request signal DREQ according to the value of the status register STREG, only necessary received data can be read and processed according to the communication state. Become. Also in these points, it can contribute to reduction of bus traffic and reduction of the processing load of CPU25.

[Embodiment 2]
FIG. 6 shows a specific example of a communication bridge circuit 10A according to Embodiment 2 of the present invention. The configuration of the register circuit 30A and the function of the bus interface circuit 31A are different from those of the communication bridge circuit 10 described with reference to FIG. 2, and the bus interface circuit 31A has a register circuit for the received data stored in the buffer memory 32. The compare function is realized based on the setting of 30A. Hereinafter, the configuration related to the difference will be described in detail, and the detailed description of the configuration similar to the first embodiment will be omitted.

  The control register circuit 30A includes a compare data register CMPDREG in which comparison target data to be compared with reception data stored in the buffer memory is set, and an address area on the buffer memory 32 for reception data to be compared with the comparison target data Compare start address register CMPSAREG for specifying the beginning of the comparison area, Compare end address register CMPEAREG for specifying the end of the address area, Compare result register CMPRSLTREG for storing the comparison results, and a comparison account for holding the number of comparison matches of the comparison results It has a register CMPCOUNTREG. These registers are arranged in the address space of the CPU 25 so that they can be accessed from the internal bus 28 via the bus interface circuit 31A, like the other registers. The CPU 25 refers to the reception data from the target communication channel being stored in the corresponding Tsutoshi channel buffer area and the status register is set to communication completion, or the status register is set to communication completion. In response to the interrupt request generated by the interrupt request signal IRQ, the registers CMPSAREG, CMPEAREG, and CMPDREG are written.

  For example, the bus interface circuit 31A detects the completion of data writing to the register register CMPDREG and starts a comparison operation. The received data in the range from the memory address specified by the register CMPSAREG to the memory address specified by the register CMPEAREG Are sequentially compared with the data in the register CMPDREG, the comparison result such as the address of the received data is stored in the register CMPRSLTREG, and the comparison match count is accumulated in the register CMPCOUNTREG.

  As a result, even if the CPU 25 does not refer to all of the received data stored in the buffer memory 32, the comparison result accumulated by the bus interface circuit 31A is referred to from the registers CMPRSLTREG and CMPCUNTREG, and only necessary received data is read. Can reduce the burden on the CPU 25, reduce bus traffic, and improve the data processing efficiency for received data. By referring to the count value of the register CMPCOUNTREG, it is possible to easily cope with a case where it is desired to pay attention to a state where a specific code repeatedly appears.

  In particular, the interrupt request logic (IRQLGC) 50A possessed by the register circuit 30A, when compared with the interrupt request logic 50 of FIG. 2, outputs an interrupt request signal IRQ to the CPU 25 when the number of comparison matches held by the competition account register CMPCOUNTREG reaches a predetermined number. An interrupt request generation function for asserting and enabling reference to the interrupt factor is added. As a result, the CPU 25 can wait for the generation of an interrupt request and refer to the compare result register CMPRSLTREG or the like, or can start an interrupt process according to the number of comparison matches held in the compare account register CMPCOUNTREG.

  Further, the data transfer request logic (DREQLGC) 51A possessed by the register circuit 30A is a data transfer request to the DMAC 20 when the number of comparison matches held by the CMPCOUNTREG in the competition account register reaches a predetermined number compared to the data transfer request logic 51 of FIG. A data transfer request function for outputting the signal DREQ is added. As a result, it is possible to perform a process of transferring necessary received data to the SDRAM 4 by waiting for a data transfer request by the request signal DREQ without activating the data transfer process by the CPU 25 and starting the direct memory access.

  FIG. 7 illustrates a compare operation based on the setting of the register circuit 30A by the bus interface circuit 31A. Here, a case where the received data stored in the communication channel buffer area CHBUF4_R corresponding to the communication channel CH4 is the target of the comparison process is illustrated. The addresses assigned to the communication channel buffer area CHBUF4_R are addresses 1000 to 1100. The register CMPSAREG is set to address 1000, the register CMPEAREG is set to address 1100, and the register CMPDREG is set to H'AAA. When the data H'AAA is written to the register CMPDREG, the comparison process is started. When the data H'AAA is referred to between the addresses 1000 to 1100 in the communication channel buffer area CHBUF4_R, the comparison result and its address are compared with the compare result register. Stored sequentially in CMPRSLTREG, the number of matches is accumulated in the competition account register CMPCOUNTREG. The CPU 25 refers to the compare result register CMPRSLTREG and the compare account register CMPCUNTREG to access necessary received data from the communication channel buffer area CHBUF4_R, or in response to an interrupt request, the CPU 25 refers to the communication channel buffer area CHBUF4_R or transfers data. In response to the request, the DMAC 20 performs processing for transferring data in the communication channel buffer area CHBUF4_R to the SDRAM 4.

[Embodiment 3]
FIG. 8 shows a specific example of the communication bridge circuit 10B according to the third embodiment of the present invention.

  The functions of the register circuit 30B, the bus interface circuit 31B, and the transfer control circuit 40B are different from those of the communication bridge circuit 10 described with reference to FIG. 2, and a transfer control circuit for received data input to the temporary reception buffer RDBUF. 40B realizes the compare function based on the setting of the register circuit 30B. Hereinafter, the configuration related to the difference will be described in detail, and the detailed description of the configuration similar to the first embodiment will be omitted.

  In the control register circuit 30B, a compare data register CMPRDREG in which comparison target data to be compared with reception data is set, and a memory address in which reception data is written according to a comparison result between the reception data and the comparison target data are set. A plurality of sets of compare condition memory address registers CMPPMAREG and branch condition setting registers DVGCNDREG in which an operation mode for received data received in the temporary reception buffer is set according to the comparison result, for example, register block RBLK0 and register block RBLK1 Two sets of are added.

  The transfer control circuit 40B compares the received data received in the temporary reception buffer with the comparison target data, transitions to a write operation to the communication channel buffer area according to the comparison result, and the transition of the transitioned write operation. A function for enabling the CPU to refer to the result is added. For example, according to setting values set in the plurality of register blocks RBLK0 and RBLK1, necessary received data is selected from the received data and stored in the buffer memory 32. Extended receive mode has been added.

FIG. 9 illustrates the operation of the transfer control circuit 40B in the extended reception mode. When data is received in the temporary reception buffer RDBUF, it is determined whether or not the received data matches the data in the compare data register CMPRDREG [RBLK0] of the register block RBLK0 (S1). The received data is written to the address on the buffer memory 32 designated by the compare point memory address register CMPPMAREG [RBLK0] of the register block RBLK0, and the address is preset in the received address counter RACUNT and incremented by +1 (S2). . Following this operation, a transition to the process indicated by the branch condition setting register DVGCNDREG [RBLK0] of the register block RBLK0 is instructed (S3).
For example, the determination processing target for the received data in the temporary reception buffer RDBUF is an instruction to change to the address of the compare point memory address register CMPPMAREG [RBLK0] of the register block RBLK1. According to the instruction, a match determination is made for the received address counter RACUNT (S4A), and the received data of the temporary receive buffer RDBUF is stored in the buffer memory 32 according to the count value of the address counter RACUNT until the match is reached (S5). If it is determined, for example, it is determined whether or not the received data matches the data in the compare data register CMPRDREG [RBLK1] of the register block RBLK1 (S4B). It is written to the address on the buffer memory 32 designated by the compare point memory address register CMPPMAREG [RBLK1] of RBLK1 (S6). After this operation, the branch condition setting register DVGCNDREG [RBLK1] of the register block RBLK1 is written. Transition to be processed is instructed (S7). For example, the reception process ends.

  In the operation transition instruction in step S3 after the reception data is written to the buffer memory 32 for the first time in step S2, the reception start status information is set in the predetermined status register STREG, and thereby the control register circuit 30B starts reception to the CPU 25. May be requested. Similarly, in the operation transition instruction in step S7 after the intended received data is written in the buffer memory 32 in step S6, status information indicating completion of reception is set in a predetermined status register STREG, thereby causing the CPU 25 to control the control register circuit 30B. A reception start interrupt may be requested, or the DMAC 20 may be requested to transfer received data.

  FIG. 10 shows a timing chart of the data reception operation based on the sequence of FIG.

  CC is set in the compare data register CMPRDREG [RBLK0] of the register block RBLK0, 100 is set in the compare point memory address register CMPPMAREG [RBLK0] of the register block RBLK0, and the compare data register CMPRDREG [RBLK1] of the register block RBLK01. Is set to DD, and address 104 is set to the compare point memory address register CMPPMAREG [RBLK1] of the register block RBLK1. The conditions of steps S4A, S4B, S5, S6 and S1 in FIG. 9 are set in the branch condition setting register DVGCNDREG [RBLK0] of the register block RBLK0. In the branch condition setting register DVGCNDREG [RBLK1] of the register block RBLK1, a condition for ending the reception process is set. As a result, in the example of FIG. 10, only the required received data CC, data1, data2, data3, and DD, which are part of the received data, are stored at addresses 100 to 104 of the buffer memory 32, and the reception process is terminated. Can do.

  According to this, it is possible to confirm the reception data based on the result of previously comparing the reception data input to the temporary reception buffer RDBUF with the comparison target data, and to transfer only the necessary reception data to the communication channel buffer. It is not necessary to transfer all of the reception data input to the temporary reception buffer RDBUF to the corresponding communication channel buffer area on the buffer memory 32. Further, in order to arrange unnecessary reception data in advance, the CPU 25 This can contribute to lightening the burden, reducing bus traffic, and improving the data processing efficiency for received data. By freely using a plurality of sets of registers typified by the register blocks RBLK0 and RBLK1 for each communication channel, it is possible to variably set the processing sequence for the reception data input to the temporary reception buffer RDBUF.

  In particular, the interrupt request logic (IRQLGC) 50B possessed by the control register circuit 30B is compared with the interrupt request logic 50 of FIG. 2 by the transfer control circuit 40B according to the setting of the branch condition setting register DVGCNDREG in accordance with a predetermined compare point memory address register CMPPMAREG. When the reception data writing to the address set in (1) is completed, an interrupt request signal IRQ for requesting an interrupt to the CPU 25 and a function for outputting the interrupt factor are added. As a result, the CPU 25 can refer to the received data written in the buffer memory 32 after an interrupt request is generated, or can start interrupt processing corresponding to the interrupt factor corresponding to the interrupt request. Become.

  Further, the data transfer request logic (DREQLGC) 51B held by the register circuit 30B is compared with the data transfer request logic 51 shown in FIG. A function for outputting a data transfer request signal DREQ to the DMAC 20 when writing of received data is completed at the address set by CMPPMAREG is added. Thereby, without performing the data transfer process by the CPU 25, a process of transferring necessary received data to the SDRAM 4 by waiting for the data transfer request and starting the DMA transfer can be performed.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, a single semiconductor device can be realized by combining the first to third embodiments.

  The communication channel interface circuit is not limited to double buffers for transmission and reception. The same applies to the communication channel buffer area. In those cases, the function may be switched dynamically according to the transmission / reception timing.

  A register such as a compare start memory register for a bus interface having a compare function for received data described in the second embodiment may be provided for each transfer channel. The number of register blocks RBLK0 and RBLK1 described in the third embodiment is not limited to two and may be more. As the number increases, more complex branch conditions can be set.

  The address area designation register in which the address area is set is not limited to the configuration designated by the start address and the end address, but may be designated by the start address and the area size.

  The communication circuit is not limited to the SCI, and may be a circuit used for another serial communication circuit or a parallel communication circuit.

  Registers (CMPASREG, CMPEAREG, CMPDREG, CMPRSLTREG, CMPCUNREG) used for the compare function of the bus interface circuit may be provided for each communication channel.

1 Microcomputer (MCU)
28 Internal bus 25 Central processing unit (CPU)
11 Communication Circuit 10 Communication Bridge Circuit (COMBRDG)
20 Direct memory access controller (DMAC)
21 Interrupt controller (INTC)
31 Bus interface circuit (BUSIF)
CH0 to CHn Communication channel 32 Buffer memory (MRY)
33 Communication interface circuit (COMIF)
30 register circuit (CREG)
SCICLK Serial clock TREG Transmission register circuit RREG Reception register circuit 40 Transfer control circuit (TRCNT)
RACUNT reception address counter TACUNT transmission address counter TDBUF Temporary transmission buffer CHIF0 to CHIF4 Communication channel interface circuit SYSCLK System clock BSAREG Start address register BEAREG End address register STREG Status register CHBUF0_R Communication channel buffer for reception data CHBUF0_T Buffer IRQ interrupt request signal 50 Interrupt request logic (IRQLGC)
51 Data transfer request logic (DREQLGC)
60 Timing control circuit (TMGC)
61 Transfer Protocol Logic Circuit (PRTCL)
CMPDREG compare data register CMPSAREG compare start address register CMPEAREG compare end address register CMPRSLTREG compare result register CMPCUNTREG compare account register CMPRDREG compare data register CMPPMAREG compare point memory address register DVGCNDREG branch condition setting register RBLK0, RBL

Claims (18)

An internal bus, a central processing unit connected to the internal bus, a communication circuit having a plurality of communication channels, and a communication bridge circuit for connecting the communication circuit to the internal bus,
The communication bridge circuit includes a bus interface circuit connected to the internal bus, a buffer memory connected to the bus interface circuit and assigned with a communication channel buffer area corresponding to the communication channel on a one-to-one basis, and the communication channel buffer area A communication interface circuit for controlling transmission data to be read from the communication channel to the corresponding communication channel and writing reception data given from the communication channel to the corresponding communication channel buffer area, and defining the communication channel buffer area via the bus interface circuit A semiconductor device, comprising: a register circuit configured to set information and set definition information to the communication interface circuit. The communication interface circuit includes a communication channel interface circuit corresponding to the communication channel on a one-to-one basis, and a transfer control circuit for controlling data transfer between the communication channel interface circuit and the buffer memory.
The register circuit has an address register that defines a start address and an end address of a corresponding communication channel buffer area for each communication channel, and status information of a communication state is set by the corresponding communication channel interface circuit, and the central processing unit The semiconductor device according to claim 1, further comprising: a status register that can be referred to by:   The semiconductor device according to claim 2, wherein the register circuit further includes an interrupt request logic that outputs an interrupt request to the central processing unit in accordance with status information held in the status register. A direct memory access controller connected to the internal bus;
The semiconductor device according to claim 2, wherein the register circuit further includes a data transfer request logic that outputs a data transfer request to the direct memory access controller in accordance with status information held in the status register.   When the write address to the buffer memory matches the start address set in the register circuit, the bus interface circuit starts transmission by a transmission start trigger signal to the communication channel interface circuit corresponding to the matched start address. The semiconductor device according to claim 2, wherein an instruction is given. The communication channel interface circuit includes a reception address counter and a transmission address counter that generate an access address for the buffer memory, a temporary reception buffer that holds communication data for each address count value by the reception address counter, and the transmission A temporary transmission buffer for holding transmission data for each address count value by the trusted address counter,
The transfer control circuit writes data from the temporary reception buffer to the corresponding communication channel buffer based on the value of the reception address counter, and from the corresponding communication channel buffer based on the value of the transmission address counter. Controlling the reading of data to the temporary transmission buffer;
The reception address counter and the transmission address counter are initialized with a start address from the register circuit, and the value of the reception address counter is updated each time data is written from the temporary reception buffer to the corresponding communication channel buffer. 4. The semiconductor device according to claim 3, wherein the value of the transmission address counter is updated each time data is read from the communication channel buffer to the temporary transmission buffer. The transfer control circuit assigns the timing slots for writing data from the temporary reception buffer to the buffer memory in correspondence with all communication channels in a time-sequential manner, and assigns all timing slots for reading data from the buffer memory to the temporary transmission buffer. A timing control circuit that performs control to sequentially correspond to the communication channels in time division, and
When the write timing slot allocated by the timing control circuit arrives, when the temporary reception buffer of the corresponding communication channel interface circuit is in the data holding state, the reception data input from the temporary reception buffer is received and written to the buffer memory, or When the read timing slot allocated by the timing control circuit arrives, control is performed to read the transmission data from the buffer memory and transfer it to the corresponding temporary transmission buffer when the temporary transmission buffer of the corresponding communication channel interface circuit is empty. The semiconductor device according to claim 6, further comprising: a transfer protocol logic circuit for performing.   The communication channel interface circuit sequentially updates the value of the transmission address counter every time data is read from the corresponding communication channel buffer area to the temporary transmission buffer, changes the value from the start address to the end address, and responds from the temporary reception buffer. 8. The semiconductor device according to claim 7, wherein the value of the reception address counter is sequentially updated every time reception data is written to the communication channel buffer area to be changed from the start address to the end address.   When the central processing unit repeatedly transmits data in the communication channel buffer area defined by the register circuit, in the first transmission, the transmission data is written in all areas of the communication channel buffer area, and transmission is instructed. 9. The semiconductor device according to claim 8, wherein in transmission, only transmission data in a part of the communication channel buffer area is updated to instruct transmission.   2. The semiconductor device according to claim 1, wherein the bus interface circuit compares the received data stored in the buffer memory with comparison target data, accumulates the comparison result, and makes the accumulated comparison result referable to the central processing unit. .   The control register circuit includes a compare data register in which the comparison target data is set, a compare address area designation register in which an address area on a buffer memory of received data to be compared with the comparison target data is set, and the comparison result is The semiconductor device according to claim 10, comprising a compare result register to be accumulated.   The semiconductor device according to claim 11, wherein the control register circuit further includes a competition account register that holds the number of comparison matches of the comparison result.   The semiconductor device according to claim 12, wherein the register circuit further includes an interrupt request logic that requests an interrupt to the central processing unit when the number of comparisons held by the competition account register reaches a predetermined number. A direct memory access controller connected to the internal bus;
13. The semiconductor device according to claim 12, further comprising: a data transfer request logic that outputs a data transfer request to the direct memory access controller when the number of comparison matches held by the competition account register reaches a predetermined number. The communication interface circuit includes a communication channel interface circuit corresponding to the communication channel on a one-to-one basis, and a transfer control circuit for controlling data transfer between the communication channel interface circuit and the buffer memory.
The communication channel interface circuit includes a reception address counter and a transmission address counter that generate an access address for the buffer memory, a temporary reception buffer that holds communication data for each address count value by the reception address counter, and the transmission A temporary transmission buffer for holding transmission data for each address count value by the trusted address counter,
The transfer control circuit writes data from the temporary reception buffer to the corresponding communication channel buffer based on the value of the reception address counter, and from the corresponding communication channel buffer based on the value of the transmission address counter. Controls the reading of data to the temporary transmission buffer, compares the received data received in the temporary reception buffer with the data to be compared, and transitions to the operation of writing the received data to the communication channel buffer area according to the comparison result The semiconductor device according to claim 1, wherein the transition result of the write operation can be referred to the CPU. The control register circuit includes a compare data register in which comparison target data to be compared with reception data is set, and a compare in which a memory address to which reception data is written is set according to a comparison result between the reception data and the comparison target data A plurality of point memory address registers and a branch condition setting register in which an operation mode for received data received in the temporary reception buffer is set according to the comparison result;
The semiconductor device according to claim 15, wherein the transfer control circuit has an extended reception mode in which required reception data is selected from reception data and stored in the buffer memory in accordance with setting values set in the plurality of sets of registers. .   The register circuit further requests an interrupt to the central processing unit when the transfer control circuit completes writing of received data to an address set in a predetermined compare point memory address register according to the setting of the branch condition setting register. The semiconductor device according to claim 16, further comprising an interrupt request logic. A direct memory access controller connected to the internal bus;
The register circuit further requests a data transfer request to the direct memory access controller when the transfer control circuit completes writing received data to an address set by a predetermined compare point memory address register according to the setting of the branch condition setting register. The semiconductor device according to claim 16, further comprising a data transfer request logic that outputs

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