JP2001265711A - Device for transferring data and bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of signal wiring and to provide flexible access control similar to a channel type. SOLUTION: An I/O bus 20 is a bus structure using both a channel type and a bus type and is composed of an I/O common bus commonly connected to I/O devices 21-23 and a channel interface signal line independently provided for each I/O device. Each of channel interface signal lines contains a clock SCLK and data transfer between each of I/O devices and a bus arbitrator 15 is executed synchronously with the clock SCLK outputted from the side of transmitting. The I/O common bus is provided with the CAD bus of 8-bit width for transmitting a command, an address and data in time-division manner and a signal for distinguishing whether the output onto the CAD bus is the command or data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer device and a bus system, and more particularly to a data transfer device and a bus system used for a portable information terminal or the like.

[0002]

2. Description of the Related Art Conventionally, as a bus structure for an I / O device used in a portable information terminal or the like, (1) a bus type,
(2) Two types of channel type are known.

The bus type has a structure in which a plurality of I / O devices are connected by a common bus. In addition to an address bus, a data bus, and a clock signal line, a plurality of I / O devices are used.
Shared between devices. For this reason, the number of signal wirings can be reduced, but since each signal is shared between devices, wiring measures to improve the instability of the signal waveform due to this are indispensable, and frequency improvement and power consumption reduction are required. It is disadvantageous in point.

On the other hand, the channel type has a structure in which an address bus, a data bus, a clock signal line, and the like are independently provided for each I / O device. Flexible access control can be performed for each I / O device, and noise reduction is simpler than that of a bus type, so that the performance is easily improved. However, on the other hand, there is a problem that the number of signal wirings increases.

[0005]

In a small electronic device such as a portable information terminal, the mounting area of components is limited.
It is necessary to keep the number of signal wires as small as possible.
However, if a bus-type wiring structure as described above is used for this purpose, power consumption increases due to factors such as the need to constantly supply clocks to all devices. For this reason, even in the channel type wiring structure, a new bus structure is required to reduce the number of signal wirings.

As a method of reducing the number of signal lines on a bus, a method of outputting addresses and data on the same bus in a time-division manner is known. However, conventionally, the output order of the address and the data and the output timing thereof are determined in advance, and it is necessary to always access at that timing. For this reason, there is a problem that a malfunction occurs when a sequence shift or the like due to noise occurs. Further, since it is required that the address phase and the data phase are always continuous, an address phase and a data phase for accessing a certain I / O device are divided, and another I / O device is interposed therebetween. It has been difficult to control access to the I / O device or to accept an access request from another I / O device.

The present invention has been made in view of such circumstances, and realizes a new bus structure capable of reducing the number of signal wirings and realizing the same flexible access control as the channel type. Accordingly, an object of the present invention is to provide a data transfer device and a bus system suitable for a small electronic device such as a portable information terminal requiring a small size and low power consumption.

[0008]

SUMMARY OF THE INVENTION The present invention is a data transfer apparatus for transferring data between a bus arbitrator and a plurality of I / O devices, wherein each of the I / O devices has a bus ownership. The bus arbitrator is provided with grant means for granting ownership of the bus, and the bus arbitrator and each of the I / O devices are provided with a command, an address and a data. Means for outputting the same on the same bus, means for transmitting a clock to the other party when transferring data using the bus,
Means for receiving data transferred from the other party by receiving a clock from the other party, and distinguishing whether the command, address, and data are output to the same bus when the command, address, and data are output to the same bus. Means for outputting a signal.

This data transfer device employs a configuration in which a command, an address, and data are output on the same bus, and is provided on a bus used for data transfer between a bus arbitrator and a plurality of I / O devices. , Commands, addresses and data are transmitted in a time-division manner. In this case, whether a command or data is output to the bus is specified by outputting a dedicated signal for distinguishing the command or data from the transfer source.

[0010] Therefore, normal data transfer can be performed without transferring commands and data at predetermined timings as in the related art, so that resistance to a sequence shift due to noise can be improved. . Further, since it is not always necessary to execute the address phase and the data phase consecutively, the address phase and the data phase for accessing a certain I / O device are divided, and during that time, the communication with another I / O device is performed. It is also possible to execute data transfer between them.

Further, by outputting a signal for distinguishing between command and data from the I / O device,
Since it is possible to explicitly notify the bus arbitrator whether the data output from the O device to the bus is a command or data, the I / O device issues a command autonomously to Transfer can also be performed. In particular, the present data transfer device uses a channel-type configuration in which the receiving side receives data in synchronization with a clock from the transfer source in combination with a bus-type configuration in which commands, addresses, and data are output on the same bus. Whether the data transfer from the I / O device is caused by a data read to the I / O device,
Since a mechanism for determining whether the command is based on an autonomous command from the I / O device is required, a configuration is used in which the signal is notified from the I / O device to the bus arbitrator by a dedicated signal. Thereby, more flexible access control is realized.

In addition to the above configuration, when the bus arbitrator and each of the I / O devices receive a command, address, and data from a partner via the same bus, the bus arbitrator and the I / O device can be fixed. It is preferable to further provide a means for notifying the other party of the receiving state of the receiving side at the set timing.

In this manner, by fixing the timing of notifying the receiving state of the receiving side to the other party, it is not necessary to issue a clock for latching the receiving state, and the number of terminals can be reduced. In this case, the receiving state is notified from the receiving side in synchronization with the clock from the transmitting side. Therefore, the circuit for determining the receiving state (acknowledgement, retry request, error) is synchronized with the transmitting circuit. It becomes possible to design, and the circuit can be simplified. In addition, in the data phase, by specifying that the reception state is notified in the first cycle, it is possible to prepare for retry or the like at an early stage.

Further, according to the present invention, in the data transfer device according to the above-mentioned claim 1, the release timing of a bus used for transferring the command, the address and the data is fixed, and the bus arbitrator is fixed. It is characterized in that the ownership of the bus is controlled at the bus release timing.

In this configuration, when another bus right is requested, the release timing is determined, so that the bus can be switched at a high speed. In particular, multiple I
In the case of sequentially accessing while switching the / O device, the bus arbitrator can determine the occurrence of the switching before the actual switching timing, so that the loss due to the bus right switching is minimized. Thus, data transfer between a plurality of I / O devices can be efficiently performed while switching the I / O devices.

Further, in addition to the configuration of the above-mentioned claim 1, the command is provided with an address extension bit indicating whether or not the extension of an address bit length follows, so that the bus arbitrator and each of the I / O devices are provided. , It is preferable that an address bit length following the command is determined by the address extension bit. As a result, in general, high-speed access is performed in a short cycle of address bits, and when a large memory space is handled, control is performed to expand the memory space by expanding the address bit length using address expansion bits. It becomes possible.
Therefore, it is possible to flexibly respond to the system configuration.

Further, in addition to the configuration of the above-described claim 1, the bus arbitrator and each of the I / O devices have a first data transfer mode for executing a continuous data transfer while incrementing an address. It is preferable that a means is further provided for designating, by the command, which data transfer mode to use, the second data transfer mode for executing continuous data transfer without incrementing the address.

Thus, in addition to the normal burst transfer in which data is transferred while incrementing the address, continuous data transfer with the same address to a buffer such as a FIFO can be performed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of an information processing apparatus using a bus system according to an embodiment of the present invention. This information processing apparatus is used as a portable information terminal or the like, and as shown in FIG.
RAM 12, ROM 13, gate array (Gate A)
(rray) 14, and a plurality of I / O devices 21 to 2
3 is provided.

The I / O devices 21 to 23 are various peripheral devices such as a floppy (registered trademark) disk drive (FDD), a hard disk drive (HDD), an audio device, a digital camera, and a communication controller.

Gate Array 1
4 is a memory bus 10 on the host side and an I / O device 21
23 to the I / O bus 20 on the side of
I / O device 2 in response to an access request from PU 11
Access control is performed on the memory devices 1 to 23 or memory access is performed in response to a memory access request from the I / O devices 21 to 23. The gate array 14 incorporates, as peripheral devices, for example, a display drive circuit for driving a liquid crystal display device (not shown), and I / O devices 21 to 23.
Bus arbitrator (B
us Arbitrator) circuit 15.

As shown, the host-side memory bus 10 includes a 32-bit data bus, a 26-bit address bus, and control signals. The control signals include a chip select signal CS, a read signal Read, and three write signals Write. The Write signals indicate 1-byte write, 2-byte write, and 4-byte write, respectively.

The CPU 11 issues a memory address using the memory bus 10 so that the RAM 12 and the ROM 1
Access 3 The CPU 11 has I / O devices 21 to
23 is also accessed by issuing a memory address using the memory bus 10. That is, the CPU 11
In view of this, the hardware configuration is such that all the I / O devices 21 to 23 are developed on a memory map,
The / O device is used as a memory mapped I / O.

An I / O device to which the I / O devices 21 to 23 are connected
The I / O bus 20 has a bus structure using both the channel type and the bus type described above, and is provided independently for each I / O device and an I / O common bus commonly connected to the I / O devices 21 to 23. Channel interface signal line. The data transfer width of the memory bus 10 is 32 bits, while the data transfer width of the I / O common bus is 8 bits. That is, the I / O common bus has an 8-bit width CAD in which commands, addresses, and data are transmitted in a time-division manner.
A bus is included, and data transfer to and from each I / O device is performed via a CAD bus.

Therefore, when transferring data between the CPU 11 and each I / O device, a 26-bit width address and a 32-bit width parallel data are each divided into 8-bit units, which are serially converted into I / O devices. Parallel / serial conversion processing to transfer to the device side, or I /
A serial / parallel conversion process is performed in which addresses and data serially transferred in 8-bit data units from the O device side are collected into a 32-bit width and transferred to the memory bus 10 side.

Bus Arbitrator (Bus Arbitrator)
(Rator) circuit 15 is provided with three channels of channels 1 to 3. Each channel is connected to a corresponding I / O device via a channel interface signal line.

The bus arbitrator circuit 15 and each I /
FIG. 2 shows the terminal specifications of the O device. That is, there are thirteen IO common buses and eight CAD signal lines CAD [7:
0], one command / address status signal line C
A, two acknowledge signal lines ACK [1: 0], one OFF signal line OFFB, one reset signal line RES
It is composed of ETB.

Command / address status signal CA
Is a signal for distinguishing whether a command or data currently output on the CAD is a command or data. While the command or address is being output, the status signal CA is set to the active state "H" by the output side (master). During the period during which data is output, status signal CA is set to the inactive state "L".

The acknowledge signal ACK [1: 0] is a response signal indicating the receiving state of the command (address) or data receiving side (slave), and ACK = "01" indicates that the command, address or data cycle has been completed normally. (Acknowledgment), and ACK = "10" indicates a retransmission request (Retry) of a command, address or data cycle. In which cycle the acknowledgment signal ACK [1: 0] is output is fixed for each of the address phase and the data phase.

The OFF signal line OFFB and the reset signal line RESETB are connected to the bus arbitrator circuit 1 respectively.
5 to the I / O device side.
Shows O device off and reset.

Each channel interface signal line is provided with one source synchronous clock signal SCLK, one interrupt signal INTB, one bus request signal BREQ, and one bus permission signal BGNT.

The source synchronous clock signal SCLK is a transfer synchronous clock for outputting a command, an address, or data, and is a data (command, command,
Address, data). The source synchronous clock signal SCLK is output from the master side. Data reception by the slave on the receiving side is started by the source synchronous clock signal SCLK from the master side, and receives a command, address or data in synchronization with the source synchronous clock signal SCLK.

The bus use right request signal BREQ is a signal for requesting the bus arbitrator circuit 15 to use the IO common bus, and is issued from the I / O device to the bus arbitrator circuit 15. The bus arbitrator circuit 15 arbitrates a bus use request signal BREQ from each of the I / O devices 21 to 23, and sends a bus use permission signal BG to the I / O device to which the bus use right should be given.
Issue NT. Each of the bus use right request signal BREQ and the bus use right permission signal BGNT is a signal of negative logic.

Therefore, the bus arbitrator circuit 15 has 1
3+ (3 × 4) = 25, 13+ for each I / O device
4 = 17 terminals.

Data exchange always occurs between the bus arbitrator circuit 15 and the I / O devices 21 to 23 in two relations of a master and a slave, and transfer is performed after the output side of transfer data secures the bus right. The data transfer is performed by controlling the clock SCLK. Each I / O device has a bus request (BREQ) circuit, and only an I / O device that has been granted permission from the bus arbitrator circuit 15 can output data.

<Commands and Addresses> Next, with reference to FIGS. 3 to 5, commands and addresses transferred via CAD [7: 0] having an 8-bit width will be described.

In the bus system of this embodiment, a three-clock instruction as shown in FIG. 3A and a four-clock instruction as shown in FIG. 3B are prepared. The 3-clock instruction is an 8-bit command followed by the addresses (A [15: 8], A [7:
0]). Normally, the 3-clock instruction is used, and a memory address space represented by the 3-clock instruction is to be accessed. The 4-clock instruction is an instruction used when the memory address space is extended and used. An 8-bit command is followed by an address (A [23:16], A [23:16], A) transferred three times thereafter.
[15: 8], A [7: 0]).

Whether to use the 3-clock instruction or the 4-clock instruction is specified by an extension bit defined in an 8-bit command. FIG. 4 shows the structure of an 8-bit command.

The four bits CAD [6] to CAD [3] are used in a command part (C) for designating the type of data transfer.
M [3] to CM [0]). CM [3]-CM
FIG. 5 shows an example of the relationship between the combination of [0] and the command content. When performing continuous data transfer of 2 bytes or more, usually, the address is automatically incremented by +1 every time 1 byte is read / written on the command receiving side. However, in this embodiment, the address of 2 bytes or more is continuously incremented without address increment. Instructions for performing data transfer are also provided. Further, it is possible to instruct the stop of the data transfer being executed by using the CMs [3] to CM [0].

CAD [2] indicates the type of read / write access. CAD [2] = "0" indicates read access, and CAD [2] = "1" indicates write access.

CAD [1] is an address extension bit indicating whether or not the address is extended, that is, whether the current command and address are a 3-clock instruction or a 4-clock instruction. CAD [1] = "0" indicates a 3-clock instruction, and CAD [1] = "1" indicates a 4-clock instruction.

CAD [0] is for designating the first bit of the address following the command, and is used as A [16] for a 3-clock instruction and as A [24] for a 4-clock instruction. Therefore, in practice, an 8-bit command also includes address information.

<Circuit Configuration> Next, a specific circuit configuration of the transfer circuit unit used in the present bus system will be described with reference to FIG. Since the bus interfaces of the I / O devices 21 to 23 are all the same, in FIG.
The O device 21 is shown as a representative. Also, of the channel interface signal lines, the interrupt signal is omitted.

The bus arbitrator circuit 15 has a function of controlling data transfer with an I / O device in addition to the function of bus arbitration. That is, the bus arbitrator circuit 15 includes a FIFO buffer 151 and a command / address / data synthesizing circuit (CAD
Combining circuit) 152, transfer control circuit 153, and DMA
A circuit 154 is provided.

The FIFO buffer 151 is connected to the memory bus 10
Buffer for interfacing with the control signal, address and data from the memory bus 10 and commands from the CAD bus for realizing the above-mentioned parallel / serial conversion and serial / parallel conversion. , Addresses and data.
For example, when the CPU 11 performs a write access to an I / O device, an address, data, and a WRITE signal are held in the FIFO buffer 151.

The CAD synthesizing circuit 152 is for converting the access data held in the FIFO buffer 151 into 8-bit serial data so as to be loaded on a CAD bus. The CAD synthesizing circuit 152 and the FIFO buffer 151 perform the above-described operation. The interface for parallel / serial conversion is configured. When the CPU 11 performs write access to 32-bit data to the I / O device, the CAD synthesizing circuit 152 generates the above-described 3-clock or 4-clock command (CA) based on the WRITE signal and the address, and generates the 32-bit data. 8 width data
It is divided for each bit and converted into 3-byte serial data of D0 to D3.

The transfer control circuit 153 controls actual data transfer between each I / O device. The transfer control circuit 153 includes a bus grant (BGNT) as shown in FIG.
A circuit 201, a clock generation circuit 202, a CAD transfer circuit 203, a command interpretation circuit 204, and an error checker 205 are provided.

The bus grant (BGNT) circuit 201
Bus use right request signals BREQ1 to BREQ3 and bus use right permission signal B for connecting each of the I / O devices 21 to 23 and the bus grant (BGNT) circuit 201 on a one-to-one basis.
GNT1 to GNT1 to GNT3, and the bus use right request signal BREQ1 to 3 and the bus use right permission signal BGNT1.
Arbitration of the right to use the I / O common bus using
As for the bus release timing of the I / O common bus, in which cycle the command / address phase and data phase are released is fixed, and if there is another bus use right request signal BREQ, the bus is released at that timing. A right switch is performed.

The clock generation circuit 202 generates the above-mentioned source synchronous clock signal SCLK at the time of data output.
It is also used as an operation clock of the transfer circuit 203. The frequency of the source synchronous clock signal SCLK is
It can be variably set according to the transfer processing speed of the O device. In addition, the clock generation circuit 202 internally has a switching circuit for supplying the source synchronous clock signal SCLK received from the I / O device to the CAD transfer circuit 202 and the error checker 205 as a data capture clock during reception.

The CAD transfer circuit 203 is for performing data transfer with an I / O device via a CAD bus, and has the above-described command / address status signal CA.
It also has a transmission / reception interface. When outputting a command and an address on the CAD bus, the CAD transfer circuit 203 sets the status signal CA to "H" level.

The command interpreting circuit 204 interprets the command from the I / O device, and sets parameters for causing the DMA circuit 154 to execute the DMA transfer according to the result. As a result, a memory read / memory write request from the I / O device is processed by DMA transfer.

The error checker 205 receives an acknowledgment signal ACK returned from the I / O device at a fixed timing.
Received, and the reception state of the I / O device is determined accordingly. When the retry request is returned, the retry is instructed to the CAD transfer circuit 203.

As shown, each I / O device includes a bus request (BREQ) circuit 301, a clock generation circuit 302, a CAD transfer circuit 303, and a command interpretation circuit 30.
4. Error checker 305, FIFO buffer 306,
A data read / write control circuit 307, a register group 308, and a DMA controller (DMAC) 309 are provided.

A bus request (BREQ) circuit 301 requests a bus grant (BGNT) circuit 201 of the bus arbitrator circuit 15 using a bus use right request signal BREQ, and a bus use permission signal. B
When receiving the GNT, the data output by the CAD transfer circuit 303 is permitted.

The clock generation circuit 302, the CAD transfer circuit 303, the command interpretation circuit 304, and the error checker 305 respectively include the clock generation circuit 202, the CAD transfer circuit 203, the command interpretation circuit 204, and the error checker of the bus arbitrator circuit 15. It has the same function as 205. However, the clock generation circuit 302 does not require a clock frequency variable function as in the bus arbitrator circuit 15.

The data read / write control circuit 307 reads / writes the register group 308 in response to an access request from the bus arbitrator circuit 15. The read / write data is exchanged with the CAD transfer circuit 303 via the FIFO buffer 306. FIFO buffer 3
06 outputs a signal indicating the empty state of the register,
If it is full, the error checker 205 returns a retry signal. If there is no problem, return a positive response. If no data is received, there is no response.

A DMA controller (DMAC) 309 is for operating an I / O device as a bus master. When a start address and the number of transfer bytes are set, a command and an address corresponding thereto are output from the CAD transfer circuit 303. Is done.

Next, a specific operation of the present bus system will be described.

<Case where CPU Writes Data to I / O Device> First, referring to FIG. 7 and FIG.
A case where 32-bit data is written from 1 to the I / O device 21 will be described.

In this case, the CPU 11 sends the “4-byte write signal”, “address (25 bits)” and “data (3
2 bits) "on the memory bus 10. These data are input and stored in the FIFO buffer 151 of the bus arbitrator circuit 15.

Command / address / data synthesizing circuit (C
The AD synthesizing circuit 152 fetches data from the FIFO buffer 151, and issues a command / address (CA) and data D0 such as to be loaded on the bus system of the present embodiment.
-Convert to D3.

Here, CA is a command + address, and the command is 4 byte transfer + write + 4 clock command + A [24] The address is A [23:16], A [15: 8], A
[7: 0] The data is D0 + D1 + D2 + D3 (8 bits × 4 = 3
2 bits).

These data pass through the CAD bus, and
The data is written to the O device 21. The data transfer control operation at this time is as follows.

(1) The bus arbitrator 15 secures the bus right and becomes the master (Bus Owner). (2) The bus arbitrator 15 accesses the I / O to be accessed.
The SCLK 1 is output to the device 21 at a frequency corresponding to the transfer speed of the I / O device 21. (3) At the rise of SCLK1, the I / O device 21 recognizes that it has been selected and prepares to receive data. (4) The bus arbitrator 15 outputs a command, an address, and data to the CAD [7: 0] bus in order in synchronization with the rising edge of SCLK. In the command / address phase in which the command and the address are output, the bus arbitrator 15 sets the above-mentioned command / address status signal CA to "H".

(5) The I / O device 21 reads CAD [7: O] in synchronization with the fall of SCLK1. Then, the command and the start address are interpreted to prepare for a write operation. (6) The I / O device 21 sets ACK [1:
0] signal (T in the case of a three clock instruction)
The state is output to ACK [1: 0] at two timings). (7) Thereafter, the data of the designated transfer byte number is output from the bus arbitrator 15.

(8) The I / O device 21 receives the transfer data and writes it to the designated storage area. (9) In the data phase, the I / O device 21 outputs a state to the ACK [1: 0] terminal at the leading Tl timing. If there is a Retry request, the transfer side, that is, the bus arbitrator 15 determines that the transfer in that cycle (4 or 3 clocks) has failed, and transfers again (FIG. 8). (10) The data transfer ends with the clock stopped.

The reason why the ACK timing is D0 (= T1) in the data phase is that it is possible to immediately determine whether or not data can be received by checking whether there is a free space in the FIFO, so that it can be issued at the timing of D0. However, in the case of a command, since it must be interpreted as a command, it cannot be issued at the first clock.

<Case where CPU Reads Data from I / O Device> Next, referring to FIG.
A case where 8-byte data is read from the / O device 21 will be described.

In this case, the CPU 11 generates a read signal and an address on the memory bus 10. Upon receiving the read signal, the FIFO buffer 151 of the bus arbitrator circuit 15 waits until the I / O is ready.
issue it. Then, a read command and an address are transferred from the bus arbitrator circuit 15 to the I / O device 21, and the reading of data by the I / O device 21 is started. The data transfer control operation at this time is as follows.

(1) The bus arbitrator 15 sends the SCLK 1 to the I / O device 21 to be accessed
Output at a frequency that matches the transfer speed of the / O device. (2) At the rise of SCLK1, the I / O device 21 recognizes that it has been selected and prepares to receive data. (3) The bus arbitrator 15 issues a read command to the CAD [7: 0] bus in synchronization with the rise of SCLK1,
Output in address order. In the command / address phase in which the command and the address are output, the bus arbitrator 15 sets the above-mentioned command / address status signal CA to "H".

(4) The I / O device 21 reads CAD [7: O] in synchronization with the falling edge of SCLK. Then, the command and the start address are interpreted to prepare for the read operation. (5) The bus arbitrator 15 waits for an output from the I / O device 21 in the data transfer so far. (6) Thereafter, the I / O device 21 outputs BREQ1 to the bus arbitrator 15 to request a bus right. (7) The bus arbitrator 15 determines the priority of the bus request, and issues BGNT1 to the I / O device 21 to give the bus right.

(8) After securing the bus right, the I / O device 21 outputs SCLK1 at a frequency corresponding to the transfer speed of the I / O device 21. (9) The I / O device 21 sequentially outputs the data of the transfer byte number designated to the CAD bus in byte units in synchronization with the rise of SCLK1. (10) When the specified number of transfers are completed, the I / O device 21 makes BREQ1 inactive, and the bus arbitrator 15 receives it and makes BGNT1 inactive.

<DMA Transfer by Read Request from I / O> Next, with reference to FIG. 10, an operation when DMA transfer is executed by a read request from the I / O device 21 will be described.

(1) The I / O device 21 issues BREQ1 and requests a bus right. (2) The bus arbitrator 15 issues BGNT1 to give the I / O device 21 a bus right. (3) The I / O device 21 converts the SCLK1 into its I / O
The read command and the head address are sequentially output on the CAD bus in synchronization with SCLK1 at a frequency corresponding to the transfer speed of the device. In the command / address phase in which the command and the address are output, the I / O device 21 sets the above-described command / address status signal CA to “H”.

(4) Since the signal CA is "H", the bus arbitrator 15 outputs the signal C in synchronization with the fall of SCLK1.
AD [7: O] is a command from the I / O device 21 /
Read as address. Then, the command and the start address are interpreted to prepare for DMA transfer. (5) The I / O device 21 waits for an output from the bus arbitrator 15 in the data transfer so far, and
1 is made inactive to release the bus.

(6) After that, the bus arbitrator 15 acquires the bus right and sends the SCLK to the I / O device 21.
Outputs 1. Then, the data of the transfer byte number designated to the CAD bus is sequentially output in byte units.

<DMA Transfer by Write Request from I / O> Referring to FIG. 11, an operation when DMA transfer is executed by a write request from I / O device 21 will be described.

(1) The I / O device 21 issues BREQ1 and requests a bus right. (2) The bus arbitrator 15 issues BGNT1 to give the I / O device 21 a bus right. (3) The I / O device 21 converts the SCLK1 into its I / O
The output is performed at a frequency corresponding to the transfer speed of the device, and the write command and the head address are sequentially output on the CAD bus in synchronization with SCLK1. In the command / address phase in which the command and the address are output, the I / O device 21 sets the above-described command / address status signal CA to “H”. (4) Since the signal CA is "H", the bus arbitrator 1
5 is synchronized with the falling edge of SCLK1 and CAD [7:
O] as a command / address. Then, the command and the start address are interpreted to prepare for DMA transfer. During this preparation, the right to use the bus is temporarily released from the I / O device 21.

(5) The I / O device 21 issues BREQ1 and requests a bus right. (6) When the preparation for the DMA transfer is completed, the bus arbitrator 15 issues BGNT1 to give the I / O device 21 a bus right. (7) The I / O device 21 outputs SCLK1 at a frequency corresponding to the transfer speed of the I / O device. (8) The I / O device 21 sequentially outputs the data of the transfer byte number designated to the CAD bus in byte units in synchronization with the rise of SCLK.

<Intermediate Stop of Data Transfer> Next, with reference to FIG. 12, an example of a case where the CPU 11 writes data to the I / O device 21 will be described with reference to FIG.

(1) The bus arbitrator 15 outputs SCLK1 to the I / O device 21 at a frequency corresponding to the transfer speed of the I / O device. (2) The bus arbitrator 15 outputs an 8-byte write command, address, and data in this order to the CAD [7: 0] bus in synchronization with the rise of SCLK1. In the command / address phase in which the command and the address are output, the bus arbitrator 15 sets the above-mentioned command / address status signal CA to "H".

(3) When the transfer is interrupted for some reason, the bus arbitrator 15 sets the command / address status signal CA to "H" and issues a new command or issues a stop command to the I / O. Issue to device. As a result, the ongoing data transfer can be stopped halfway.

<Switching of Data Transfer 1> Next, FIG.
The case where the bus cycle is switched to the data read operation from the I / O device 22 during the transfer of the write data to the I / O device 21 will be described with reference to FIG. Here, it is assumed that a read command is received by the I / O device 22 in advance, and a write access to the I / O device 21 is started prior to transfer of read data from the I / O device 22 to the read command. .

(1) The bus arbitrator 15 sends the SCLK 1 to the I / O device 21
1 is output at a frequency corresponding to the transfer speed. (2) The bus arbitrator 15 outputs a command, an address, and data to the CAD [7: 0] bus in synchronization with the rising edge of SCLK1. (3) When the BREQ2 from the I / O device 22 becomes active during the data transfer to the I / O device 21, the bus arbitrator 15 adjusts the timing to the predetermined bus release timing (here, the end of D3). BG
NT2 is output to give the I / O device 22 the right to use the bus. At the same time, the output of SCLK1 stops, and the transfer of write data to the I / O device 21 stops.

(4) The I / O device 22 outputs SCLK2 at a frequency corresponding to the transfer speed of the I / O device 22. (5) The I / O device 22 starts to sequentially output the data of the number of transfer bytes designated to the CAD bus in byte units in synchronization with the rise of SCLK2. (6) The bus arbitrator 15 inactivates the BGNT2 at a predetermined bus release timing to release the bus, and acquires the right to use the bus again. Then, SCLK1 is output and the I / O device 21
Initiate the rest of the data transfer to. By repeating the above, the transfer is completed.

<Switching of Data Transfer 2> Next, FIG.
The case where the bus cycle is switched to the data read operation from the I / O device 22 during the transfer of the read data from the I / O device 21 will be described with reference to FIG. Here, it is assumed that a read command is received by the I / O device 22 in advance, and a read access from the I / O device 21 is started prior to transfer of read data from the I / O device 22 to the read command. .

(1) After securing the bus right, the I / O device 21 outputs SCLK1 at a frequency corresponding to the transfer speed of the I / O device 21. (2) The I / O device 21 starts to sequentially output the data of the transfer byte number designated to the CAD bus in byte units in synchronization with the rise of SCLK1.

(3) If the BREQ2 from the I / O device 22 becomes active during the data transfer from the I / O device 21, the bus arbitrator 15 sets a predetermined bus release timing (here, the end time of D7). )
BGNT1 is made inactive according to
Activate 2

(4) When the I / O device 22 acquires the bus right, it outputs SCLK2 at a frequency corresponding to the transfer speed of the I / O device 22. (5) The I / O device 22 starts to sequentially output the data of the number of transfer bytes designated to the CAD bus in byte units in synchronization with the rise of SCLK2. (6) I / O during data transfer from I / O device 22
When BREQ1 from the device 21 becomes active,
The bus arbitrator 15 outputs the B signal in accordance with a predetermined bus release timing (here, at the end of D3).
GNT2 is made inactive and BGNT1 is made active. (7) The I / O device 21 outputs SCLK1 and starts the remaining data transfer. By repeating the above, the transfer is completed.

As described above, in the present embodiment, A. By adopting a bus structure of a combined channel / bus type and adding a signal CA for distinguishing between a command / address and data, A-1) For example, a DMA transfer by a read request from the I / O in FIG. 10 will be described. As we did, bus arbitrator 1
5 as well as autonomous requests (DMA requests) from I / O.

A-2) As described in FIG. 12, when the transfer is interrupted for some reason on the bus arbitrator 15 side during the data transfer, the CA signal is activated. The I / O side can recognize that it is not a data transfer, and the latest sequence can be stopped by a new command, or can be stopped halfway by a stop command.

A-3) For example, as described in the write operation to I / O in FIG. 7, Command / Addr
Since it is possible to recognize that the phase is the ess phase, the sequence can be rebuilt even if something goes wrong during the sequence.

B. Further, for example, as described in the retry operation of FIG. 8, by fixing the timing of returning the ACK, B-1) it is not necessary to issue a clock for latching the ACK, thereby reducing the number of pins.

B-2) The ACK generation timing uses the clock on the transmission side, so that the ACK response content (Ackno
(Wedge, Retry, Error) can be designed synchronously, so that the circuit can be simplified.

B-3) In particular, by setting the ACK response timing in the Data phase to the top, the ACK receiving side can obtain a response to the data transfer at an early stage, so that it is easy to respond and the circuit can be simplified as a result. it can.

C. For example, as described with reference to the switching of the I / O lead in FIG.
The mand / Address phase is fixed at the third or fourth cycle, and the Data phase is fixed at the second or fourth cycle. C-1) There is no need to notify the timing at which the bus can be released, and the communication signal is deleted. be able to.

C-2) I / O 21 by immobilization
, The switching timing of the I / O 22 can be determined one clock or more before actually switching, so that the switching loss can be minimized.

D. In addition, by giving an address extension bit to a command, it is possible to normally access in a short cycle to realize high-speed operation, and to handle a large memory size, the memory area can be extended by using the extension bit.

E. Normally, when the number of data to be transferred is defined, the address is incremented by 1 on the I / O side, but the function of changing the number of data transfer with the same address has been added so that the same address such as FIFO can be continuously output. Can read and write data.

[0100]

As described in detail above, according to the present invention, a bus structure of a combined channel / bus type is adopted, and a command /
By adding a signal for distinguishing an address and data, the number of signal wirings can be reduced, and the same flexible access control as that of the channel type can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of an information processing apparatus using a bus system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a bus arbitrator and an I / O according to the embodiment;
The figure which shows the terminal specification of O device.

FIG. 3 is an exemplary view for explaining a 3-clock instruction and a 4-clock instruction used in the embodiment;

FIG. 4 is an exemplary view showing the structure of a command used in the embodiment.

FIG. 5 is an exemplary view showing types of data transfer that can be specified by a command used in the embodiment;

FIG. 6 is an exemplary block diagram showing a specific circuit configuration of a transfer circuit unit used in the embodiment;

FIG. 7 is a timing chart showing an operation when the CPU writes data to an I / O device in the embodiment.

FIG. 8 is a timing chart for explaining the timing of a retry request in the embodiment.

FIG. 9 is an exemplary timing chart showing an operation when the CPU reads data from an I / O device in the embodiment.

FIG. 10 is a timing chart showing an operation when data transfer is performed in response to a read request from an I / O device in the embodiment.

FIG. 11 is an exemplary timing chart showing an operation when data transfer is performed by a write request from an I / O device in the embodiment;

FIG. 12 is an exemplary timing chart showing an operation of stopping data transfer halfway in the embodiment;

FIG. 13 is a timing chart showing the switching operation of the I / O device in the embodiment.

FIG. 14 is a timing chart showing another example of the switching operation of the I / O device in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Memory bus 11 ... CPU 12 ... RAM 13 ... ROM 14 ... Gate array 15 ... Bus arbitrator circuit 20 ... I / O bus 21-23 ... I / O device 151 ... FIFO buffer 152 ... CAD synthesis circuit 153 ... Transfer Control circuit 154 DMA circuit 201 Bus grant (BGNT) 202 Clock generation circuit 203 CAD transfer circuit 204 Command interpretation circuit 205 Error checker 301 Bus request (BREQ) circuit 302 Clock generation circuit 303 CAD transfer circuit 304 Command interpreter circuit 305 Error checker 306 FIFO buffer 307 Data read / write control circuit 308 Register group 309 DMA controller (DMAC)

Claims (9)

[Claims] 1. A data transfer apparatus for transferring data between a bus arbitrator and a plurality of I / O devices, wherein each of the I / O devices is provided with request means for requesting ownership of a bus. The bus arbitrator is provided with grant means for granting ownership of the bus, and the bus arbitrator and each of the I / O devices output a command, an address and data on the same bus. Means for transmitting a clock to the other party when transferring data using the bus; means for receiving data transferred from the other party by receiving a clock from the other party; Means for outputting a signal for distinguishing whether a command or data is output to the bus when outputting to the bus. Transfer device. 2. The bus arbitrator and each of the I / Os
2. The device according to claim 1, further comprising means for notifying the receiving side of the receiving state at a fixed timing when the device receives a command, an address, and data from the other side via the same bus. A data transfer device according to claim 1. 3. A bus release timing used for transferring the command, the address, and the data is fixed, and the bus arbitrator controls distribution of ownership of the bus with the fixed bus release timing. The data transfer device according to claim 1, wherein 4. The command includes an address extension bit indicating whether or not the address bit length that follows is extended, and the bus arbitrator and each of the I / O devices are controlled by the address extension bit. 2. The data transfer device according to claim 1, wherein an address bit length following the command is determined. 5. The bus arbitrator and each of the I / Os
The device has a first data transfer mode for executing a continuous data transfer while incrementing an address, and a second data transfer mode for executing a continuous data transfer without incrementing the address. 2. The data transfer apparatus according to claim 1, further comprising means for designating which of the first and second data transfer modes is to be used. 6. The bus arbitrator according to claim 1, further comprising means for dividing an address and data sent from a CPU and converting the divided data into serial data to be put on a bus. 2. The data transfer device according to claim 1. 7. A bus through which commands, addresses, and data are transmitted in a time-division manner, a plurality of I / O devices connected to the bus, and each of the I / O devices connected to the bus.
A bus system having data transfer control means for executing data transfer with a device via the bus, wherein the bus indicates which of the command and the data is output on the bus. The data transfer control means and each of the I / O devices receive a clock signal transmitted from a partner via a clock signal line disposed therebetween, Means for starting reception of a command, address, or data transmitted from the transmission source of the clock signal via the bus; and outputting a command, address, or data on the bus in synchronization with the clock signal. Means for notifying to the other party whether the command or data being output to the bus is a command or data using the phase distinction signal line. A bus system characterized by the following. 8. A response signal line for notifying a receiving side of a command or data reception state on a receiving side to the other party is defined in the bus, and the drive timing of the response signal line is determined by a command on the bus. 8. The bus system according to claim 7, wherein each of a command phase in which is output and a data phase in which data is output on the bus are fixedly defined. 9. The data transfer control means according to claim 1, wherein:
A bus arbitration means for arbitrating bus ownership in response to a bus right request from the O device; the release timing of the bus is determined by a command phase in which a command is output on the bus and a data phase on the bus. Each of the output data phases is fixedly defined, and the bus arbitration unit executes release of each of the command phase and the data phase being executed at a fixed timing in response to a new bus right request. The bus system according to claim 7, wherein: