CN207764780U - printer core control system based on FPGA - Google Patents
printer core control system based on FPGA Download PDFInfo
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- CN207764780U CN207764780U CN201820203339.5U CN201820203339U CN207764780U CN 207764780 U CN207764780 U CN 207764780U CN 201820203339 U CN201820203339 U CN 201820203339U CN 207764780 U CN207764780 U CN 207764780U
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Abstract
The utility model belongs to movement control technology field more particularly to a kind of printer core control system.Printer core control system based on FPGA, including MCU units, MCU units connect print control interface by FPGA unit.Utility model is additionally arranged FPGA unit between MCU units and printer core, by the powerful interface resource of FPGA unit, can customize corresponding sequential and mating peripheral circuit according to different printer cores.And according to the difference of printer core, selective welding respective peripheral circuit and the demand for realizing the movement.FPGA unit can be compatible with most printer core, versatile, and develop simply, efficiently.
Description
Technical field
The utility model belongs to movement control technology field more particularly to a kind of printer core control system.
Background technology
Current printer core control platform mostly uses single MCU control unit.Different printer cores is due to its electric interfaces
It needs to develop different circuit control units with the difference of internal mechanical unit, although MCU can select same, it is most
Whole Control card is required for redesigning, without versatility.
In addition, FPGA technology is a kind of domestic low cost development technology, development language is unified, and development platform is less, exploitation
Engineering is versatile, facilitates the transplanting between system.
Utility model content
The utility model for MCU control unit in the prior art there is no the technical issues of versatility, and it is an object of the present invention to provide
A kind of printer core control system based on FPGA.
The printer core control system based on FPGA of the utility model, including MCU units, the MCU units pass through
FPGA unit connects print control interface；
Print data buffer process module, print command buffer process module are equipped in the FPGA unit, the MCU is mono-
Member provides CLK clock signals respectively, the CLK clock signals by PLL times of frequency module connect print data buffer process module,
Print command buffer process module；The print data buffer process module connects SSC interfaces by SSC buses, passes through data
Print control interface described in link connection, it is total that the print data buffer process module also connects EBI by data communication bus
Line interface, the MCU units connect the SSC buses by SSC interfaces respectively, connect the data by EBI bus interface
Communication bus, the MCU units provide clock and synchronizing signal by the SSC buses for the FPGA unit；The FPGA
Unit completes the reading of data, and is the LVDS data formats that printer core needs by SSC timing conversions；
The print command buffer process module connects EBI bus interface by command communication bus, passes through command link
The print control interface is connected, the MCU units pass through EBI bus interface bind command communication bus, the FPGA unit
The order data that the MCU units transmit is converted to the serial bus protocol of printer core identification, and configures printer core；Institute
It states FPGA unit and sends the information that the printer core transmits to the MCU unit resolves.
The utility model is additionally arranged FPGA unit between MCU units and printer core, powerful by FPGA unit
Interface resource can customize corresponding sequential and mating peripheral circuit according to different printer cores.And not according to printer core
Together, selective welding respective peripheral circuit and the demand of the movement is realized.FPGA unit can be compatible with most printer
Core, it is versatile, and develop simply, efficiently.
The print data buffer process module includes the frequency divider being connect with CLK clock signals, connects with the frequency divider
The multiple selector connect, the MCU units provide the CLK clock signals, and the EBI bus interface is selected by DPI frequencies
Register connects the multiple selector, and the multiple selector output sampling clock feeds back to the MCU units；In order to
MCU units configure DPI frequency mask registers by EBI bus interface, and multiple selector is according to DPI frequency mask registers
Configuration Values determine sampling clock of the output phase for resolution ratio.
The print data buffer process module further includes the sorting that lock-out pulse occurs module, connect with line locking signal
Isolation logic module, the print control interface provide the line locking signal, and the EBI bus interface is posted by lock-out pulse
Storage connects the lock-out pulse and module occurs, and the sorting isolation logic module connects the lock-out pulse and module, institute occurs
It states sampling clock and connects the lock-out pulse generation module, the lock-out pulse occurs module output line synchronizing signal and feeds back to institute
State MCU units.Print control interface provides line locking signal, this signal low level is effective, is always maintained under line effective status low
Level.Timesharing generates SSC enable signals after sorting isolation logic module detects line locking signal failing edge, and makes lock-out pulse
It is effective that module difference occurs.Lock-out pulse register is configured by system clock, removes configuration single pulse width and a line respectively
Pulse number forms line locking signal.
The lock-out pulse register includes that lock-out pulse starts register, lock-out pulse end register, lock-out pulse
Line length register.
The print data buffer process module further includes the LVDS conversion modules of print data signal connection, the MCU
Unit provides print data signal, and the LVDS conversion modules export LVDS signals to the print control interface.LVDS is converted
Module is responsible for the data-signal that MCU units input being converted to the printer core reading that LVDS formats are connected for print control interface
It takes.The utility model receives the data on the SSC interfaces from MCU units by FPGA unit, and is driven by special clock
Pattern is packaged into the printer core that every line number is sent to the connection of print control interface according to timesharing.Above structure realizes simple and effective
Data transmission.
The print command buffer process module includes the frequency divider being connect with CLK clock signals, connects with the frequency divider
The the first clock post-processing module connect, the first clock post-processing module generate connection second clock post-processing after logical timer
Module, the second clock post-processing module export synchronised clock to the print control interface；
The print command buffer process module further includes parallel serial conversion module, serioparallel exchange module, two-way separation module,
The order data of the MCU units output connects described pair after connecting the parallel serial conversion module by the EBI bus interface
Road separation module, the two-way separation module connect the print control interface by data line；The print control interface is anti-
After the feedback data of feedback connects the serioparallel exchange module by the two-way separation module, fed back by the EBI bus interface
To the MCU units.The FPGA unit of the utility model be responsible for the instruction for issuing MCU units, configuration information by and go here and there turn
Mold changing block is converted to the printer core that serial data is sent to the connection of print control interface.FPGA unit, which also receives, comes from printer
State, the error information of core, and MCU units are sent to by bus form by serioparallel exchange module.Above structure realizes
Simple and effective order data transmission.
The parallel serial conversion module includes buffer process module, the data being connect with buffer process module latch mould
The output end of block, the shift register enabled by the buffer process module displacement, the data latch module connects the shifting
The output end of bit register, the shift register connects the two-way separation module；
The EBI bus interface connects the buffer process module by writing the effective register of data, is posted by writing data
Storage connects the data latch module；
The logical timer is separately connected the buffer process module, the shift register.The MCU of the utility model is mono-
Member sets that write the effective register of data effective by EBI bus interface, and write data register director data is written, at caching
Reason module parsing, which is write the effective register of data and obtained, writes useful signal, and the data of write data register are passed through data latch module
Data are latched, and enabled shift register, parallel data is shifted by Serial output by logical timer, is sent by data line
To printer core.
The serioparallel exchange module includes buffer process module, the data being connect with buffer process module latch mould
Block, the shift register enabled by the buffer process module displacement, the parallel letter of the two-way separation module output end output
Number it is sequentially connected the shift register, the data latch module, multiplexer；The buffer process module it is another defeated
Outlet connects the multiplexer；The status register of one printer core connects the multiplexer；
The EBI bus interface connects the buffer process module by reading the effective register of data, is posted by reading data
Storage connects the multiplexer；
The logical timer is separately connected the buffer process module, the shift register.The printing of the utility model
When the state of movement, feedback information return, after process to be sent, MCU units are switched to reading mode.MCU units pass through EBI
Bus interface set read the effective register of data it is effective, and pass through buffer process module generate displacement the effective shift LD of enable signal
Device converts serial data into parallel data, and latch data is in data latch module.MCU units are set by EBI bus interface
Read data register passes through the status register and feedback data of multiplexer read printer core.
Further include Power Management Unit, the Power Management Unit output 5V power supplys and 3.3V power supplys, the 3.3V power supplys
Connect the logic power end of the FPGA unit；
The 3.3V power supplys connect core power ends after exporting 1.2V power supplys by power conversion chip；
The 5V power supplys connect the LDVS power ends of the FPGA unit after exporting 2.5V power supplys by power conversion chip.
Further include FPGA peripheral circuit, the FPGA peripheral circuit includes external crystal-controlled oscillation, described in the external crystal-controlled oscillation connection
The Clock Tree of FPGA unit.External crystal-controlled oscillation provides clock for FPGA unit.
The FPGA peripheral circuit includes E2ROM modules, and the E2ROM modules connect the BOOT drivings of the FPGA unit
Interface.E2ROM modules provide the load of BOOT programs for FPGA unit.
The FPGA peripheral circuit includes emulation interface, and the emulation interface connects the debugging driving mould of the FPGA unit
Block.Emulation interface provides serial debugging interface for FPGA unit.
The FPGA peripheral circuit includes reset circuit, the reset terminal of the reset circuit connection FPGA unit.Reset electricity
Road provides basic electrification reset delay for FPGA unit.
The positive effect of the utility model is：The printer core control system based on FPGA of the utility model is
Based on FPGA technology, corresponding sequential and mating peripheral circuit, user can be formulated according to different printer cores can realize difference
Transplanting between printer core platform.FPGA is based on its powerful interface resource, and flexibility is strong, and the development cycle is short, saves more
More human resources.
The technique effect of the design of the utility model, concrete structure and generation is made furtherly below with reference to attached drawing
It is bright, to be fully understood from the purpose of this utility model, feature and effect.
Description of the drawings
Fig. 1 is the system integrated circuit connection figure of the utility model；
Fig. 2 is the main circuit connection diagram of the utility model FPGA unit；
Fig. 3 is the circuit connection diagram of the utility model print data buffer process module；
Fig. 4 is the circuit connection diagram of the utility model print command buffer process module；
Fig. 5 is that the bus of the utility model writes sequence diagram；
Fig. 6 is that the bus of the utility model reads sequence diagram；
Fig. 7 is the line locking data time sequence figure of the utility model；
Fig. 8 is the order of the utility model, status information serial data sequence diagram.
Specific implementation mode
As shown in Figure 1, the printer core control system based on FPGA of the utility model, including MCU units, FPGA are mono-
Member, print control interface.MUC units can according to circumstances select cpu type, support basic expansion bus and SSC interfaces i.e.
It can be used in this system.The printer core of print control interface connection is responsible for, is configured to the MCU units of the utility model,
And receive reporting an error from printer core, prompt message；Real-time print data is sent by SSC interfaces.
The fpga chip EP2C8 of ALTERA companies may be used in FPGA unit.What FPGA unit was responsible for issuing MCU units
Instruction, configuration information are kept in, and are converted to serial data by parallel-serial conversion and are sent to printer core.FPGA unit receives
State, error information from printer core, and MCU units are sent to by bus form by serioparallel exchange；FPGA unit
The data on the SSC interfaces from MCU are also received, and every line number is packaged by special clock drive mode and is sent to according to timesharing
Printer core.
Further include Power Management Unit, Power Management Unit output 5V power supplys and 3.3V power supplys, 3.3V power supplys are divided into two-way,
The logic power end for connecting FPGA unit all the way is that whole system and FPGA logic cell are powered.Another way passes through DC-DC power source
Conversion chip connects core power ends after exporting 1.2V power supplys, powers for FPGA kernel units.5V power supplys pass through another DC-DC electricity
The LDVS power ends that FPGA unit is connected after the conversion chip output 2.5V power supplys of source, power for entire differential output circuit.
Further include FPGA peripheral circuit, FPGA peripheral circuit includes external crystal-controlled oscillation, E2ROM modules, emulation interface, resets electricity
Road.External crystal-controlled oscillation connects the Clock Tree of FPGA unit, and clock is provided for FPGA unit.E2ROM modules connect FPGA unit
BOOT driving interfaces provide the load of BOOT programs for FPGA unit.Emulation interface connects the debugging drive module of FPGA unit,
Serial debugging interface is provided for FPGA unit.Reset circuit connects the reset terminal of FPGA unit, is provided for FPGA unit basic
Electrification reset postpones.
With reference to Fig. 2, print data buffer process module, print command buffer process module are equipped in FPGA unit.Due to
The signal of FPGA unit and MCU units is asynchronous, therefore the print data buffer process module of the utility model is used for：MCU is mono-
Member provides clock and synchronizing signal by the pattern of bus configuration print data buffer process module, first choice for SSC buses, then
Complete the reading of a line number evidence, and the data format for the LVDS that SSC timing conversions are needed for printer core.It is specific as follows：
MCU units provide CLK clock signals respectively, and CLK clock signals connect print data by PLL times of frequency module and cache
Processing module, print command buffer process module.Print data buffer process module connects SSC interfaces by SSC buses, passes through
Data link connects print control interface, and print data buffer process module also connects EBI buses by data communication bus and connects
Mouthful, MCU units connect SSC buses by SSC interfaces respectively, connect data communication bus, MCU units by EBI bus interface
By the SSC buses clock and synchronizing signal are provided for FPGA unit；FPGA unit completes the reading of data, and when by SSC
Sequence is converted to the LVDS data formats of printer core needs.
It is program process when EBI bus interface is write with reference to Fig. 5, is program process when EBI bus interface is read with reference to Fig. 6.
With reference to Fig. 2, print command buffer process module is used for：MCU units pass through bus configuration print command caching process
The pattern of module, order data are converted to serial bus protocol that printer core can identify by the module and carry out configuration machine
Core；Printer core state, error information and inside modules status information are uploaded to MCU units by bus and are parsed.Tool
Body is as follows：
Print command buffer process module connects EBI bus interface by command communication bus, is connected by command link
Print control interface, MCU units are by EBI bus interface bind command communication bus, the life that FPGA unit transmits MCU units
It enables data be converted to the serial bus protocol of printer core identification, and configures printer core；FPGA unit transmits printer core
Information send MCU unit resolves to.
With reference to Fig. 3, in one embodiment, in the print data buffer process module of the utility model, system clock is logical
It crosses 16 frequency dividers and generates 1X, 2X, 4X, 8X frequency-dividing clock, correspond to respective DPI resolution ratio 600,300,200,100 respectively.Pass through and is
Bus of uniting (EBI bus interface) configures DPI frequency mask registers, passes through multichannel according to DPI frequency mask register Configuration Values
Selector determines that the output phase of sampling clock TK0, TK1 to(for) resolution ratio, concrete structure are as follows：
Print data buffer process module includes 16 frequency dividers being connect with CLK clock signals, it is more to be connect with frequency divider
Road selector, MCU units provide CLK clock signals, and EBI bus interface connects multi-path choice by DPI frequency mask registers
Device, multiple selector output sampling clock feed back to MCU units, in order to which MCU units configure DPI frequencies by EBI bus interface
Rate mask register, multiple selector determine the output phase adopting for resolution ratio according to the Configuration Values of DPI frequency mask registers
Sample clock.
With reference to Fig. 3 ,/BDO line locking signal low levels are effective, and low level is always maintained under line effective status.In a reality
It applies in example, in the print data buffer process module of the utility model, SSC sortings isolation logic module detects/BDO line lockings
Timesharing generates SSC enable signals after signal failing edge, and it is effective to make TF lock-out pulses that module difference occur.Matched by system clock
Set lock-out pulse TF start, terminate, line length register, remove a configuration TF single pulses width and line pulse number respectively, formed
One line locking signal TF0, TF1, concrete structure are as follows：
Print data buffer process module include TF0 lock-out pulses occur module, TF1 lock-out pulses occur module, with/
The SSC of BDO line locking signals connection sorts isolation logic module, print control interface offer/BDO line locking signals, EBI buses
Interface starts that register, lock-out pulse end register, that lock-out pulse line length register is separately connected TF0 is same by lock-out pulse
Module occurs for pace pulse, and TF1 lock-out pulses occur module and directly connect with EBI bus interface.Sort the connection of isolation logic module
SSC0 enable signals are issued into TF0 lock-out pulses generation module respectively, SSC1 enable signals are issued to TF1 lock-out pulses generation mould
Block.Sampling clock is separately connected TF0 lock-out pulses and module, TF1 lock-out pulses generation module occurs, and mould occurs for TF0 lock-out pulses
Block output TF0 line locking signals feed back to MCU units, and TF1 lock-out pulses occur module output TF1 line locking signals and feed back to
MCU units.
With reference to Fig. 3, in one embodiment, in the print data buffer process module of the utility model, LVDS moduluss of conversion
Block is responsible for TD0, TD1 data-signal of input being converted to LVDS formats, and concrete structure is as follows：
Print data buffer process module further includes the two LVDS conversions being connect respectively with TD0, TD1 print data signal
Module, MCU units provide TD0, TD1 print data signal, two LVDS conversion modules output/VD00 ,/VD01 signals to printing
Control interface.The utility model by FPGA unit receive the SSC interfaces from MCU units on data, and by it is special when
Clock drive mode is packaged into the printer core that every line number is sent to the connection of print control interface according to timesharing.Above structure realizes letter
Single effective data transmission.
It is line locking data time sequence process in print data buffer process module with reference to Fig. 7.
With reference to Fig. 4, in one embodiment, in the print command buffer process module of the utility model, system clock passes through 2
Road 16 frequency divider frequency dividing generates logical timer tclk by 1 road clock post-processing module, by 2 road clock post-processing module productions
The synchronised clock SCLK of raw print control interface, concrete structure are as follows：Print command buffer process module includes believing with CLK clocks
Number sequentially connected two 16 frequency dividers, the first clock post-processing module, the first clock post-processing module generate logical timer
Second clock post-processing module is connected after tclk, second clock post-processing module output synchronised clock SCLK to print control connects
Mouthful.
With reference to Fig. 4, in one embodiment, in the print command buffer process module of the utility model, system is to printing
Movement sends instruction process, sets that write the effective register of data effective by bus, and write data register director data is written, and leads to
It crosses parallel serial conversion module and logical timer tclk and 16 bit parallel datas is shifted into Serial output, printing is sent to by SC data lines
Movement.When the state of printer core, feedback information return, after process to be sent, system is switched to reading mode.Bus sets reading
The effective register of data is effective, and by serioparallel exchange module, converts serial data into 16 bit parallel datas.Bus sets reading
Feedback data is read according to register, concrete structure is as follows：
Print command buffer process module further includes parallel serial conversion module, serioparallel exchange module, two-way separation module, MCU
The order data of unit output connects two-way separation module, two-way separation after connecting parallel serial conversion module by EBI bus interface
Module connects print control interface by SC data lines.The feedback data of print control interface feedback is connected by two-way separation module
After connecing serioparallel exchange module, MCU units are fed back to by EBI bus interface.
With reference to Fig. 4, in one embodiment, in the parallel serial conversion module of the utility model, buffer process module parsing is write
The effective register of data, which obtains, writes useful signal, and the data of write data register are latched BUFFER by data and lock data
It deposits, and enabled shift register, 16 bit parallel datas is shifted by Serial output by logical timer tclk, are sent out by SC data lines
Printer core is given, concrete structure is as follows：
Parallel serial conversion module includes buffer process module, is connect with buffer process module data latch module is cached
The output end of the enabled shift register of processing module displacement, data latch module connects shift register, shift register
Output end connects two-way separation module.EBI bus interface by writing the effective register Connection Cache processing module of data, by writing
Data register connects data latch module.Logical timer is separately connected buffer process module, shift register.
With reference to Fig. 4, in one embodiment, in the serioparallel exchange module of the utility model, buffer process module generates shifting
Position enable signal acts on shift register, and latch sets data latch BUFFER and 16 data are latched into BUFFER, bus
Set status register and feedback data of the read data register by multiplexer read printer core.Concrete structure is as follows：
Serioparallel exchange module includes buffer process module, is connect with buffer process module data latch module is cached
The parallel signal of the enabled shift register of processing module displacement, the output of two-way separation module output end is sequentially connected shift LD
Device, data latch module, multiplexer.Another output end of buffer process module, i.e. data select end connection multiplexing
Device.The status register of printer core connects multiplexer.EBI bus interface is by reading the effective register Connection Cache of data
Processing module connects multiplexer by read data register.Logical timer tclk is separately connected buffer process module, displacement
Register.
With reference to Fig. 8, under the synchronous effect of synchronised clock SCLK, printer core is sent serial data by SC data lines
To the when program process of FPGA unit.
The utility model is additionally arranged FPGA unit between MCU units and printer core, powerful by FPGA unit
Interface resource can customize corresponding sequential and mating peripheral circuit according to different printer cores.And not according to printer core
Together, selective welding respective peripheral circuit and the demand of the movement is realized.FPGA unit can be compatible with most printer
Core, it is versatile, and develop simply, efficiently.
Claims (10)
1. a kind of printer core control system based on FPGA, including MCU units, it is characterised in that：The MCU units pass through
FPGA unit connects print control interface；
Print data buffer process module, print command buffer process module, the MCU units point are equipped in the FPGA unit
Indescribably for CLK clock signals, the CLK clock signals connect print data buffer process module, printing by PLL times of frequency module
Order caching processing module；The print data buffer process module connects SSC interfaces by SSC buses, passes through data link
The print control interface is connected, the print data buffer process module also connects EBI buses by data communication bus and connects
Mouthful, the MCU units connect the SSC buses by SSC interfaces respectively, connect the data communication by EBI bus interface
Bus, the MCU units provide clock and synchronizing signal by the SSC buses for the FPGA unit；
The print command buffer process module connects EBI bus interface by command communication bus, is connected by command link
The print control interface, the MCU units are by EBI bus interface bind command communication bus, and the FPGA unit is by institute
The order data for stating the transmission of MCU units is converted to the serial bus protocol of printer core identification, and configures printer core；It is described
FPGA unit sends the information that the printer core transmits to the MCU unit resolves.
2. the printer core control system based on FPGA as described in claim 1, it is characterised in that：The print data caching
The multiple selector that processing module includes the frequency divider being connect with CLK clock signals, is connect with the frequency divider, the MCU are mono-
Member provides the CLK clock signals, and the EBI bus interface connects the multiple selector by DPI frequency mask registers,
The multiple selector output sampling clock feeds back to the MCU units；
The print data buffer process module further includes that module occurs for lock-out pulse, the sorting that is connected with line locking signal is isolated
Logic module, the print control interface provide the line locking signal, and the EBI bus interface passes through lock-out pulse register
It connects the lock-out pulse and module occurs, the sorting isolation logic module connects the lock-out pulse and module occurs, described to adopt
Sample clock connects the lock-out pulse and module occurs, and the lock-out pulse generation module output line synchronizing signal feeds back to described
MCU units.
3. the printer core control system based on FPGA as claimed in claim 2, it is characterised in that：The lock-out pulse deposit
Device includes that lock-out pulse starts register, lock-out pulse end register and lock-out pulse line length register.
4. the printer core control system as claimed in claim 1,2 or 3 based on FPGA, it is characterised in that：The printing number
Further include the LVDS conversion modules of print data signal connection according to buffer process module, the MCU units provide print data letter
Number, the LVDS conversion modules export LVDS signals to the print control interface；LVDS conversion modules are responsible for MCU units is defeated
The data-signal entered is converted to LVDS formats and is read for the printer core that print control interface connects.
5. the printer core control system based on FPGA as described in claim 1, it is characterised in that：The print command caching
Processing module includes the frequency divider being connect with CLK clock signals, the first clock post-processing module being connect with the frequency divider, institute
It states after the first clock post-processing module generates logical timer and connects second clock post-processing module, the second clock post-processes mould
Block exports synchronised clock to the print control interface；
The print command buffer process module further includes parallel serial conversion module, serioparallel exchange module, two-way separation module, described
The order data of MCU units output connects the two-way point after connecting the parallel serial conversion module by the EBI bus interface
From module, the two-way separation module connects the print control interface by data line；The print control interface feedback
After feedback data connects the serioparallel exchange module by the two-way separation module, institute is fed back to by the EBI bus interface
State MCU units.
6. the printer core control system based on FPGA as claimed in claim 5, it is characterised in that：The parallel serial conversion module
The data latch module that is connect including buffer process module, with the buffer process module, by the buffer process module displacement
The output end of enabled shift register, the data latch module connects the shift register, the shift register
Output end connects the two-way separation module；
The EBI bus interface connects the buffer process module by writing the effective register of data, passes through write data register
Connect the data latch module；
The logical timer is separately connected the buffer process module, the shift register.
7. the printer core control system based on FPGA as claimed in claim 5, it is characterised in that：The serioparallel exchange module
The data latch module that is connect including buffer process module, with the buffer process module, by the buffer process module displacement
Enabled shift register, the parallel signal of two-way separation module output end output be sequentially connected the shift register,
The data latch module, multiplexer；Another output end of the buffer process module connects the multiplexer；One
The status register of printer core connects the multiplexer；
The EBI bus interface connects the buffer process module by reading the effective register of data, passes through read data register
Connect the multiplexer；
The logical timer is separately connected the buffer process module, the shift register.
8. the printer core control system based on FPGA as described in claim 1, it is characterised in that：It further include power management list
Member, the Power Management Unit output 5V power supplys and 3.3V power supplys, the 3.3V power supplys connect the logic electricity of the FPGA unit
Source；
The 3.3V power supplys connect core power ends after exporting 1.2V power supplys by power conversion chip；
The 5V power supplys connect the LDVS power ends of the FPGA unit after exporting 2.5V power supplys by power conversion chip.
9. the printer core control system based on FPGA as described in claim 1, it is characterised in that：It further include the peripheries FPGA electricity
Road, the FPGA peripheral circuit include external crystal-controlled oscillation, and the external crystal-controlled oscillation connects the Clock Tree of the FPGA unit；
The FPGA peripheral circuit includes E2ROM modules, and the BOOT drivings that the E2ROM modules connect the FPGA unit connect
Mouthful.
10. the printer core control system based on FPGA as described in claim 1, it is characterised in that：Further include the peripheries FPGA
Circuit, the FPGA peripheral circuit include emulation interface, and the emulation interface connects the debugging drive module of the FPGA unit；
The FPGA peripheral circuit includes reset circuit, the reset terminal of the reset circuit connection FPGA unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820203339.5U CN207764780U (en) | 2018-02-06 | 2018-02-06 | printer core control system based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820203339.5U CN207764780U (en) | 2018-02-06 | 2018-02-06 | printer core control system based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063195A (en) * | 2019-11-19 | 2020-04-24 | 珠海市德宇辉煌信息科技有限公司 | License plate recognition device and system |
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2018
- 2018-02-06 CN CN201820203339.5U patent/CN207764780U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063195A (en) * | 2019-11-19 | 2020-04-24 | 珠海市德宇辉煌信息科技有限公司 | License plate recognition device and system |
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