CN102207922A - Bus interface and clock frequency control method thereof - Google Patents
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- CN102207922A CN102207922A CN2010101587630A CN201010158763A CN102207922A CN 102207922 A CN102207922 A CN 102207922A CN 2010101587630 A CN2010101587630 A CN 2010101587630A CN 201010158763 A CN201010158763 A CN 201010158763A CN 102207922 A CN102207922 A CN 102207922A
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Abstract
The embodiment of the invention discloses a bus interface, which comprises a chip selection end, a first transmission bus end, a second transmission bus end and a clock control device. The chip selection end transmits a chip selection signal to start the transmission of data. When the data transmission is started, the first transmission bus end transmits the data to a second device, and the second transmission bus end transmits the data from the second device to a first device. The clock control device is provided with a frequency processing unit and a transmission clock generating unit. When the frequency set value changes, the frequency processing unit outputs a clock control signal, and the transmission clock generating unit receives the clock control signal and generates a transmission clock signal according to the numerical value of the frequency set value. According to the bus interface and a clock frequency control method thereof of the embodiment, the frequency of the transmission clock signal can be timely and elastically regulated according to the requirement of the system on the clock frequency, so that more data or commands are received, and the transmission time of the data is effectively shortened.
Description
Technical field
The present invention relates to a kind of clock control device, relate in particular to a kind of clock control device that produces the required clock signal of universal serial bus.
Background technology
Serial bus interface (Serial Peripheral Interface; SPI) for being widely used in a kind of between element and the element from/body frame structure connecting interface.In the middle of traditional serial bus interface, the serial transmission clock of being exported is single-frequency, and in other words, the data that no matter is transmitted all adopts single transfer rate to transmit for order or data.For day by day novel system applies, the serial transmission clock of single-frequency can't satisfy the demand in the system.
Therefore need a kind of new clock control device, can adjust the frequency of transfer clock immediately and promptly according to the needs of each system.
Summary of the invention
The embodiment of the invention provides the clock frequency control method of a kind of bus interface and bus interface, can adjust the frequency of transmit clock signal immediately and flexibly according to the requirement of system to clock frequency.
According to one embodiment of the invention, bus interface is coupled to one first device, and this bus interface includes a chip selecting side, one first transfer bus end, one second transfer bus end and a clock control device.The chip selecting side is in order to transmit a chip select signal, the transmission of log-on data by this.When data transmission started, the first transfer bus end was sent to one second device with data, and the second transfer bus end transfers to first device with data from second device.Clock control device contains a frequency processing unit and a transfer clock generation unit.When a frequency setting value changed, a clock control signal was exported in the frequency processing unit, and transfer clock generation unit receive clock control signal also produces a transmit clock signal according to frequency setting value.
According to another embodiment of the present invention, bus interface is coupled to one first device, and this bus interface contains a chip selecting side, one first transfer bus end, one second transfer bus end and a clock control device.The chip selecting side is in order to transmit a chip select signal, the transmission of log-on data by this.When data transmission started, the first transfer bus end was sent to second device with data, and the second transfer bus end transfers to first device with data from second device.Clock control device contains a frequency processing unit and a transfer clock generation unit.The frequency processing unit produces the frequency that a transmit clock signal is adjusted in a frequency control position, transfer clock generation unit receive frequency control bit, and produce a transmit clock signal according to the frequency control position.
According to an embodiment more of the present invention, but the frequency of clock frequency control method modulation one transmit clock signal of bus interface, this clock control method for frequency judges whether a bus begins transmission command or data, when bus begins transmission command or data, detect a frequency setting value and whether change.When frequency setting value changes, judge whether a package group finishes transmission.The group finishes transmission when package, then is written into new frequency setting value, according to the frequency of loaded frequency setting value adjustment transmit clock signal, and the adjusted transmit clock signal of output frequency.
According to another embodiment of the present invention, the clock frequency control method of bus interface, can carry out the frequency of central modulation one transmit clock signal in package group transmission, this clock control method for frequency can judge whether a bus begins transmission command or data, when bus begins transmission command or data, judge whether a variable different time preface output signal is established.Establish when variable different time preface output signal, then, in the middle of a plurality of frequency setting values, select one, and make the frequency of transmit clock signal be adjusted into the pairing frequency of selected frequency setting value according to the numerical value of a frequency control position.
Description of drawings
For allowing above-mentioned and other purposes of the present invention, feature, advantage and embodiment can become apparent appended graphic being described as follows:
Fig. 1 is the block schematic diagram that illustrates bus system;
Fig. 2 A is the calcspar that illustrates an embodiment of the present invention bus interface clock control device;
Fig. 2 B is the process flow diagram that illustrates an embodiment of the present invention bus interface clock frequency control method;
Fig. 2 C is the oscillogram that illustrates an embodiment of the present invention bus interface clock control device;
Fig. 3 A is the calcspar that illustrates another embodiment bus interface clock control device of the present invention;
Fig. 3 B is the process flow diagram that illustrates another embodiment bus interface timing control method of the present invention;
Fig. 3 C be illustrate an embodiment of the present invention bus interface clock control device oscillogram.
Drawing reference numeral:
101: serial bus interface 103: serial bus interface
200: clock control device 201: frequency detecting unit
203: transmission cycle controller 203: the transmission cycle controller
204: transfer clock generation unit 205: the transmission cycle buffer
Logical-arithmetic unit 209 in 207: the first: logic comparator
211: frequency setting value buffer 213: computing numerical value buffer
215: clock counter 217: the transmission cycle counter
221～229: step 300: clock control device
301: but 303: the second logical-arithmetic units of variation frequency control module
305: multiplex's selector switch 321～329: step
307: frequency control position buffer
309,311: the frequency setting value buffer
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the embodiment of the invention is described in further details below in conjunction with accompanying drawing.At this, illustrative examples of the present invention and explanation thereof are used to explain the present invention, but not as a limitation of the invention.
Bus interface of following examples and clock frequency control method thereof can be adjusted the frequency of serial transmission clock signal immediately according to needs, can make serial bus interface (Serial Peripheral Interface; SPI) device on can the immediate reaction data variation, maybe can collect more data.
Please refer to Fig. 1, it is the block schematic diagram that illustrates an embodiment of the present invention bus system.In the middle of this bus system, bus interface, for example serial bus interface 101, can be coupled to first device 105, and serial bus interface 103 can be coupled to second device 107.First device 105 can be serial bus master, second device 107 can be universal serial bus from device, serial bus interface 101 can have chip selecting side (Slave Select) SS, the first transfer bus end and go out from going into (Master Output SlaveInput) MOSI, the second transfer bus end to go into from going out (Master Input Slave Output) MISO as main as main, and clock control device 109.
Chip selecting side SS can be used to transmit chip select signal, by this transmission of log-on data.When data transmission starts, the first transfer bus end MOSI is sent to second device, 107, the second transfer bus end MISO with data with for example serial (Serial) pattern and then data is transferred to first device 105 with for example serial (Serial) pattern from second device 107.But the transmission speed that clock control device 109 clockings come control data.
Please refer to Fig. 2 A, it is the calcspar that illustrates an embodiment of the present invention bus interface clock control device.Clock control device 200, be used for producing the transmit clock signal that frequency adjustable becomes, for example can be the clock control device that is arranged at serial bus interface (Serial Peripheral Interface) main device (Master) or comes control data (Data) and order (Command) transmission in the middle of the device (Slave).Clock control device 200 can have frequency processing unit 202 and transfer clock generation unit 204.When a frequency setting value changes, frequency processing unit 202 output clock control signals.Transfer clock generation unit 204 receives this clock control signal, and produces transmit clock signal according to frequency setting value.
Frequency processing unit 202 can contain frequency detecting unit 201 and frequency setting value buffer 211.Frequency setting value buffer 211 receives and the stored frequency setting value, detects for frequency detecting unit 201.Whether frequency detecting unit 201 couples frequency setting value buffer 211, change to detect frequency setting value.When frequency detecting unit 201 detects frequency setting value and changes, the frequency change flag will be established (Assert), frequency setting value in the frequency setting value buffer 211 can be output to computing numerical value buffer 213, aforesaid establishment can be and makes the frequency change flag have the accurate position of a certain logic, and for example 0 or 1.
In the middle of Fig. 2 A, transfer clock generation unit 204 contains clock counter 215, logic comparator 209, transmission cycle counter 217, transmission cycle controller 203, first logical-arithmetic unit 207, computing numerical value buffer 213.
Aforesaid clock counter 215 can be in order to cycle (cycle) number of number system clock signal, the frequency of this clock signal of system is usually above the frequency of transmit clock signal, is that calculate on the basis in order to clock counter 215 with the clock signal of system, adjusts the frequency of transmit clock signal.Logic comparator 209 can be in order to receive and the number of cycles of comparison frequency setting value and the clock signal of system that added up, when frequency setting value equates with the number of cycles of clock signal of system, logic comparator 209 can be established the clock enable signal, impels transmission cycle counter 217 output transmit clock signals.Situation when aforesaid frequency setting value equates with the number of cycles of clock signal of system can describe by following object lesson.If frequency setting value is 0x15F (16 carry), then when clock counter 215 by 0 on number to 0x15F or when counting to 0x15F down by 0xFFF, transmission cycle counter 217 will be exported transmit clock signal, the New count of laying equal stress on.Gap between aforementioned frequency setting value and maximum value or minimal value is big more, represents gate time long more, and in this case, the frequency of transmit clock signal will be low more.
When clock counter 215 adopt by 0 up count mode the time, the content of aforesaid frequency setting value for example can be one " divisor ".For instance, when system clock is 24MHz,, can with the content setting of frequency setting value buffer 211 " 12 " just at this time if wish that the clock of output is 2MHz, then 12 clock signal of system of clock counter 215 countings are after the cycle, and promptly exportable clock is the transmit clock signal of 2MHz.
In the middle of the present embodiment, the frequency of transmit clock signal can just can be carried out modulation after finishing at data packet (Data Packet) or order package (Command packet) transmission, can in the middle of same data packet group or same order package group's transmission, not carry out modulation, in this case, can see through transmission cycle controller 203 and judge whether the package group finishes transmission.When frequency setting value changes and the package group finishes in the transmission, first logical-arithmetic unit 207 can be established the frequency change flags, and the frequency of expression transmit clock signal needs conversion; If the frequency of transmit clock signal is finished variation, then first logical-arithmetic unit 207 can instead be established (De-assert) frequency change flag.Computing numerical value buffer 213 can be written into (Load) frequency setting value from frequency setting value buffer 211, and the output frequency setting value be to logic comparator 209 when the frequency change flag is established.In another embodiment, frequency setting value can directly export logic comparator 209 to by frequency setting value buffer 211.
Please refer to Fig. 2 B, it is the process flow diagram that illustrates an embodiment of the present invention bus interface clock frequency control method.But the frequency of clock frequency control method modulation transmit clock signal, this clock control method for frequency judge at first whether bus begins transmission command or data (step 221).When bus begins transmission command or data, then detect frequency setting value and whether change (step 223), if transmission does not begin as yet, then stay on and come the state of testbus in step 221.If find that in the middle of step 223 frequency setting value changes, then continue to judge whether a package group finishes transmission (step 225); If frequency setting value does not change, then stay on and in step 223, detect frequency setting value.The group finishes transmission when package, then is written into new frequency setting value, and adjusts the frequency (step 227) of transmit clock signal according to loaded frequency setting value, then again output frequency through adjusted transmit clock signal (step 229); If the package group does not finish transmission as yet, then continue to detect the package group.
Please refer to Fig. 2 C, it illustrates the oscillogram of an embodiment of the present invention bus interface clock control device.In the middle of the signal that Fig. 2 C is illustrated, chip select signal, transfer clock and mainly go out from signal such as going into and to export to from device by main device, the master goes into then can be by export main device to from device from going out signal, wherein mainly go out from going into main to go into to be responsible for carrying order and data from going out signal, transmit clock signal then can be used to be responsible for the transmission speed of control command and data.Having illustrated three package groups on the transmit clock signal of Fig. 2 C, is respectively package group 1, package group 2 and package group 3, and frequency is then adjusted between a package group and another package group.
Fig. 2 C when frequency setting value, can be caused the frequency change flag earlier and establish when being adjusted to 0x15F by 0x7F (16 carry), follows the frequency of transmit clock signal and just can and then adjust as can be seen thus.Find that when clock control device the frequency of transmit clock signal finishes adjustment according to new frequency setting value, can instead establish the frequency change flag, when treating next frequency change again with it establishment.
When need carry out command transfer as configuration address (Configuration), can accelerate transmission speed, so can increase the frequency of the transmit clock signal that is adopted; Be only the transmission of data information after command transfer is finished, these data are produced by slower device such as the analog-digital converter of reaction, and transmission speed is slow, so can reduce the frequency of transmit clock signal.
Please refer to Fig. 3 A, it illustrates the calcspar of another embodiment bus interface clock control device of the present invention.The clock control device 300 of this embodiment can carry out central and the package group does not finish in the transmission as yet in same package group transmission, adjusts the frequency of transmit clock signal.Clock control device 300 timing units contain frequency processing unit 302 and transfer clock generation unit 304.Frequency processing unit 302 produces the frequency that transmit clock signal is adjusted in the frequency control positions, transfer clock generation unit 304 receive frequency control bits, and produce transmit clock signal according to the numerical value of frequency control position.
But frequency processing unit 302 can contain frequency control position buffer 307 variation frequency control modules 301, frequency setting value buffer 309 and frequency setting value buffer 311.Frequency control position buffer 307 is in order to the stored frequency control bit, and the user can see through a peripheral control unit (not illustrating) this frequency control position is stored in the frequency control position buffer 307.But the frequency control position can further be written in the variation frequency control module 301, but can have a shift count index (not illustrating) in the variation frequency control module 301, this shift count index can export the frequency control position of its reception to second logical-arithmetic unit 303 in the transfer clock generation unit 304 in regular turn.For instance, shown in Fig. 3 C, but variation frequency control module 301 can export second logical-arithmetic unit 303 to according in regular turn that it is the stored numerical value 00000000011 of shift count index.
In the middle of Fig. 3 A, frequency setting value buffer 309 and frequency setting value buffer 311 receives and stores the frequency setting value of several different numerical value, for example 0x80 and 0x15F, and see through multiplex's selector switch 305 of transfer clock generation unit 304, selected frequency setting value is offered computing numerical value buffer 213, change the frequency of transmit clock signal by this.
Transfer clock generation unit 304 contains multiplex's selector switch 305, second logical-arithmetic unit 303, computing numerical value buffer 213, clock counter 215, logic comparator 209 and transmission cycle counter 217, and wherein the running of computing numerical value buffer 213, clock counter 215, logic comparator 209 and transmission cycle counter 217 then has been stated from the middle of the embodiment of Fig. 2 A.
When the user establishes variable different time preface output signal (numerical value is 1), second logical-arithmetic unit 303 can offer multiplex's selector switch 305 with the frequency control position, again by the numerical value of multiplex's selector switch 305 according to the frequency control position, select one in the middle of several frequency setting values and be used as the frequency of transmit clock signal, and can see through computing numerical value buffer 213 and store the frequency setting value that multiplex's selector switchs 305 are chosen.
The number of cycles that clock counter 215 number system clock signals are produced, the number of cycles and the frequency setting value of 209 comparison system clock signals of logic comparator, when the number of cycles of clock signal of system equates with frequency setting value, clock counter 215 can be established the clock enable signal, causes transmission cycle counter 217 output transmit clock signals.
Clock control device also has transmission cycle controller 203 and transmission cycle buffer 205 in addition.Transmission cycle buffer 205 stores the transfer clock pulse number that institute's desire produces, whether clock period number that 203 comparisons of transmission cycle controller institute desire produces and the clock period number that has produced both equate, judge whether the package group has finished transmission, when this two number equates to represent the package group to finish transmission, can consider whether need adjust at this moment the frequency of transmit clock signal once more.
Please refer to Fig. 3 B, it is the process flow diagram that illustrates another embodiment bus interface clock frequency control method of the present invention, this clock control method for frequency is the frequency of coming the modulation transmit clock signal in the middle of package group transmission is carried out, the method judges at first whether bus begins transmission command or data (step 321), when bus begins transmission command or data, continue to judge whether variable different time preface output signal is established (step 323), if the idle step 321 that then rests on of bus, the state of continuation testbus.If find that in step 323 variable different time preface output signal is established, then according to the numerical value of frequency control position, in the middle of several frequency setting values, select one (step 325), and make the frequency of transmit clock signal be adjusted into the pairing frequency of selected frequency setting value (step 327).On the other hand, if find that in step 323 variable different time preface output signal is not established, representative just will consider the frequency of whether adjusting transmit clock signal after package group end of transmission (EOT), can not adjust frequency in the middle of the transmission.
Please refer to Fig. 3 C, it illustrates the oscillogram of an embodiment of the present invention bus interface timing control method.In the middle of the waveform of Fig. 3 C, chip select signal, transfer clock and main go out from signal such as going into export to from device by main device, the master goes into from going out signal then by export main device to from device, and wherein the master goes out from going into main to go into to be responsible for carrying order and data from going out signal.
When variable different time preface output signal is established, representative need be carried out the frequency of central modulation transmit clock signal in same package group transmission, this moment, the new frequency of the stored pairing frequency of frequency setting value 1 (0x80) of first frequency setting value buffer as transmit clock signal selected in representative if but the numerical value of variation frequency control bit is 0; , represent the new frequency of the stored pairing frequency of frequency setting value 2 (0x15F) of second frequency setting value buffer of selection as transmit clock signal if but the numerical value of variation frequency control bit is 1.
In the middle of the same package group's of this embodiment transmission, 5 positions, front belong to the command component that buffer is set, transmission speed can be promoted to for example 2MHZ (transmission time is 0.5 μ s), then is section data, and transmission speed is reduced to for example 400K (transmission time is 2.5 μ s).For instance, can't adjust and only have under the state of single transmission frequency (for example 400KHz) in the frequency of original transmit clock signal, 16 transmission needs 16 * 2.5us=40us.Adjust the frequency of transmit clock signal through an embodiment thus, 16 transmission only need 5 * 0.5us+11 * 2.5us=30us, has saved for 25% time.
The clock control device of above embodiment or method, can be according to the requirement of system to clock frequency, between two package groups of order or data, also or in the middle of the same package group of order or data transmission carries out, immediately and flexibly adjust the frequency of transmit clock signal, receive the data or the order of greater number, to shorten the delivery time of data effectively.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; any technician in the technical field of the invention; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (14)
1. a bus interface is characterized in that, described bus interface is coupled to one first device, and described bus interface comprises:
One chip selecting side is in order to transmit a chip select signal, the transmission of log-on data by this;
One first transfer bus end with when data transmission starts, is sent to one second device with data;
One second transfer bus end with when data transmission starts, transfers to described first device with data from described second device; And
One clock control device, described clock control device comprises:
A clock control signal with when a frequency setting value changes, is exported in one frequency processing unit; And
One transfer clock generation unit receives described clock control signal and produces a transmit clock signal according to described frequency setting value.
2. bus interface as claimed in claim 1 is characterized in that, described frequency processing unit comprises:
One frequency setting value buffer receives and stores described frequency setting value; And
Whether one frequency detecting unit couples described frequency setting value buffer, change to detect described frequency setting value.
3. bus interface as claimed in claim 2 is characterized in that, described transfer clock generation unit comprises:
One clock counter is counted the number of cycles of a clock signal of system;
One logic comparator, the number of cycles of reception and more described frequency setting value and described clock signal of system when described frequency setting value equates with the number of cycles of described clock signal of system, is established a clock enable signal; And
One transmission cycle counter with when described clock enable signal is established, is exported described transmit clock signal.
4. bus interface as claimed in claim 3 is characterized in that, described transfer clock generation unit more comprises:
Whether one transmission cycle controller finishes transmission to judge a package group;
One first logical-arithmetic unit to establish when described clock control signal and described package group finishes in the transmission, is established a frequency change flag; And
One computing numerical value buffer with when described frequency change flag is established, is written into described frequency setting value from described frequency setting value buffer, and exports described frequency setting value to described logic comparator.
5. bus interface as claimed in claim 4, it is characterized in that, described transfer clock generation unit more comprises a transmission cycle buffer, to store the clock period number that described transmit clock signal institute desire produces, clock period number that the described transmission cycle controller comparison of confession institute desire produces and the clock period number that has produced, when this two number equates, judge that described package group has finished transmission.
6. a bus interface is characterized in that, described bus interface is coupled to one first device, and described bus interface comprises:
One chip selecting side is in order to transmit a chip select signal, the transmission of log-on data by this;
One first transfer bus end with when data transmission starts, is sent to one second device with data;
One second transfer bus end with when data transmission starts, transfers to described first device with data from described second device; And
One clock control device, described clock control device comprises:
One frequency processing unit is in order to produce the frequency that a transmit clock signal is adjusted in a frequency control position; And
One transfer clock generation unit receives described frequency control position, and produces a transmit clock signal according to the numerical value of described frequency control position.
7. bus interface as claimed in claim 6 is characterized in that, the frequency of described transmit clock signal is in the middle of same package group transmission is carried out, and described package group do not finish in the transmission as yet, carries out modulation.
8. bus interface as claimed in claim 6 is characterized in that, described frequency processing unit comprises:
One frequency control position buffer is in order to store described frequency control position; And
But a variation frequency control module is written into described frequency control position by described frequency control position buffer, and exports described frequency control position to described transfer clock generation unit in regular turn through a shift count index.
9. bus interface as claimed in claim 8 is characterized in that, described frequency processing unit more comprises a plurality of frequency setting value buffers, stores and provide a plurality of frequency setting values.
10. bus interface as claimed in claim 9 is characterized in that, described transfer clock generation unit comprises:
One multiplex's selector switch is to select one according to the numerical value of described frequency control position in the middle of described frequency setting value;
One clock counter is to count the number of cycles of a clock signal of system;
One logic comparator, the described frequency setting value that reception and more described multiplex's selector switch are chosen and the number of cycles of described clock signal of system, when described frequency setting value equates with the number of cycles of described clock signal of system, establish a clock enable signal; And
One transmission cycle counter with when described clock enable signal is established, is exported described transmit clock signal.
11. bus interface as claimed in claim 10 is characterized in that, described transfer clock generation unit more comprises:
One computing numerical value buffer is to store the described frequency setting value that described multiplex's selector switch chosen and to export described frequency setting value to described logic comparator; And
One second logical-arithmetic unit with when a variable different time preface output signal is established, offers described multiplex's selector switch with described frequency control position.
12. bus interface as claimed in claim 11 is characterized in that, described transfer clock generation unit more comprises:
One transmission cycle buffer is to store the clock period number that described transmit clock signal institute desire produces; And
One transmission cycle controller, on behalf of a package group, clock period number that produces with more described transmit clock signal institute desire and the clock period number that has produced when this two number equates, finished transmission.
13. the clock frequency control method of a bus interface is characterized in that, described clock frequency control method is in order to the frequency of modulation one transmit clock signal, and described clock frequency control method comprises:
Judge whether a bus begins transmission command or data;
When described bus begins transmission command or data, detect a frequency setting value and whether change;
When described frequency setting value changes, judge whether a package group finishes transmission;
When described package group finishes transmission, then be written into the frequency that new described frequency setting value and the loaded described frequency setting value of foundation are adjusted described transmit clock signal; And
The adjusted described transmit clock signal of output frequency.
14. the clock frequency control method of a bus interface is characterized in that, described clock frequency control method is in order in the middle of package group transmission is carried out, the frequency of modulation one transmit clock signal, and described clock frequency control method comprises:
Judge whether a bus begins transmission command or data;
When described bus begins transmission command or data, judge whether a variable different time preface output signal is established;
Establish when described variable different time preface output signal, then, in the middle of a plurality of frequency setting values, select one according to the numerical value of a frequency control position; And
Make the frequency of described transmit clock signal be adjusted into the selected pairing frequency of described frequency setting value.
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| CN105718402B (en) * | 2016-01-13 | 2021-04-20 | 福州瑞芯微电子股份有限公司 | Programmable timing generator |
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