CN102207922B - Bus interface and clock frequency control method thereof - Google Patents
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Abstract
The embodiment of the invention discloses a bus interface, which comprises a chip selection end, a first transmission bus end, a second transmission bus end and a clock control device. The chip selection end transmits a chip selection signal to start the transmission of data. When the data transmission is started, the first transmission bus end transmits the data to a second device, and the second transmission bus end transmits the data from the second device to a first device. The clock control device is provided with a frequency processing unit and a transmission clock generating unit. When the frequency set value changes, the frequency processing unit outputs a clock control signal, and the transmission clock generating unit receives the clock control signal and generates a transmission clock signal according to the numerical value of the frequency set value. According to the bus interface and a clock frequency control method thereof of the embodiment, the frequency of the transmission clock signal can be timely and elastically regulated according to the requirement of the system on the clock frequency, so that more data or commands are received, and the transmission time of the data is effectively shortened.
Description
Technical field
The present invention relates to a kind of clock control device, relate in particular to a kind of clock control device that produces the required clock signal of universal serial bus.
Background technology
Serial bus interface (Serial Peripheral Interface; SPI) for being widely used in one between element and element from/body frame structure connecting interface.In the middle of traditional serial bus interface, the serial transmission clock of exporting is single-frequency, and in other words, the data that no matter transmitted, for order or data, all adopts single transfer rate to transmit.For day by day novel system applies, the serial transmission clock of single-frequency cannot meet the demand in system.
Therefore need a kind of new clock control device, can, according to the needs of each system, immediately and promptly adjust the frequency of transfer clock.
Summary of the invention
The embodiment of the present invention provides the clock frequency control method thereof of a kind of bus interface and bus interface, can the requirement to clock frequency according to system, immediately and flexibly adjust the frequency of transmit clock signal.
According to one embodiment of the invention, bus interface is coupled to a first device, and this bus interface includes a chip selection end, one first transfer bus end, one second transfer bus end and a clock control device.Chip selection end is in order to transmit a chip select signal, the transmission of log-on data by this.In the time that data transmission starts, data are sent to one second device by the first transfer bus end, and the second transfer bus end transfers to first device by data from the second device.Clock control device contains a frequency processing unit and a transfer clock generation unit.In the time that a frequency setting value changes, a clock control signal is exported in frequency processing unit, and transfer clock generation unit receive clock control signal also produces a transmit clock signal according to frequency setting value.
According to another embodiment of the present invention, bus interface is coupled to a first device, and this bus interface contains a chip selection end, one first transfer bus end, one second transfer bus end and a clock control device.Chip selection end is in order to transmit a chip select signal, the transmission of log-on data by this.In the time that data transmission starts, data are sent to the second device by the first transfer bus end, and the second transfer bus end transfers to first device by data from the second device.Clock control device contains a frequency processing unit and a transfer clock generation unit.Frequency processing unit produces a frequency control position adjusts the frequency of a transmit clock signal, transfer clock generation unit receive frequency control bit, and produce a transmit clock signal according to frequency control position.
According to an embodiment more of the present invention, the clock frequency control method thereof of bus interface can modulation one transmit clock signal frequency, this clock frequency control method thereof judges whether a bus starts transmission command or data, when bus starts transmission command or data, detect a frequency setting value and whether change.When frequency setting value changes, judge whether a package group completes transmission.When package, group completes transmission, is written into new frequency setting value, adjusts the frequency of transmit clock signal according to loaded frequency setting value, and the transmit clock signal of output frequency after adjusting.
According to another embodiment of the present invention, the clock frequency control method thereof of bus interface, can carry out in a package group transmission frequency of central modulation one transmit clock signal, this clock frequency control method thereof can judge whether a bus starts transmission command or data, when bus starts transmission command or data, judge whether a variable different time order output signal is established.Establish when variable different time order output signal,, according to the numerical value of a frequency control position, in the middle of multiple frequency setting values, select one, and make the frequency of transmit clock signal be adjusted into the corresponding frequency of selected frequency setting value.
Brief description of the drawings
For above and other object of the present invention, feature, advantage and embodiment can be become apparent, appended graphic being described as follows:
Fig. 1 is the block schematic diagram that illustrates bus system;
Fig. 2 A is the calcspar that illustrates an embodiment of the present invention bus interface clock control device;
Fig. 2 B is the process flow diagram that illustrates an embodiment of the present invention bus interface clock frequency control method thereof;
Fig. 2 C is the oscillogram that illustrates an embodiment of the present invention bus interface clock control device;
Fig. 3 A is the calcspar that illustrates another embodiment bus interface clock control device of the present invention;
Fig. 3 B is the process flow diagram that illustrates another embodiment bus interface timing control method of the present invention;
Fig. 3 C be illustrate an embodiment of the present invention bus interface clock control device oscillogram.
Drawing reference numeral:
101: serial bus interface 103: serial bus interface
200: clock control device 201: frequency detecting unit
203: transmission cycle controller 203: transmission cycle controller
204: transfer clock generation unit 205: transmission cycle buffer
207: the first logical-arithmetic units 209: logic comparator
211: frequency setting value buffer 213: computing numerical value buffer
215: clock counter 217: transmission cycle counter
221～229: step 300: clock control device
301: can 303: the second logical-arithmetic units of variation frequency control module
305: multiplex's selector switch 321～329: step
307: frequency control position buffer
309,311: frequency setting value buffer
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiment of the present invention is described in further details.At this, schematic description and description of the present invention is used for explaining the present invention, but not as a limitation of the invention.
The bus interface of following examples and clock frequency control method thereof thereof, can adjust immediately according to needs the frequency of serial transmission clock signal, can make serial bus interface (Serial Peripheral Interface; SPI) device on can immediate reaction data variation, maybe can collect more data.
Please refer to Fig. 1, it is the block schematic diagram that illustrates an embodiment of the present invention bus system.In the middle of this bus system, bus interface, for example serial bus interface 101, can be coupled to first device 105, and serial bus interface 103 can be coupled to the second device 107.First device 105 can be serial bus master, the second device 107 can be universal serial bus from device, serial bus interface 101 can have chip selection end (Slave Select) SS, the first transfer bus end as led from entering (Master Output SlaveInput) MOSI, the second transfer bus end as led from going out (Master Input Slave Output) MISO, and clock control device 109.
Chip selection end SS can be used to transmit chip select signal, by this transmission of log-on data.In the time that data transmission starts, the first transfer bus end MOSI is sent to the second device 107, the second transfer bus end MISO by data with for example serial (Serial) pattern and data is transferred to first device 105 with for example serial (Serial) pattern from the second device 107.Clock control device 109 can clocking be controlled the transmission speed of data.
Please refer to Fig. 2 A, it is the calcspar that illustrates an embodiment of the present invention bus interface clock control device.Clock control device 200, be used for producing the transmit clock signal that frequency can modulation, for example, can be and be arranged at serial bus interface (Serial Peripheral Interface) main device (Master) or from controlling the clock control device of data (Data) and order (Command) transmission in the middle of device (Slave).Clock control device 200 can have frequency processing unit 202 and transfer clock generation unit 204.In the time that a frequency setting value changes, frequency processing unit 202 output clock control signals.Transfer clock generation unit 204 receives this clock control signal, and produces transmit clock signal according to frequency setting value.
Frequency processing unit 202 can contain frequency detecting unit 201 and frequency setting value buffer 211.Frequency setting value buffer 211 receives and stored frequency setting value, detects for frequency detecting unit 201.Whether frequency detecting unit 201 couples frequency setting value buffer 211, change to detect frequency setting value.In the time that frequency detecting unit 201 detects that frequency setting value changes, frequency change flag will be established (Assert), frequency setting value in frequency setting value buffer 211 can be output to computing numerical value buffer 213, aforesaid establishment can be and makes frequency change flag have a certain logic level, and for example 0 or 1.
In the middle of Fig. 2 A, transfer clock generation unit 204 contains clock counter 215, logic comparator 209, transmission cycle counter 217, transmission cycle controller 203, the first logical-arithmetic unit 207, computing numerical value buffer 213.
Aforesaid clock counter 215 can be in order to the cycle of number system clock signal (cycle) number, the frequency of this clock signal of system is usually above the frequency of transmit clock signal, calculate as basis taking clock signal of system in order to clock counter 215, adjust the frequency of transmit clock signal.Logic comparator 209 can be in order to receive and the number of cycles of comparison frequency setting value and the clock signal of system that added up, in the time that frequency setting value equates with the number of cycles of clock signal of system, logic comparator 209 can be established clock enable signal, impels transmission cycle counter 217 to export transmit clock signal.Situation when aforesaid frequency setting value equates with the number of cycles of clock signal of system can describe by following object lesson.If frequency setting value is 0x15F (16 carry), when clock counter 215 by 0 on number when number is to 0x15F to 0x15F or under by 0xFFF, transmission cycle counter 217 will be exported transmit clock signal, the New count of laying equal stress on.Gap between aforementioned frequency setting value and maximum value or minimal value is larger, represents that gate time is longer, and in this case, the frequency of transmit clock signal will be lower.
When clock counter 215 adopt by 0 up count mode time, the content of aforesaid frequency setting value for example can be one " divisor ".For instance, when system clock is 24MHz, if wish, the clock of output is 2MHz, can be just at this time " 12 " by the content setting of frequency setting value buffer 211, after clock counter 215 is counted 12 clock signal of system cycles, can output clock the transmit clock signal that is 2MHz.
In the middle of the present embodiment, the frequency of transmit clock signal can just can be carried out modulation after data packet (Data Packet) or order package (Command packet) are transmitted, can in the middle of same data packet group or same order package group's transmission, not carry out modulation, in this case, can see through transmission cycle controller 203 and judge whether package group completes transmission.When frequency setting value changes and package group completes in transmission, the first logical-arithmetic unit 207 can be established frequency change flags, represents that the frequency of transmit clock signal needs conversion; If the frequency of transmit clock signal completes variation, the first logical-arithmetic unit 207 can instead be established (De-assert) frequency change flag.Computing numerical value buffer 213 can, in the time that frequency change flag is established, be written into (Load) frequency setting value, and output frequency setting value be to logic comparator 209 from frequency setting value buffer 211.In another embodiment, frequency setting value can directly export logic comparator 209 to by frequency setting value buffer 211.
Clock control device 200 can more contain transmission cycle buffer 205, the pulse number of the transmit clock signal producing for storage institute wish.Aforesaid transmission cycle controller 203 can be in order to the pulse number that relatively institute's wish produces and the pulse number having produced, when this two number equates, represent that the package group in bus has completed transmission, clock control device 200 can be adjusted the frequency of transmit clock signal at this moment.
Please refer to Fig. 2 B, it is the process flow diagram that illustrates an embodiment of the present invention bus interface clock frequency control method thereof.Clock frequency control method thereof can modulation transmit clock signal frequency, first this clock frequency control method thereof judges whether bus starts transmission command or data (step 221).When bus starts transmission command or data, detect frequency setting value and whether change (step 223), if transmission not yet starts, stay on and carry out the state of testbus in step 221.If find in the middle of step 223, frequency setting value changes, and continues to judge whether a package group completes transmission (step 225); If frequency setting value does not change, stay on and in step 223, detect frequency setting value.When package, group completes transmission, is written into new frequency setting value, and adjusts the frequency (step 227) of transmit clock signal according to loaded frequency setting value, follows the transmit clock signal (step 229) of output frequency after adjusting again; If package group not yet completes transmission, continue to detect package group.
Please refer to Fig. 2 C, it illustrates the oscillogram of an embodiment of the present invention bus interface clock control device.In the middle of the signal illustrating at Fig. 2 C, chip select signal, transfer clock and mainly go out can be exported to from device by main device from the signal such as entering, master enters can be by export main device to from device from going out signal, wherein master goes out from entering with main to enter to be responsible for carrying order and data from going out signal, and transmit clock signal can be used to be responsible for the transmission speed of control command and data.On the transmit clock signal of Fig. 2 C, having illustrated three package groups, is respectively package group 1, package group 2 and package group 3, and frequency is adjusted between a package group and another package group.
Fig. 2 C can find out thus, in the time that frequency setting value is adjusted to 0x15F by 0x7F (16 carry), can first causes frequency change flag and establish, and then the frequency of transmit clock signal just can and then be adjusted.When clock control device finds that the frequency of transmit clock signal completes adjustment according to new frequency setting value, can instead establish frequency change flag, with when the next frequency change again by it establishment.
In the time that need carry out command transfer as configuration address (Configuration), can accelerate transmission speed, therefore can increase the frequency of adopted transmit clock signal; After command transfer completes, be only the transmission of data information, these data produce as analog-digital converter by reacting slower device, and transmission speed is slow, therefore can reduce the frequency of transmit clock signal.
Please refer to Fig. 3 A, it illustrates the calcspar of another embodiment bus interface clock control device of the present invention.The clock control device 300 of this embodiment can carry out central and package group in same package group transmission not yet to be completed in transmission, adjusts the frequency of transmit clock signal.Clock control device 300 timing units contain frequency processing unit 302 and transfer clock generation unit 304.Frequency processing unit 302 produces frequency control position adjusts the frequency of transmit clock signal, transfer clock generation unit 304 receive frequency control bits, and produce transmit clock signal according to the numerical value of frequency control position.
Frequency processing unit 302 can contain frequency control position buffer 307, can variation frequency control module 301, frequency setting value buffer 309 and frequency setting value buffer 311.Frequency control position buffer 307 is in order to stored frequency control bit, and user can see through a peripheral control unit (not illustrating) this frequency control position is stored in frequency control position buffer 307.Frequency control position can further be written into can variation frequency control module 301 in, can in variation frequency control module 301, can have a shift count index (not illustrating), this shift count index can sequentially export the frequency control position of its reception to the second logical-arithmetic unit 303 in transfer clock generation unit 304.For instance, as shown in Figure 3 C, can sequentially export its stored numerical value 00000000011 to second logical-arithmetic unit 303 according to shift count index by variation frequency control module 301.
In the middle of Fig. 3 A, frequency setting value buffer 309 and frequency setting value buffer 311 receive and store the frequency setting value of several different numerical value, for example 0x80 and 0x15F, and see through multiplex's selector switch 305 of transfer clock generation unit 304, selected frequency setting value is offered to computing numerical value buffer 213, change by this frequency of transmit clock signal.
Transfer clock generation unit 304 contains multiplex's selector switch 305, the second logical-arithmetic unit 303, computing numerical value buffer 213, clock counter 215, logic comparator 209 and transmission cycle counter 217, and wherein the running of computing numerical value buffer 213, clock counter 215, logic comparator 209 and transmission cycle counter 217 has been loaded in the middle of the embodiment of Fig. 2 A.
In the time that user establishes variable different time order output signal (numerical value is 1), the second logical-arithmetic unit 303 can offer multiplex's selector switch 305 by frequency control position, the numerical value according to frequency control position by multiplex's selector switch 305 again, be used as the frequency of transmit clock signal from selecting one in the middle of several frequency setting values, and can see through computing numerical value buffer 213 and store the frequency setting value that multiplex's selector switch 305 is chosen.
The number of cycles that clock counter 215 number system clock signals produce, number of cycles and the frequency setting value of 209 comparison system clock signals of logic comparator, in the time that the number of cycles of clock signal of system equates with frequency setting value, clock counter 215 can be established clock enable signal, causes transmission cycle counter 217 to export transmit clock signal.
Clock control device also has transmission cycle controller 203 and transmission cycle buffer 205 in addition.Transmission cycle buffer 205 stores the transfer clock pulse number that institute's wish produces, whether the clock period numbers that 203 comparison institute wishs of transmission cycle controller produce and the clock period number having produced both equate, judge whether package group has completed transmission, complete transmission when this two number equates to represent package group, can again consider whether need adjust at this moment the frequency of transmit clock signal.
Please refer to Fig. 3 B, it is the process flow diagram that illustrates another embodiment bus interface clock frequency control method thereof of the present invention, this clock frequency control method thereof is the frequency of carrying out modulation transmit clock signal in the middle of package group transmission is carried out, first the method judges whether bus starts transmission command or data (step 321), when bus starts transmission command or data, continue to judge whether variable different time order output signal is established (step 323), if the idle step 321 that rests on of bus, the state of continuation testbus.If find in step 323, variable different time order output signal is established, according to the numerical value of frequency control position, in the middle of several frequency setting values, select one (step 325), and make the frequency of transmit clock signal be adjusted into the corresponding frequency of selected frequency setting value (step 327).On the other hand, if find in step 323, variable different time order output signal is not established, and representative just can consider whether to adjust the frequency of transmit clock signal after package group end of transmission (EOT), in the middle of transmission, can not adjust frequency.
Please refer to Fig. 3 C, it illustrates the oscillogram of an embodiment of the present invention bus interface timing control method.In the middle of the waveform of Fig. 3 C, chip select signal, transfer clock and mainly go out to be exported to from device by main device from the signal such as entering, master enters from going out signal by export main device to from device, and wherein master goes out from entering with main to enter to be responsible for carrying order and data from going out signal.
In the time that variable different time order output signal is established, representative need to be carried out in same package group transmission the frequency of central modulation transmit clock signal, if numerical value that now can variation frequency control bit is 0, the new frequency of the stored corresponding frequency of frequency setting value 1 (0x80) of first frequency setting value buffer as transmit clock signal selected in representative; If numerical value that can variation frequency control bit is 1, the new frequency of the stored corresponding frequency of frequency setting value 2 (0x15F) of second frequency setting value buffer as transmit clock signal selected in representative.
In the middle of the same package group's of this embodiment transmission, 5 positions belong to the command component that buffer is set above, transmission speed can be promoted to for example 2MHZ (transmission time be 0.5 μ s), then be the part of data, transmission speed be reduced to for example 400K (transmission time be 2.5 μ s).For instance, cannot adjust and for example only have, under the state of single transmission frequency (400KHz) in the frequency of original transmit clock signal, the transmission of 16 needs 16 × 2.5us=40us.Adjust the frequency of transmit clock signal through an embodiment thus, the transmission of 16 only need 5 × 0.5us+11 × 2.5us=30us, has saved for 25% time.
The clock control device of above embodiment or method, can the requirement to clock frequency according to system, between two package groups of order or data, also or in the middle of the same package group of order or data transmission carries out, immediately and flexibly adjust the frequency of transmit clock signal, receive data or the order of greater number, effectively to shorten the delivery time of data.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on the claim scope person of defining.
Claims (13)
1. a bus interface, is characterized in that, described bus interface is coupled to a first device, and described bus interface comprises:
One chip selection end, in order to transmit a chip select signal, the transmission of log-on data by this;
One first transfer bus end, with in the time that data transmission starts, is sent to one second device by data;
One second transfer bus end, with in the time that data transmission starts, transfers to described first device by data from described the second device; And
One clock control device, for adjusting the frequency of a transmit clock signal, to change the transmission speed of described data transmission, described clock control device comprises:
One frequency processing unit, with in the time that a frequency setting value changes, output one clock control signal; And
One transfer clock generation unit, comprises a clock counter, and described transfer clock generation unit receives described clock control signal, and by described clock counter and described frequency setting value to a system time signal-count, to produce described transmit clock signal;
The frequency of described transmit clock signal changes according to described frequency setting value.
2. bus interface as claimed in claim 1, is characterized in that, described frequency processing unit comprises:
One frequency setting value buffer, receives and stores described frequency setting value; And
Whether one frequency detecting unit, couples described frequency setting value buffer, change to detect described frequency setting value.
3. bus interface as claimed in claim 2, is characterized in that, described clock counter is counted the number of cycles of described clock signal of system, and described transfer clock generation unit more comprises:
One logic comparator, the number of cycles of reception more described frequency setting value and described clock signal of system, in the time that described frequency setting value equates with the number of cycles of described clock signal of system, described transfer clock generation unit will be exported described transmit clock signal.
4. bus interface as claimed in claim 3, is characterized in that, described transfer clock generation unit more comprises:
One transmission cycle controller, to judge whether a package group completes transmission;
One first logical-arithmetic unit, to establish when a clock control signal and described package group completes in transmission, establishes a frequency change flag; And
One computing numerical value buffer, with in the time that described frequency change flag is established, is written into described frequency setting value from described frequency setting value buffer, and exports described frequency setting value to described logic comparator.
5. bus interface as claimed in claim 4, it is characterized in that, described transfer clock generation unit more comprises a transmission cycle buffer, the clock period number producing to store described transmit clock signal institute wish, the clock period number that the described transmission cycle controller comparison of confession institute wish produces and the clock period number having produced, when this two number equates, judge that described package group has completed transmission.
6. a bus interface, is characterized in that, described bus interface is coupled to a first device, and described bus interface comprises:
One chip selection end, in order to transmit a chip select signal, the transmission of log-on data by this;
One first transfer bus end, with in the time that data transmission starts, is sent to one second device by data;
One second transfer bus end, with in the time that data transmission starts, transfers to described first device by data from described the second device; And
One clock control device, for adjusting the frequency of a transmit clock signal, to change the transmission speed of described data transmission, described clock control device comprises:
One frequency processing unit, adjusts the frequency of described transmit clock signal in order to produce a frequency control position; And
One transfer clock generation unit, receives described frequency control position, and produces described transmit clock signal according to the numerical value of described frequency control position;
Wherein, described transfer clock generation unit comprises:
One multiplex's selector switch selects one with the numerical value according to described frequency control position in the middle of described frequency setting value;
One buffer, to store the described frequency setting value that described multiplex's selector switch chosen and to export described frequency setting value to logic comparator; And
One second logical-arithmetic unit, with in the time that a variable different time order output signal is established, offers described multiplex's selector switch by described frequency control position.
7. bus interface as claimed in claim 6, is characterized in that, the frequency of described transmit clock signal is in the middle of same package group transmission is carried out, and described package group not yet completes in transmission, carries out modulation.
8. bus interface as claimed in claim 6, is characterized in that, described frequency processing unit comprises:
One frequency control position buffer, in order to store described frequency control position; And
One can variation frequency control module, is written into described frequency control position by described frequency control position buffer, and sees through a shift count index and sequentially export described frequency control position to described transfer clock generation unit.
9. bus interface as claimed in claim 8, is characterized in that, described frequency processing unit more comprises multiple frequency setting value buffers, stores and provide multiple frequency setting values.
10. bus interface as claimed in claim 9, is characterized in that, described transfer clock generation unit comprises:
One clock counter, to count the number of cycles of a clock signal of system;
One logic comparator, the described frequency setting value that reception more described multiplex's selector switch are chosen and the number of cycles of described clock signal of system, in the time that described frequency setting value equates with the number of cycles of described clock signal of system, described transfer clock generation unit will be exported described transmit clock signal.
11. bus interface as claimed in claim 6, is characterized in that, described transfer clock generation unit more comprises:
One transmission cycle buffer, the clock period number producing to store described transmit clock signal institute wish; And
One transmission cycle controller, the clock period number producing with more described transmit clock signal institute wish and the clock period number having produced, when this two number equates, represent that a package group has completed transmission.
The clock frequency control method thereof of 12. 1 kinds of bus interface, is characterized in that, described clock frequency control method thereof is in order to the frequency of modulation one transmit clock signal, and described clock frequency control method thereof comprises:
Judge whether a bus starts transmission command or data;
When described bus starts transmission command or data, detect a frequency setting value and whether change;
When described frequency setting value changes, judge whether a package group completes transmission;
When described package group completes transmission, be written into new described frequency setting value and adjust the frequency of described transmit clock signal according to loaded described frequency setting value; And
Described transmit clock signal after output frequency is adjusted;
Wherein, the frequency of described transmit clock signal is adjusted a system time signal-count by described clock counter and described frequency setting value;
The frequency of described transmit clock signal changes according to described frequency setting value.
The clock frequency control method thereof of 13. 1 kinds of bus interface, is characterized in that, described clock frequency control method thereof is in order in the middle of carrying out in a package group transmission, the frequency of modulation one transmit clock signal, and described clock frequency control method thereof comprises:
Judge whether a bus starts transmission command or data;
When described bus starts transmission command or data, judge whether a variable different time order output signal is established;
Establish when described variable different time order output signal,, according to the numerical value of a frequency control position, in the middle of multiple frequency setting values, select one; And
Make the frequency of described transmit clock signal be adjusted into the selected corresponding frequency of described frequency setting value.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106815155A (en) * | 2015-12-01 | 2017-06-09 | 英飞凌科技奥地利有限公司 | Data are accessed via different clocks |
| CN106815155B (en) * | 2015-12-01 | 2019-12-13 | 英飞凌科技奥地利有限公司 | Accessing data via different clocks |
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