CN105718402A - Programmable time sequence generator - Google Patents
Programmable time sequence generator Download PDFInfo
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- CN105718402A CN105718402A CN201610020516.1A CN201610020516A CN105718402A CN 105718402 A CN105718402 A CN 105718402A CN 201610020516 A CN201610020516 A CN 201610020516A CN 105718402 A CN105718402 A CN 105718402A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention provides a programmable time sequence generator. The programmable time sequence generator comprises a counter unit, an FIFO unit, a comparator unit and a latch unit. The counter unit and the FIFO unit are both connected to the comparator unit, and the FIFO unit and the comparator unit are both connected to the latch unit; The FIFO unit stores three sets of values, i.e. A, B and C, and the values of the sets A, B and C are read out from the FIFO unit firstly; The comparator unit compares an A value output by the FIFO unit with a counting value of the counter unit, and after the counter unit is cleared when the A value is equal to the counting value, currently output data is latched into the latch unit, and a calculation formula of the output data is that the current output data equals to (last output data and (not C)) or (B and C), wherein, when the currently output data is output data in an initial state, the last output data equals to 0; and then a next set of values of the sets A, B and C are read out from the FIFO unit. The programmable time sequence generator provided by the present invention is capable of preventing an output time sequence from being solidified and thus outputting any time sequence, and occupies very few CPU resources.
Description
Technical field
The present invention relates to a kind of programmable timing generator.
Background technology
IC and IC connects communication, and the sequential being required for observing an agreement could mutually send and receive data.So all can there be a lot of controller inside IC, such as IIC controller, SPI controller, lcd controller etc..Outfan at each controller can have a timing sequencer, but existing product is just fixing in the dust it when design, arises that the IC that can not support non-standard or upgraded version.Just have person in this case to select and simulate corresponding sequential with GPIO, but the resource of a lot of CPU can be taken, and frequency is run not high.
Summary of the invention
The technical problem to be solved in the present invention, is in that to provide a kind of programmable timing generator, can export arbitrary sequence by software arrangements, and account for cpu resource and few.
The present invention is achieved in that a kind of programmable timing generator, including a counter unit, a cell fifo, a comparator unit and a latch unit；
(1), described counter unit and cell fifo be all connected with comparator unit, described cell fifo and comparator unit are all connected with latch unit；
(2), described cell fifo deposits A, B, C tri-class value；
(3) inside described cell fifo, first read the value of A, B, C；
(4) A value that, cell fifo is exported by described comparator unit also compares with the count value of described counter unit, after counter unit being reset when equal, in current output data latch to latch unit, the computing formula of described output data is:
Currently export data=(last output data and (notC)) or (BandC)；Wherein, when current output data are the output data of original state, last output data=0；
(5) from FIFO, then read the value of next group A, B, C again, return to step (4), thus can realize the data that the output of appointment time is specified, just can reach the effect of programmable timing generator.
Further, described counter unit receives clock, runs the signal enabling and resetting, and described cell fifo receives the signal writing enable；
When being reset to high, described counter unit is set to-1, is emptied by described cell fifo simultaneously, and latch unit is set to 0；
When being reset to low and writing enable for, time high, the value of A, B and C being deposited in place's cell fifo when the rising edge of clock is come；When being reset to low and reading to enable as time low, when the decline at clock is prolonged next, cell fifo exports the data come at first；
When being reset to low and running enable for time high, described counter unit starts counting up, described comparator unit is by the A value contrast of the count value of described counter unit with the output of described cell fifo, if time equal, described counter unit is set to 0, the reading of cell fifo is enabled and is set to 1, described latch unit latches described output data, and allow cell fifo export the value of next group A, B, C, if unequal, FIFO read enable and is set to 0.
Further, described cell fifo is three FIFO compositions, and three FIFO deposit A, B and C value respectively, and A value is fiducial value, and B value is output valve, and C value is output enable value.
Present invention have the advantage that the timing sequencer of the present invention, including counter unit, cell fifo, comparator unit and latch unit, A, B, C that cell fifo is deposited tri-class value can configure on demand, so that the sequential of output will not be cured and export arbitrary sequence, and it is few to account for cpu resource.
Accompanying drawing explanation
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the Organization Chart of programmable timing generator of the present invention.
Fig. 2 is that programmable timing generator one of the present invention performs processes result schematic diagram.
Detailed description of the invention
As it is shown in figure 1, the programmable timing generator of the present invention, including a counter unit, a cell fifo, a comparator unit and a latch unit；
(1), described counter unit and cell fifo be all connected with comparator unit, described cell fifo and comparator unit are all connected with latch unit；
(2), described cell fifo deposits A, B, C tri-class value；When implementing, described cell fifo can be made up of three FIFO, and three FIFO deposit A, B and C value respectively, and wherein, A value is fiducial value, and B value is output valve, and C value is output enable value.
(3) inside described cell fifo, first read the value of A, B, C；
(4) A value that, cell fifo is exported by described comparator unit also compares with the count value of described counter unit, after counter unit being reset when equal, in current output data latch to latch unit, the computing formula of described output data is:
Currently export data=(last output data and (notC)) or (BandC)；Wherein, when current output data are the output data of original state, last output data=0；
(5) from FIFO, then read the value of next group A, B, C again, return to step (4), thus can realize the data that the output of appointment time is specified, just can reach the effect of programmable timing generator.
When implementing, as it is shown in figure 1, described counter unit receives clock, runs the signal enabling and resetting, described cell fifo receives the signal writing enable；
When being reset to high, described counter unit is set to-1, is emptied by described cell fifo simultaneously, and latch unit is set to 0；
When being reset to low and writing enable for, time high, the value of A, B and C being deposited in place's cell fifo when the rising edge of clock is come；When being reset to low and reading to enable as time low, when the decline at clock is prolonged next, cell fifo exports the data come at first；
When being reset to low and running enable for time high, described counter unit starts counting up, described comparator unit is by the A value contrast of the count value of described counter unit with the output of described cell fifo, if time equal, described counter unit is set to 0, the reading of cell fifo is enabled and is set to 1, described latch unit latches described output data, and allow cell fifo export the value of next group A, B, C, if unequal, FIFO read enable and is set to 0.
For example, when inputting two groups of data in cell fifo:
First group: fiducial value A=4, export enable value C=1, output valve B=1；
Second group: fiducial value A=2, export enable value C=2, output valve B=2.
As in figure 2 it is shown, when enabling position and being 1, start working in inside, 4 all after dates, exporting 1, after 2 all after dates, output valve is 3.
The timing sequencer of the present invention includes counter unit, cell fifo, comparator unit and latch unit, A, B, C that cell fifo is deposited tri-class value can configure on demand, so that the sequential of output will not be cured and export arbitrary sequence, and it is few to account for cpu resource.
Although the foregoing describing the specific embodiment of the present invention; but those familiar with the art is to be understood that; we are merely exemplary described specific embodiment; rather than for the restriction to the scope of the present invention; those of ordinary skill in the art, in the equivalent modification made according to the spirit of the present invention and change, should be encompassed in the scope of the claimed protection of the present invention.
Claims (3)
1. a programmable timing generator, it is characterised in that: include a counter unit, a cell fifo, a comparator unit and a latch unit；
(1), described counter unit and cell fifo be all connected with comparator unit, described cell fifo and comparator unit are all connected with latch unit；
(2), described cell fifo deposits A, B, C tri-class value；
(3) inside described cell fifo, first read the value of A, B, C；
(4) A value that, cell fifo is exported by described comparator unit also compares with the count value of described counter unit, after counter unit being reset when equal, in current output data latch to latch unit, the computing formula of described output data is:
Currently export data=(last output data and (notC)) or (BandC)；Wherein, when current output data are the output data of original state, last output data=0；
(5) from FIFO, then read the value of next group A, B, C again, return to step (4).
2. programmable timing generator according to claim 1, it is characterised in that: described counter unit receives clock, runs the signal enabling and resetting, and described cell fifo receives the signal writing enable；
When being reset to high, described counter unit is set to-1, is emptied by described cell fifo simultaneously, and latch unit is set to 0；
When being reset to low and writing enable for, time high, the value of A, B and C being deposited in place's cell fifo when the rising edge of clock is come；When being reset to low and reading to enable as time low, when the decline at clock is prolonged next, cell fifo exports the data come at first；
When being reset to low and running enable for time high, described counter unit starts counting up, described comparator unit is by the A value contrast of the count value of described counter unit with the output of described cell fifo, if time equal, described counter unit is set to 0, the reading of cell fifo is enabled and is set to 1, described latch unit latches described output data, and allow cell fifo export the value of next group A, B, C, if unequal, FIFO read enable and is set to 0.
3. programmable timing generator according to claim 1 and 2, it is characterised in that: described cell fifo is three FIFO compositions, and three FIFO deposit A, B and C value respectively, and A value is fiducial value, and B value is output valve, and C value is output enable value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610020516.1A CN105718402B (en) | 2016-01-13 | 2016-01-13 | Programmable timing generator |
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| CN201610020516.1A CN105718402B (en) | 2016-01-13 | 2016-01-13 | Programmable timing generator |
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| CN105718402A true CN105718402A (en) | 2016-06-29 |
| CN105718402B CN105718402B (en) | 2021-04-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112073472A (en) * | 2020-08-18 | 2020-12-11 | 浙江鸿城科技有限责任公司 | Soft zero clearing processing method for counter |
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| CN112073472A (en) * | 2020-08-18 | 2020-12-11 | 浙江鸿城科技有限责任公司 | Soft zero clearing processing method for counter |
| CN112073472B (en) * | 2020-08-18 | 2023-04-07 | 浙江鸿城科技有限责任公司 | Soft zero clearing processing method for counter |
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| CN105718402B (en) | 2021-04-20 |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |
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