CN105550151A

CN105550151A - High-efficiency serial bus control circuit

Info

Publication number: CN105550151A
Application number: CN201510888509.9A
Authority: CN
Inventors: 张则乐; 胡林军
Original assignee: CETC 41 Institute
Current assignee: CETC 41 Institute
Priority date: 2015-12-02
Filing date: 2015-12-02
Publication date: 2016-05-04
Anticipated expiration: 2035-12-02
Also published as: CN105550151B

Abstract

The invention discloses a high-efficiency serial bus control circuit, particularly relating to the field of communication control. The high-efficiency serial bus control circuit comprises a master equipment circuit and a slave equipment circuit; the master equipment circuit is provided with a serial bus chip selection signal, a serial bus clock signal, a serial bus data input signal, a serial bus data output signal, a serial bus clock output signal, a first completion signal and a CPU interconnection signal; the slave equipment circuit is provided with a slave equipment chip selection signal, a slave equipment clock signal, a slave equipment data input signal, a slave equipment data output signal, a slave equipment clock input signal and a second completion signal; the serial bus chip selection signal is connected with the slave equipment chip selection signal; the serial bus clock signal is connected with the slave equipment clock signal; the serial bus data input signal is connected with the slave equipment data output signal; the serial bus data output signal is connected with the slave equipment data input signal; and the serial bus clock output signal is connected with the slave equipment clock input signal.

Description

A kind of efficient serial bus controlling circduit

Technical field

The present invention relates to Control on Communication field, be specifically related to a kind of efficient serial bus controlling circduit.

Background technology

The kind of bus is a lot, divides, can be divided into computing machine (comprising peripheral hardware) bus, measurement and control bus and network communication bus by usable range; Divide by data mode, have bit parallel transmission bus and bit serial transmission bus; The data-bus width that parallel transfer bus transmits by it, can be divided into again 8,16 and 32 BITBUS network, etc.Regardless of which kind of bus, their acting in conjunction the template in computing machine or TT&C system or various equipment can be linked to be an entirety, to carry out message exchange to each other by public signal wire.In order to effectively, reliably carry out message exchange, bus protocols is called to a series of regulations that bus signals and transmission physical medium that is regular and that transmit these signals thereof do.The bus protocols ratified by a certain standardization body or recommend is certain bus standard.

The parallel bus that computing machine often uses has isa bus, pci bus.Isa bus has 62 signal wires and one to have the socket of 36 numbers lines to form by one, 23 address wires, 16 data lines, memory read/write line, IO read-write line, interrupt request line, DMA is had to ask line, DMA line of response, 14.31818MHz high-speed clock signal OSC, 4.77MHz clock signal of system, etc.The read-write of storer or IO is at least 4 system clock cycles, and therefore the data throughput of isa bus is up to 2.39MB/s.

Pci bus originates from microcomputer, become computer bus standard now, its frequency of operation is 33MHz, 66MHz, data bits is 32,64, transmission bandwidth reaches 132MB/s, 264MB/s, 528MB/s, had great improvement than isa bus, what adopt at present extensively is the pci bus of 32 33MHz.Pci bus signal as shown in Figure 1.System signal comprises reset signal RST# and clock signal clk.Arbitrating signals has bus application REQ# and bus grant signal GNT#.Interface control signal comprises the FRAME# signal that main equipment starts PCI, and main equipment gets out signal IRDY#, gets out signal TRDY# from equipment, stop data transfer signals STOP#, locking signal LOCK#, initialization apparatus selects signal IDSEL#, equipment choice signal DEVSEL#.PCI does not have the read-write in general data cycle, but adopts the read-write properties of command code formal definition pci cycle.Each pci cycle is started by main equipment, first clock period, and AD [31..0] Signal transmissions address information, the order of C/BE# [3..0] formation control, definition pci cycle.After second clock, AD [31..0] carries out data transmission, C/BE# [3..0] identification byte effective information.Parity signal is PAR.Error reporting signal has data parity check error reporting signal PERR#, system mistake report signal SERR#.In addition, look-at-me INTA#, INTB#, INTC#, INTD# is also had.

GPIB be a kind of between programmable instrument device, the international programmable instrument Digital Interface Standard that connects of instrument and computer inter.Gpib interface bus is a kind of bidirectional bus of asynchronous data transfer mode, adopts the reed-type plug of 24 pin.The information transmitted by cable between equipment has two classes, and a class is the information for interface system self-management; The another kind of information being the equipment interconnected by interface system and using.Gpib bus has 16 signal wires, wherein 8 is data line DIO1 ~ DIO8,3 communications link DAV data are effective, the unripe reception data of NRFD, NDAC data do not receive, and 5 root interface boundary of administration IFC interface clears, ATN note, SRQ services request, REN remote enable, EOI terminate or identify.

Based on the control system of parallel bus, between each wiring board and base plate, interconnect signal is more, generally has address/data lines, also has control line, causes pcb board to connect up complicated.Such as, when employing 32 pci buss, each wiring board at least needs 51 root interface signal wires, cause the wiring difficulty of pcb board to increase.In order to reduce pcb board wiring complexity, improve the reliability of system, the interconnect signal between wiring board can adopt universal serial bus.

Traditionally, the interface of PC and peripheral hardware is divided into serial ports and parallel port.Serial ports is generally used for connecting mouse and external Modem, and its data transmission rate is from every number of seconds kbps to hundreds of kbps.The data transmission rate of parallel port can reach 1MB per second, is generally used for connecting printer, scanner etc.

Traditional interface mode is when with Peripheral Interfaces such as keyboard, mouse, printer, Modem, and data rate is low, poor expandability, can not plug and play, cannot adapt to the develop rapidly of PC software and hardware.For above Problems existing, the USB (universal serial bus) that has been born again (UniversalSerialBus, be called for short USB), become to support general accepted standard on the computing machine of USB and peripheral hardware, keyboard, mouse, wideband multimedia equipment, scanner, printer and memory device etc. can have been supported.USB is a kind of USB (universal serial bus) of point-to-point communication, and the transmission speed provided has low speed 1.5Mbps, 12Mbps, high speed 480Mbps etc. are several at full speed.The shortcoming of USB system is that agreement is complicated, and need the support of operating system, the design difficulty of driver is higher.

Summary of the invention

The object of the invention is for interconnect signal between each wiring board of traditional control system based on parallel bus and base plate more, cause the deficiency that pcb board wiring reliability that is complicated, system is low, propose the master and slave circuit design of a kind of employing, comprise multipair main equipment circuit and from circuitry, by main equipment circuit with realize the efficient serial bus controlling circduit of the one of CPU to the control of multiple wiring board from circuitry.

The present invention specifically adopts following technical scheme:

A kind of efficient serial bus controlling circduit, comprise main equipment circuit and from circuitry, described main equipment circuit is provided with universal serial bus chip selection signal, universal serial bus clock signal, serial bus data input signal, serial bus data outputs signal, universal serial bus clock output signal, first settling signal and with CPU interconnect signal, describedly be provided with from equipment chip selection signal from circuitry, from equipment clock signal, from device data input signal, output signal from device data, from equipment clock input signal and the second settling signal, described universal serial bus chip selection signal is connected with from equipment chip selection signal, described universal serial bus clock signal is connected with from equipment clock signal, described serial bus data input signal is connected with outputing signal from device data, described serial bus data output signal is connected with from device data input signal, described universal serial bus clock output signal is connected with from equipment clock input signal.

Preferably, describedly CPU chip selection signal, CPU read signal, CPU write signal, cpu address signal, cpu data signal, cpu clock input signal and CPU waiting signal is comprised with CPU interconnect signal.

Preferably, described main equipment circuit comprises idle pulley, main sending mode and main receiving mode, describedly comprises idle pulley, from receiving mode with from sending mode from circuitry.

Preferably, described universal serial bus chip selection signal is output signal, Low level effective, and described universal serial bus clock signal is output signal, and described universal serial bus clock output signal controls to produce Control timing sequence from circuitry.

Preferably, described is input signal with the CPU chip selection signal of CPU interconnect signal, described CPU read signal is input signal, described CPU write signal is input signal, described cpu address signal is input signal, described cpu data signal is input/output signal, and described CPU waiting signal is output signal, and described cpu clock input signal controls main equipment circuit generation Control timing sequence.

The beneficial effect that the present invention has is: can realize the efficient control of CPU to multiple wiring board, can reduce the quantity of interconnect signal between system neutral road plate and base plate, facilitate the wiring of PCB, improves the reliability of system.

Accompanying drawing explanation

Fig. 1 pci bus signal.

A kind of efficient serial bus controlling circduit wiring board connection diagram of Fig. 2.

A kind of efficient serial bus controlling circduit theory diagram of Fig. 3.

Fig. 4 main equipment, from equipment connection schematic diagram.

Fig. 5 universal serial bus write order sequential chart.

Fig. 6 universal serial bus read command sequential chart.

The main sending mode sequential chart of Fig. 7 universal serial bus.

The main receiving mode sequential chart of Fig. 8 universal serial bus.

Universal serial bus main sending mode sequential chart when Fig. 9 arranges delay register.

Universal serial bus main receiving mode sequential chart when Figure 10 arranges delay register.

Embodiment

Below in conjunction with the drawings and specific embodiments, the specific embodiment of the present invention is described further:

As in Figure 2-4, a kind of efficient serial bus controlling circduit, comprise main (Master) circuitry and from (Slaver) circuitry, main equipment circuit is provided with universal serial bus chip selection signal (SCS), universal serial bus clock signal (SCLK), serial bus data input signal (SDI), serial bus data output signal (SDO), universal serial bus clock output signal (CLKOUT), first settling signal (/DONE) and with CPU interconnect signal, be provided with from equipment chip selection signal (S_SCS) from circuitry, from equipment clock signal (S_SCLK), from device data input signal (S_SDI), from device data output signal (S_SDO), from equipment clock input signal (S_CLK) and the second settling signal (/S_DONE), universal serial bus chip selection signal is connected with from equipment chip selection signal, universal serial bus clock signal is connected with from equipment clock signal, serial bus data input signal is connected with outputing signal from device data, serial bus data output signal is connected with from device data input signal, universal serial bus clock output signal is connected with from equipment clock input signal.

Describedly comprise CPU chip selection signal (/CS), CPU read signal (/RD), CPU write signal (/WR), cpu address signal (A [1..0]), cpu data signal (D [x..0]), cpu clock input signal (CLK) and CPU waiting signal (/WAIT) with CPU interconnect signal, wherein x+1 is the figure place of data bus, can be 8,16,24,32,64.

Main equipment circuit comprises idle pulley, main sending mode and main receiving mode, comprises idle pulley, from receiving mode with from sending mode from circuitry.

Universal serial bus chip selection signal is output signal, Low level effective, and clock signal is output signal, and clock output signal controls to produce Control timing sequence from circuitry.

Be input signal with the CPU chip selection signal of CPU interconnect signal, CPU read signal is input signal, CPU write signal is input signal, cpu address signal is input signal, cpu data signal is input/output signal, CPU waiting signal is output signal, and cpu clock input signal controls main equipment circuit generation Control timing sequence.The instruction of current execution is inserted latent period for asking CPU during low level by CPU waiting signal (/WAIT), for NMOSFET type circuit, drain electrode output circuit structure is opened in suggestion employing, external pull-up resistor need be connect, for NPN type triode circuit, suggestion adopts open collector output circuit structure, need connect external pull-up resistor.

The first settling signal (/DONE) that main equipment circuit produces, Low level effective.From the second settling signal (/S_DONE) that circuitry produces, Low level effective.For NMOSFET type circuit, drain electrode (opendrain) output circuit structure is opened in/DONE signal and/S_DONE signal suggestion employing, need connect external pull-up resistor.For NPN type triode circuit ,/DONE signal and the suggestion of/S_DONE signal adopt open collector (opencollector) output circuit structure, need connect external pull-up resistor.At this moment, can by organize more universal serial bus /DONE signal or/S_DONE signal link together.

As shown in Figure 5, be universal serial bus write order sequential chart of the present invention, for 7 bit addressing spaces, 8 bit data.The write operation of universal serial bus, forms write command byte by the write order of the addresses of 7 and 1, and the data of writing of a byte or multiple byte are below formed.First SCS becomes low level, and expression will be read and write universal serial bus.After SCS becomes low level, SCLK sends 8 pulses, and rising edge is effective, and SDO sends the addressable address of 7 and the write order of 1, and write order low level represents.Then SCLK sends 8 pulses, and rising edge is effective, for data write operation, and the output data word of SDO displacement simultaneously joint.For the write operation of n byte, SCLK sends n and is multiplied by 8 shift clock pulses.After completing write order, SCS signal is set to high level.Example shown in Fig. 5 is toward in the 0x78 of universal serial bus address, writes 0xaa and 0x55 successively.

As shown in Figure 6, be universal serial bus read command sequential chart, for 7 bit addressing spaces, 8 bit data.The read operation of universal serial bus, forms read command byte by the read command of the addresses of 7 and 1, and below a byte or multiple byte read data form.First SCS becomes low level, and expression will be read and write universal serial bus.After SCS becomes low level, SCLK sends 8 pulses, and rising edge is effective, and SDO sends the addressable address of 7 and the read command of 1, and read command high level represents.Then SCLK sends 8 pulses, and rising edge is effective, and for data reading operation, SDI inputs shifted data byte simultaneously.For the write operation of n byte, SCLK sends n and is multiplied by 8 shift clock pulses.After completing read command, SCS signal is set to high level.Example shown in Fig. 6 is from the 0x78 of universal serial bus address, reads in 0xaa and 0x55 successively.

Similar, universal serial bus of the present invention can carry out read-write operation to 15 bit addressing spaces, 16 bit data, also read-write operation can be carried out to 23 bit addressing spaces, 24 bit data, also read-write operation can be carried out to 31 bit addressing spaces, 32 bit data, also read-write operation can be carried out to 63 bit addressing spaces, 64 bit data.

When employing 8 bit CPU interface, this Serial Bus Implementers is 8 bit patterns, and namely each operation steps of universal serial bus produces 8 serial clocks, and each register of series bus controller is designed to 8.Internal instruction register comprises a 7 bit address A6 ~ A0 and Read-write Catrol position expression will operate which address, is read operation or write operation.7 bit address can addressing 128 address spaces.When Read-write Catrol position is 0, expression will carry out write operation, represents and will carry out read operation when being 1.

When employing 16 bit CPU interface, this Serial Bus Implementers is 16 bit patterns, and namely each operation steps of universal serial bus produces 16 serial clocks, and the register design of series bus controller is 16.Internal instruction register comprises a 15 bit address A14 ~ A0 and Read-write Catrol position addressing space is 32k, i.e. 32768 unit.

When employing 32 bit CPU interface, this Serial Bus Implementers is 32 bit patterns, and namely each operation steps of universal serial bus produces 32 serial clocks, and the register design of series bus controller is 32.Internal instruction register comprises a 31 bit address A30 ~ A0 and Read-write Catrol position addressing space is 2G, i.e. 2147483648 unit.

The CPU access port of series bus controller is 4, and need A1 and A0 two address wires to carry out addressing, its register gathers as shown in table 1.The design of series bus controller of the present invention is described with 8 bit patterns below.

Register name	Register functions	A1	A0	Read-write type
					Status register	State machine information	0	0	Read
Delay register	Control time delay	0	1	Read/write
					Data register	Command/data	1	0	Read/write 4-->
Control register	Control/state	1	1	Read/write

Table 1

The data bit of status register is as shown in table 2, is read-only register, represents the state machine information of series bus controller with 8 bit S.

Table 2

The data bit of delay register is as shown in table 3, is read-write register, and control the time delay of series bus controller with 8 bit T, default to numerical value 0, its actual delay time is KT, K is constant, is certain time cycle.

Table 3

The data layout of order is as shown in table 4, represents the addressable address of universal serial bus, with 1 Read-write Catrol position with 7 bit A representing that this instruction to carry out read operation or write operation, is that 0 expression will carry out write operation, is that 1 expression will carry out read operation.

Table 4

The order that the storage of command/data register will send, or the data that will read and write.During memory command, its data bit is as shown in table 4.Storage to read and write data time, its data bit is as shown in table 5, is read-write register, the data representing the data that will write serial bus slave with 8 bit D and read from serial bus slave.In the implementation of the every bar instruction of universal serial bus, during CPU first time write order/data register, order data is written in inner order register, write data into during write order/data register afterwards in inner output register, from the input register of inside, during read command/data register, obtain the data that will read.

Table 5

The data bit of write control register is as shown in table 6, only has lowest order effective.Write 0, is set to low level by universal serial bus SCS signal, and write 1, is set to high level by universal serial bus SCS signal.

Table 6

The data bit of read control register is as shown in table 7.Lowest order represents the state of universal serial bus SCS signal, reads 1 when SCS signal is high level, reads 0 when SCS signal is low level.Its high 7 addressable address storing universal serial bus, can read this numerical value.

Table 7

Series bus controller (serialbuscontroller) has Three models, i.e. idle pulley (idlemode), main sending mode (mastertransmittermode), main receiving mode (masterreceivermode).Series bus controller state machine information can be obtained by read status register.

Idle pulley represents that master controller is in idle condition, and at this moment the value of status register is hexadecimal 0xE8.

When this serial operation instruction is for writing type, master controller is in main sending mode, and the value of status register is respectively 0xA0,0xE0,0xA2,0xE2.When series bus controller is in transmission coomand mode, the value of status register is 0xA0 ,/DONE signal is high level.Order is sent, and after the time delay that generation delay register is specified, the value of status register becomes 0xE0, and simultaneously/DONE signal is set to low level.When series bus controller is in transmission data mode, the value of status register is that 0xA2 ,/DONE signal is set to high level.Data are sent, and after the time delay that generation delay register is specified, the value of status register becomes 0xE2, and/DONE signal is set to low level.

When this serial operation instruction is for reading type, master controller is in main receiving mode, and the value of status register is respectively 0xA0,0xE1,0xA3,0xE3.When series bus controller is in transmission address state, the value of status register is 0xA0 ,/DONE signal is high level.Order is sent, and after the time delay that generation delay register is specified, the value of status register becomes 0xE1, and simultaneously/DONE signal is set to low level.When series bus controller is in reception data mode, the value of status register is that 0xA3 ,/DONE signal is set to high level.Data receiver is complete, and after the time delay that generation delay register is specified, the value of status register becomes 0xE3, and/DONE signal is set to low level.

Serial bus slave (serialbusslavedevice) has Three models, namely idle pulley (idlemode), from sending mode (slavetransmittermode), from receiving mode (slavereceivermode).Status register storage string row bus is from equipment state machine information.The design philosophy of serial bus slave of the present invention is described with 8 bit patterns below.

Idle pulley represents from equipment and is in idle condition, and at this moment the value of status register is hexadecimal 0xF8.

When this serial operation instruction is for writing type, be in from receiving mode from equipment, the value of status register is respectively 0xB1,0xF1,0xB3,0xF3,0xB5.When becoming low level to S_SCS signal wire from high level from equipment Inspection ,/S_DONE signal wire is set to high level.When being in reception coomand mode from equipment, the value of status register is 0xB1.Order receives, and the value of status register becomes 0xF1, and simultaneously/S_DONE signal wire is set to low level.When being in reception data mode from equipment, the value of status register is that 0xB3 ,/S_DONE signal wire is set to high level.Data receiver is complete, and the value of status register becomes 0xF3, and/S_DONE signal wire is set to low level.When S_SCS signal wire becomes high level, this command reception is complete, is in execution command status from equipment, and the value of status register becomes 0xB5, and/S_DONE signal wire is set to high level.Instruction is finished, and is in idle condition from equipment, and the value of status register becomes 0xF8, and/S_DONE signal wire is set to low level.

When this serial operation instruction is for reading type, be in from sending mode from equipment, the value of status register is respectively 0xB1,0xB4,0xF0,0xB2,0xF2.When becoming low level to S_SCS signal wire from high level from equipment Inspection ,/S_DONE signal wire is set to high level.When being in receiver address state from equipment, the value of status register is 0xB1.Address accept is complete, performs this instruction, and the value of status register becomes 0xB4.After DSR, the value of status register becomes 0xF0, and simultaneously/S_DONE signal wire is set to low level.When being in transmission data mode from equipment, the value of status register is that 0xB2 ,/S_DONE signal wire is set to high level.Data are sent, and the value of status register becomes 0xF2, and simultaneously/S_DONE signal wire is set to low level.When becoming high level to S_SCS signal wire from low level from equipment Inspection, the value of status register becomes 0xF8, and/S_DONE signal wire is set to high level.

As shown in Figure 7, be the main sending mode sequential chart of universal serial bus.Wherein, CLK ,/CS ,/RD ,/WR ,/WAIT, A [1..0], D [7..0] ,/DONE are series bus controller and cpu i/f signal.SCS, SCLK, SDI, SDO are series bus controller end signal, and STATUS is series bus controller status register.S_SCS, S_SCLK, S_SDI, S_SDO are serial bus slave end signal, and/S_DONE is serial bus slave output signal, and can detect its state by CPU, S_STATUS is serial bus slave status register.

The 0x78 address location of CPU serially bus writes 0xAA and 0x55 successively in this example.When series bus controller is in the free time, the value of status register is 0xE8.Control register write 0x00, the SCS signal of CPU serially bus controller is set to low level, and start the main transmit operation of a universal serial bus, the value of status register becomes 0xA0, and/DONE signal is set to high level, and/WAIT signal is set to high level.CPU serially bus controller command/data register write 0xF0, these data are as demanded storage in the order register of inside, and its lowest order is 0, and therefore this order specifies a write operation.SCLK produces 8 time clock, and SDO Serial output order 0xF0, SDO export complete, and the value of status register becomes 0xE0, and simultaneously/DONE signal is set to low level, represents last step end of operation.CPU serially bus controller command/data register write order after, just can judge whether last operation steps completes by the state of circulation readings/DONE signal or the/state of S_DONE signal or the value of status register, operate until last operation steps carries out next step again after completing.CPU serially bus controller command/data register write 0xAA, the value of status register becomes 0xA2, and/DONE signal is set to high level.SCLK produces 8 time clock, and SDO serial output data 0xAA, SDO export complete, and the value of status register becomes 0xE2, and simultaneously/DONE signal is set to low level, represents last step end of operation.CPU serially bus controller command/data register write data after, just can judge whether last operation steps completes by the state of circulation readings/DONE signal or the/state of S_DONE signal or the value of status register, operate until last operation steps carries out next step again after completing.If there are next data to export, such as, CPU serially bus controller command/data register write 0x55, the value of status register becomes 0xA2, and/DONE signal is set to high level.SCLK produces 8 time clock, and SDO serial output data 0x55, SDO export complete, and the value of status register becomes 0xE2, and simultaneously/DONE signal is set to low level, represents last step end of operation.CPU serially bus controller command/data register write data after, just can judge whether last operation steps completes by the state of circulation readings/DONE signal or the/state of S_DONE signal or the value of status register, operate until last operation steps carries out next step again after completing.After data are sent, control register write 0x01, the SCS signal of CPU serially bus controller is set to high level, and the value of status register becomes 0xE8, and/DONE signal is set to high level, and this has operated.

When series bus controller is main sending mode, serial bus slave is in from receiving mode.When serial bus slave is in the free time, the value of status register is 0xF8.Serial bus slave detect S_SCS signal become low after, the value of status register becomes 0xB1, and/S_DONE signal is set to high level.S_SCLK receives 8 time clock, S_SDI serial received order data, be that 0xF0, S_SDI input is complete in this example, the value of status register becomes 0xF1, and simultaneously/S_DONE signal is set to low level, represents last step end of operation.SCLK then receives 8 time clock, 0xB3 is become in the value of the rising edge status register of the 1st time clock, / S_DONE signal is set to high level, S_SDI Serial data receiving is complete, numerical value is 0xAA in this example, the value of status register becomes 0xF3, and simultaneously/S_DONE signal is set to low level, represents last step end of operation.If there are next data to input, S_SCLK receives 8 time clock, 0xB3 is become in the value of the rising edge status register of the 1st time clock, / S_DONE signal is set to high level, S_SDI Serial data receiving is complete, and numerical value is 0x55 in this example, and the value of status register becomes 0xF3, simultaneously/S_DONE signal is set to low level, represents last step end of operation.After serial bus slave detects that S_SCS signal becomes height, general/S_DONE signal is set to high level, represents that this instruction receives.The value of status register becomes 0xB5, represents and is performing this instruction.After executing this instruction, general/S_DONE signal is set to low level, and serial bus slave is in idle condition, and the value of status register becomes 0xF8.

As shown in Figure 8, be the main receiving mode sequential chart of universal serial bus, CPU reads 0xAA and 0x55 successively from the 0x78 address location of universal serial bus in this example.When series bus controller is in the free time, the value of status register is 0xE8.Control register write 0x00, the SCS signal of CPU serially bus controller is set to low level, and start main receptions of universal serial bus and operate, the value of status register becomes 0xA0, and/DONE signal is set to high level, and/WAIT signal is set to high level.CPU serially bus controller command/data register write 0xF1, these data are as demanded storage in the order register of inside, and its lowest order is 1, and therefore this order specifies a read operation.SCLK produces 8 time clock, and SDO Serial output 0xF1, SDO export complete, and the value of status register becomes 0xE1, and simultaneously/DONE signal is set to low level, represents last step end of operation.CPU serially bus controller command/data register write order after, just can judge whether last operation steps completes by the state of circulation readings/DONE signal or the/state of S_DONE signal or the value of status register, operate until last operation steps carries out next step again after completing.CPU reads the command/data register of series bus controller, and the value of status register becomes 0xA3, and/DONE signal is set to high level, and/WAIT signal is set to low level, represents and inserts latent period.SCLK produces 8 time clock, SDI serial input data 0xAA, SDI input is complete, the value of status register becomes 0xE3, D [7..0] data line exports 0xAA ,/WAIT signal and is set to high level, and simultaneously/DONE signal is set to low level, represent last step end of operation, at this moment CPU completes the command/data register manipulation reading series bus controller.If need to read next data, CPU reads the command/data register of series bus controller, and the value of status register becomes 0xA3, and/DONE signal is set to high level, and/WAIT signal is set to low level, represents and inserts latent period.SCLK produces 8 time clock, SDI serial input data 0x55, SDI input is complete, the value of status register becomes 0xE3, D [7..0] data line exports 0x55 ,/WAIT signal and is set to high level, and simultaneously/DONE signal is set to low level, represent last step end of operation, at this moment CPU completes the command/data register manipulation reading series bus controller.After data receiver, control register write 0x01, the SCS signal of CPU serially bus controller is set to height, and the value of status register becomes 0xE8, and/DONE signal is set to high level, and this has operated.

When series bus controller is main receiving mode, serial bus slave is in from sending mode.When serial bus slave is in the free time, the value of status register is 0xF8.Serial bus slave detect S_SCS signal become low after, the value of status register becomes 0xB1, and/S_DONE signal is set to high level.S_SCLK receives 8 time clock, S_SDI serial received order data, 0xF1 in this example, S_SDI input is complete, and the value of status register becomes 0xB4, represents that serial bus slave is in the data preparing to read, after getting out the data that will read, the value of status register becomes 0xF0, and simultaneously/S_DONE signal is set to low level, represents last step end of operation.SCLK then receives 8 time clock, 0xB2 is become in the value of the rising edge status register of the 1st time clock, / S_DONE signal is set to high level, S_SDO serial data is sent, 0xAA in this example, the value of status register becomes 0xF2, and simultaneously/S_DONE signal is set to low level, represents last step end of operation.If there are next data to export, S_SCLK receives 8 time clock, 0xB2 is become in the value of the rising edge status register of the 1st time clock, / S_DONE signal is set to high level, S_SDO serial data is sent, and is 0x55 in this example, and the value of status register becomes 0xF2, simultaneously/S_DONE signal is set to low level, represents last step end of operation.After serial bus slave detects that S_SCS signal becomes height, general/S_DONE signal is set to high level, and represent that this instruction is finished, serial bus slave is in idle condition, and the value of status register becomes 0xF8.

As shown in Figure 9, for arranging delay register universal serial bus main sending mode sequential chart time.As shown in Figure 10, for arranging delay register universal serial bus main receiving mode sequential chart time.The value arranging delay register is T, then the actual time delay time is KT, K is constant, is certain time cycle.In main sending mode, in fact 0xA0 and the 0xA2 state of series bus controller is extended the KT time respectively, that is, the KT time has been postponed in the generation of 0xE0 and 0xE2 state and/DONE settling signal respectively.In main receiving mode, in fact 0xA0 and the 0xA3 state of series bus controller is extended the KT time respectively, that is, the KT time has been postponed in the generation of 0xE1 and 0xE3 state and/DONE settling signal and/WAIT signal rising edge respectively.This is when whether each step of CPU use/DONE input completes, and consider that the process time delay of serial bus slave is significant, the delay time of setting is greater than the response time of serial bus slave.

The simplest circuit form of this series bus controller is only reservation two and the register of cpu i/f, namely retains command/data register and control register, removes status register, delay register.At this moment CPU can detect/state of DONE signal or/S_DONE signal to be to control each operation steps of series bus controller.

When SCS, the SCLK of this universal serial bus, SDI, SDO ,/S_DONE signal adopt difference output form, there is good anti-common mode interference ability, can be used for Long line transmission.At this moment can not transmit CLKOUT signal, serial bus slave uses local clock signal.The signal that universal serial bus transmits is SCS ,/SCS, SCLK ,/SCLK, SDI ,/SDI, SDO ,/SDO ,/S_DONE, S_DONE.At the transmitting terminal of signal, use differential driver, change single-ended signal into differential signal, at the receiving end of signal, use differential receiver, change differential signal into single-ended signal.At this moment this universal serial bus can be used for the transmission of inter-system data, because this universal serial bus have employed synchronous data transfer mode, therefore greatly improves than the speed of the asynchronous serial transmission modes such as RS232.

Be illustrate the design philosophy of universal serial bus main equipment of the present invention and serial bus slave and circuit sequence with 8 bit patterns in instructions, can be easy to be generalized to 16,24,32,64 bit-serial bus control system.Adopt this universal serial bus of High-speed Digital Circuit Design, frequency of operation is more than 100MHz, and the data exchange rate of universal serial bus main equipment and serial bus slave is high.Multipair universal serial bus can concurrent working.When there being many group universal serial bus in system, the data throughput of system is high.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited in above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement also should belong to protection scope of the present invention.

Claims

1. an efficient serial bus controlling circduit, it is characterized in that, comprise main equipment circuit and from circuitry, described main equipment circuit is provided with universal serial bus chip selection signal, universal serial bus clock signal, serial bus data input signal, serial bus data outputs signal, universal serial bus clock output signal, first settling signal and with CPU interconnect signal, describedly be provided with from equipment chip selection signal from circuitry, from equipment clock signal, from device data input signal, output signal from device data, from equipment clock input signal and the second settling signal, described universal serial bus chip selection signal is connected with from equipment chip selection signal, described universal serial bus clock signal is connected with from equipment clock signal, described serial bus data input signal is connected with outputing signal from device data, described serial bus data output signal is connected with from device data input signal, described universal serial bus clock output signal is connected with from equipment clock input signal.

2. a kind of efficient serial bus controlling circduit as claimed in claim 1, it is characterized in that, describedly comprise CPU chip selection signal, CPU read signal, CPU write signal, cpu address signal, cpu data signal, cpu clock input signal and CPU waiting signal with CPU interconnect signal.

3. a kind of efficient serial bus controlling circduit as claimed in claim 1 or 2, it is characterized in that, described main equipment circuit comprises idle pulley, main sending mode and main receiving mode, describedly comprises idle pulley, from receiving mode with from sending mode from circuitry.

4. a kind of efficient serial bus controlling circduit as claimed in claim 1 or 2, it is characterized in that, described universal serial bus chip selection signal is output signal, Low level effective, described universal serial bus clock signal is output signal, and described universal serial bus clock output signal controls to produce Control timing sequence from circuitry.

5. a kind of efficient serial bus controlling circduit as claimed in claim 1 or 2, it is characterized in that, described is input signal with the CPU chip selection signal of CPU interconnect signal, described CPU read signal is input signal, described CPU write signal is input signal, and described cpu address signal is input signal, and described cpu data signal is input/output signal, described CPU waiting signal is output signal, and described cpu clock input signal controls main equipment circuit generation Control timing sequence.