CN100483377C - Asynchronous bridge and data transmission - Google Patents
Asynchronous bridge and data transmission Download PDFInfo
- Publication number
- CN100483377C CN100483377C CNB2006100608277A CN200610060827A CN100483377C CN 100483377 C CN100483377 C CN 100483377C CN B2006100608277 A CNB2006100608277 A CN B2006100608277A CN 200610060827 A CN200610060827 A CN 200610060827A CN 100483377 C CN100483377 C CN 100483377C
- Authority
- CN
- China
- Prior art keywords
- asynchronous
- interface
- signal
- data
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Abstract
A asynchronous bridge consists of asynchronous slave interface for emitting transmission request signal, secondary synchronous unit for secondary-synchronizing said transmission request signal, asynchronous master interface for setting up bus transmission of the second clock domain, two-way storage with its one end being connected to asynchronous slave interface and another end being connected to asynchronous master interface for storing data signal of bus burst transmission. Its data transmitting method is also disclosed.
Description
Technical field
The present invention relates to chip design art, exactly, relate to the asynchronous bridge between the chip internal different clock-domains and use asynchronous bridge to carry out the method for data transmission.
Background technology
At present SOC (System On Chip, SOC (system on a chip)) in the chip, commonplace employing the design architecture of double-core or multinuclear, be the inside of SOC chip simultaneously integrated two or more processors, for example arm processor and dsp processor, usually adopt AMBA (Advanced Microcontroller Bus Architecture between the different processors, Advanced Microcontroller Bus Architecture) (the Advanced High-performance Bus of the AHB in the standard, Advanced High-performance Bus) bus links to each other, the AHB interfacing equipment that can visit the other side between the processor by ahb bus.But because different processor is generally operational in different clock zones, so clock frequency difference on the ahb bus, can not directly conduct interviews, but need carry out synchronous conversion between the ahb bus asynchronous clock domain earlier, this just need finish by the AHB2AHB asynchronous bridge.
The AHB2AHB asynchronous bridge has two AHB interfaces, wherein AHB slave unit interface (AHBSLAVE) is the bus input port, it receives from the bus transfer of clock zone 1 as the main equipment ARM nuclear of ARM clock zone, after inner synchronous conversion, become the ahb bus transmission of clock zone 2, export through AHB host device interface (AHB MASTER) as the DSP clock zone.
In the double-core system as shown in Figure 1, two such AHB2AHB asynchronous bridges have been used.Wherein, link of the synchronous conversion of the AHB1 bus transfer of ARM nuclear, become the ahb bus transmission of DSP clock zone, finish visit DSP clock zone AHB slave unit through asynchronous bridge 1; Similarly, link of the synchronous conversion of the AHB2 bus transfer of DSP nuclear, become the ahb bus transmission of ARM clock zone, finish visit ARM clock zone AHB slave unit through asynchronous bridge 2.
With AHB2AHB asynchronous bridge 1 is example, the prior art principle of work is as follows, after the AHB slave unit interface of asynchronous bridge 1 receives ARM clock zone bus transfer, AHB slave unit interface side state machine is deposited this transmission (control signal that is about on the ahb bus is deposited), sends transmission requests to AHB host device interface side then.
Owing to cross over different clock-domains, this transfer request signal is synchronous by two-stage, at the DSP clock zone, after host device interface side state machine receives this transmission requests after synchronously, according to the transmission of the control signal of having deposited on DSP clock zone reconstruction ahb bus, the AHB slave unit of visit DSP clock zone;
After visit finished, AHB host device interface side state machine sent the end of transmission (EOT) response to AHB slave unit interface side.Same, this response signal also by two-stage synchronously after, be converted to ARM clock zone signal;
After AHB slave unit interface side state machine receives the response signal of end of transmission (EOT), finish this transmission, then transmit next time, perhaps enter idle condition.
But for ahb bus burst (Burst) transmission, asynchronous bridge is to each action (beat) in the transmission in this scheme, all will through depositing-ask-rebuild transmission (newly clock zone)-such process of response-end, in other words, exactly the ahb bus burst transfer all is converted to single (single) transmission and handles, can not really support burst transfer.This processing mode causes bus efficiency low excessively, and bus bandwidth when having had a strong impact on the cross clock domain transmission when data throughout between the double-core is big, will be called the bottleneck of system especially.
Summary of the invention
The object of the invention is to provide a kind of asynchronous bridge and communication means thereof, can support the ahb bus burst transfer of cross clock domain, thereby promotes bus efficiency.
Asynchronous bridge provided by the invention comprises: asynchronous from interface, and detect and send transfer request signal when having bus transfer in first clock zone; The secondary lock unit, the synchronous described transfer request signal of secondary; Asynchronous main interface receives the transfer request signal of secondary after synchronously, sets up the bus transfer in second clock territory; Ovonic memory, described ovonic memory one end asynchronously is connected from interface with described, and the other end is connected the data-signal during the memory bus burst transfer with described asynchronous main interface;
When burst transfer is burst when reading transport-type, described asynchronous main interface writes data-signal in ovonic memory, describedly asynchronously reads described data-signal from interface from described ovonic memory; Or be burst when writing transport-type when burst transfer, and describedly asynchronously to ovonic memory, writing data-signal from interface, described asynchronous main interface is read described data-signal from described ovonic memory.
Described asynchronous main interface sends answer signal after the bus transfer in second clock territory finishes; The synchronous described answer signal of described secondary lock unit secondary; Describedly asynchronously receive the answer signal of secondary after synchronously, finish the bus transfer of first clock zone from interface.
Described ovonic memory is FIFO or two-port RAM.
Described FIFO comprises write data FIFO and read data FIFO.
Use asynchronous bridge provided by the invention carries out the method for data transmission, wherein said asynchronous bridge comprises asynchronous from interface, secondary lock unit, asynchronous main interface and ovonic memory, this method comprises the steps: asynchronously from interface the control signal on the slave unit interface side bus to be deposited, send transfer request signal, determine that according to described control signal transport-type is burst when reading to transmit, and waits for reading of data; It is synchronous that the secondary lock unit carries out secondary to described transfer request signal; Transfer request signal after asynchronous main interface reception secondary is synchronous determines that according to described control signal of depositing transport-type is that transmission is read in burst; Asynchronous main interface is set up burst in the host device interface side and is read transmission, writes data-signal in ovonic memory; Asynchronously from ovonic memory, read described data-signal, utilize the described data-signal of described slave unit interface side bus transfer from interface.
Described asynchronous reading from ovonic memory from interface also comprises before the described data-signal: asynchronously detect from interface that the storage data have surpassed predetermined threshold value the ovonic memory.
Described asynchronous reading from ovonic memory from interface also comprises before the described data-signal: asynchronous main interface sends answer signal after end of transmission (EOT) is read in the burst of host device interface side; It is synchronous that the secondary lock unit carries out secondary to described response signal; Asynchronously receive the response signal of secondary after synchronously from interface.
Use asynchronous bridge provided by the invention carries out the method for data transmission, wherein said asynchronous bridge comprises asynchronous from interface, secondary lock unit, asynchronous main interface and ovonic memory, this method comprises the steps: asynchronously from interface the control signal on the slave unit interface side bus to be deposited, send transfer request signal, determine that according to described control signal transport-type is that when transmission, the data-signal in ovonic memory on the write bus are write in burst; It is synchronous that the secondary lock unit carries out secondary to described transfer request signal; Asynchronous main interface receives the transfer request signal of secondary after synchronously, determines that according to described control signal of depositing transport-type is burst when writing transmission, waits for reading of data; Asynchronous main interface detects when the storage data have surpassed predetermined threshold value in the ovonic memory, reads described data-signal from ovonic memory, sets up burst in the host device interface side and writes transmission.
The host device interface pleurapophysis send out write end of transmission (EOT) after, comprise the steps: that further asynchronous main interface sends answer signal; It is synchronous that the secondary lock unit carries out secondary to described response signal; Asynchronously receive the response signal of secondary after synchronously, stop write data signal in ovonic memory, finish slave unit interface side bus transfer from interface.
With prior art the processing mode that burst transfer is converted into single transmission is compared, reading and writing data when the present invention program keeps in the ahb bus burst transfer by adopt ovonic memory in asynchronous bridge, realized the support of the ahb bus burst transfer of cross clock domain has been improved bus efficiency greatly.
Description of drawings
Fig. 1 is a cross clock domain system architecture synoptic diagram in the prior art scheme;
Fig. 2 is an asynchronous bridge structural representation among the present invention;
Fig. 3 is asynchronous from the Interface status transition diagram in the asynchronous bridge shown in Figure 2;
Fig. 4 is an asynchronous main interface state transition graph in the asynchronous bridge shown in Figure 2;
Fig. 5 is an asynchronous bridge workflow synoptic diagram shown in Figure 2.
Embodiment
The invention provides a kind of asynchronous bridge and communication means thereof, the ahb bus burst transfer need be converted to single transmission with asynchronous bridge in the solution prior art and handle, thereby cause the low excessively problem of bus efficiency.The present invention has additional ovonic memory in asynchronous bridge, because moment of bus is only handled a transmission (read transmission or write transmission), read-write operation can not take place simultaneously in the burst transfer, therefore only need an ovonic memory just can satisfy the demand, described ovonic memory one end is connected from interface with asynchronous, the other end is connected with asynchronous main interface, data-signal when being used to store the ahb bus burst transfer, described asynchronous from interface and described asynchronous main interface by described ovonic memory is read and write control, finish the ahb bus burst transfer.
Below in conjunction with accompanying drawing the present invention program is done further to set forth, see also shown in Figure 2ly, asynchronous bridge 5 provided by the invention comprises asynchronous from interface 51, asynchronous main interface 52, secondary SYN register 53, secondary SYN register 54 and write data FIFO (pushup storage) 55 and read data FIFO56.Wherein asynchronously be positioned at hclks clock zone (AHB SLAVE side place clock zone) from interface 51, asynchronous main interface 52 is positioned at hclkm clock zone (AHB MASTER side place clock zone); Write data FIFO55 is an end with read data FIFO56 and is connected from interface 51 with asynchronous, and the other end is connected with asynchronous main interface 52.Why two FIFO are provided, and are in order better to carry out read-write operation control; Here also can merge into a FIFO to write data FIFO55 and read data FIFO56, can finish purpose of design equally.To those of ordinary skill, obviously also can substitute write data FIFO and/or read data FIFO here with two-port RAM.
Bus by AHB slave unit interface when the AHB host device interface is transmitted, just carry out ahb bus when transmission to the hcklm clock zone from the hclks clock zone, asynchronous from interface 51 reception hclks clock zone ahb bus burst transfer, control signal on the ahb bus is deposited, data-signal on the ahb bus is write write data FIFO55, and send transfer request signal to asynchronous main interface 52; It is synchronous that 53 pairs of transfer request signals of secondary SYN register carry out secondary; Transfer request signal after asynchronous main interface 52 reception secondarys are synchronous is read the ahb bus data-signal from write data FIFO55, set up the ahb bus transmission in conjunction with the ahb bus control signal of depositing at the hcklm clock zone.
Carry out ahb bus when transmission at the hcklm clock zone to the hclks clock zone, asynchronously send transfer request signal to asynchronous main interface 52 from interface 51; It is synchronous that 53 pairs of transfer request signals of secondary SYN register carry out secondary; Transfer request signal after asynchronous main interface 52 reception secondarys are synchronous is set up the ahb bus transmission at the hcklm clock zone, and the ahb bus data-signal is write read data FIFO56; Asynchronously from read data FIFO56, read the ahb bus data-signal, set up the ahb bus transmission at the hckls clock zone from interface 51.
No matter above-mentioned which kind of situation, hcklm clock zone ahb bus transmission at first finish, asynchronous main interface 52 send answer signals to asynchronous from interface 51; It is synchronous that 54 pairs of answer signals of secondary SYN register carry out secondary; Asynchronously receive the answer signal of secondarys after synchronously, finish the transmission of hcklm clock zone ahb bus from interface 51.
See also shown in Figure 3ly, Fig. 3 has disclosed asynchronous from various state exchanges of interface and control corresponding condition, under the implication of each state shown in:
IDLE: idle condition;
ADDR: address state, deposit bus control signal, judge transport-type and send transfer request signal to the host device interface side;
SINGLE_DATA: single transmission state, wait host device interface side is finished this single transmission;
DATA_ST: the write data state, control writes this secondary burst to write data FIFO and writes data signals transmitted;
ST_WAIT: write waiting status, wait host device interface side is finished this secondary burst and is write transmission;
LD_WAIT: read waiting status, wait host device interface side is finished this secondary burst and is read transmission;
DATA_LD: the read data state, control is read this secondary burst and is read data signals transmitted from read data FIFO;
ERR1: error condition 1, two clap the first count of errored response on the ahb bus;
ERR2: error condition 2, two clap the second count of errored response on the ahb bus;
OKAY: transmission success state.
Below from the IDLE state, describe from the various state exchanges of interface asynchronous, when existing effectively transmission and bus ready on the ahb bus (condition 1), asynchronous from interface state machine enter the ADDR state and send transmission requests, this transmission requests is delivered to the host device interface side synchronously through two-stage.
Under the ADDR state, judge according to the control signal on the bus, if single read/write transmission (condition 17) then enters the SINGLE_DATA state; If transmission (condition 5) is write in burst, then state machine enters the DATA_ST state; If transmission (condition 2) is read in burst, then enter the LD_WAIT state.
Under the SINGLE_DATA state, wait for, until receiving that the host device interface side finishes the response signal of returning after this single read/write, if transmission success (condition 18) then enter the OKAY state, if error of transmission (condition 19) then enter the ERR1 state and then enter the ERR2 state.Enter transmission next time or IDLE state then.
Under the DATA_ST state, in write data FIFO, write write data (condition 8), when the count value of the data that write reaches this secondary burst and writes the length of transmission (condition 6), stop to write, enter the ST_WAIT state; Under the ST_WAIT state, state machine is waited for until receiving that the host device interface side finishes the response signal of returning after this secondary burst is write transmission, if transmission success (condition 7) then enter the OKAY state, if error of transmission (condition 12) then enter the ERR1 state and then enter the ERR2 state; Enter transmission next time or IDLE state then.
Under the LD_WAIT state, wait for (condition 9), data finish (condition 3) above default FIFO thresholding or the read operation of host device interface side in read data FIFO, enter the DATA_LD state; Under the DATA_LD state, from read data FIFO, read the total data signal, if transmission success (condition 4) then enters the OKAY state; If error of transmission (condition 11) then enter the ERR1 state and then enter the ERR2 state; Enter transmission next time or IDLE state then.
See also shown in Figure 4ly, Fig. 4 has disclosed various state exchanges of asynchronous main interface and control corresponding condition, under the implication of each state shown in:
IDLE: idle condition.
REQ: solicited status, the request bus right to use;
ADDR: address state, judge current transport-type, and begin to rebuild transmission according to the control signal of depositing;
SINGLE_DATA: single transmission state, wait AHB slave unit is finished current single transmission;
DATA_ST: burst transfer is write state, and control read data signal from write data FIFO is rebuild the burst of host device interface side clock zone and write transmission;
DATA_LD: the burst transfer read states, to rebuild burst at host device interface side clock zone and read transmission, control writes read data FIFO with the data of reading.
Below still from the IDLE state, the various state exchanges of asynchronous main interface are described, under the IDLE state, when the data of receiving single transmission requests or writing among the write data FIFO when transmission is write in burst have surpassed the FIFO thresholding, and have bus to use (condition 1) when bus is ready for the time being this moment, and state machine enters the ADDR state; When the transmission requests of slave unit interface side arrives, if also obtaining bus grant or bus, the host device interface side also do not have (condition 10) when ready, enter the REQ state.
Under the REQ state, if obtain bus grant and bus when ready (condition 11) enter the ADDR state.
Under the ADDR state,, then send the ahb bus control signal of single transmission if currently be transmitted as single transmission (condition 8); If current be transmitted as the burst write transmission (condition 5), enter the DATA_ST state; If current be transmitted as the burst read the transmission (condition 2), enter the DATA_LD state.
Under the SINGLE_DATA state, carry out single transmission, finish current single transmission (condition 9) when the AHB slave unit, send answer signal to the slave unit interface side.
Under the DATA_ST state, according to the bus control signal of depositing, control read data signal from write data FIFO is rebuild the burst of host device interface side clock zone and is write transmission (condition 6); After finishing this secondary burst to write transmission (condition 7), send answer signal to the slave unit interface side.
Under the DATA_LD state, rebuild the burst of host device interface side clock zone according to the bus control signal of depositing and read transmission and control data-signal is write read data FIFO; After finishing this secondary burst to read transmission (condition 4), send answer signal to the slave unit interface side.
See also shown in Figure 5ly, Fig. 5 has disclosed whole asynchronous bridge workflow, describes below in conjunction with Fig. 2.
On the dotted line right side, from interface, be in idle condition at the hclks clock zone in the time of at the beginning to asynchronous;
Then detect AHB slave unit interface side (AHB SLAVE side) clock zone just the hclks clock zone whether ahb bus transmission appears, if not, then continue to keep idle condition;
If the ahb bus transmission appears in the hclks clock zone, deposit the control signal on the ahb bus, and send transfer request signal to the host device interface side;
Then transport-type is judged by the control signal on the transfer bus;
If single transmission (single transmission) type, processing procedure is the same with the prior art scheme, no matter read transmission or write transmission, does not all need to utilize write data FIFO or read data FIFO, directly waits for the answer signal of host device interface side;
If transmission (burst writes transmission) is write in burst, the data-signal on the ahb bus is write write data FIFO, wait for the answer signal of host device interface side then;
Then judge whether to receive the answer signal that the host device interface side is sent, if not, continue to wait for; If receive answer signal, finish hclks clock zone AHB territory bus transfer.
If judge transport-type is that transmission (burst reads transmission) is read in burst, waits for the answer signal of host device interface side too;
Then judge whether the answer signal of receiving that the host device interface side is sent, if not, continue to wait for;
If receive the answer signal that the host device interface side is sent, read data signal from read FIFO utilizes the already present ahb bus of hclks clock zone to transmit described data-signal, after data-signal is all read in reading FIFO, finishes the transmission of hclks clock zone.
Transmission is read in burst, can also be arranged to detect the data reading to store the FIFO when having surpassed default FIFO thresholding from interface when asynchronous, direct read data signal from read FIFO just finishes the transmission of hclks clock zone read the total data signal from ovonic memory after receiving the answer signal that the host device interface side is sent after.Because a secondary burst is read information transmitted and is no more than 16 bytes usually, a kind of processing mode before selecting here to adopt.
In the dotted line left side, to asynchronous main interface, after AHB host device interface side (AHB MASTER side) receives the transfer request signal of secondary SYN register 53 secondarys after synchronously, according to the control signal on the ahb bus of depositing transport-type is judged, if single transmission requests, directly set up single transmission at the hclkm clock zone, processing procedure is the same with the prior art scheme;
If transmission is read in burst, set up the ahb bus burst at the hclkm clock zone and read transmission, the data-signal on the ahb bus is write studied in FIFO;
If transmission requests is write in burst, when detecting when writing that the storage data have surpassed predetermined threshold value among the FIFO, read data signal from write FIFO is set up the ahb bus burst at the hclkm clock zone and is write transmission;
Above-mentioned three kinds be transmitted in the hclkm clock zone and finish after, asynchronous main interface all can send answer signal to AHB slave unit interface side, this response signal is sent to asynchronous from interface by secondary SYN register 54 secondarys synchronously.
Reading and writing data when the present invention program adopts ovonic memory to keep in the ahb bus burst transfer in asynchronous bridge, and carried out corresponding state exchange control and adjusted, make asynchronous bridge can support to stride the ahb bus burst transfer in clock territory, improved bus efficiency greatly.Burst transfer is converted to the asynchronous bridge that single transmission is handled, and each action (beat) transmission probably needs 9 clock period (cycle) at a slow speed, thereby length is that 16 burst transfer needs about 16 * 9=144 cycle.And the burst asynchronous bridge that uses the present invention program to carry out length be that 16 burst transfer only needs about 32 clock period at a slow speed, on average each moves about 2 clock period at a slow speed, efficient can improve about 4 times.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1, a kind of asynchronous bridge is characterized in that, described asynchronous bridge is used for the data transmission between the chip internal different clock-domains, comprising:
Asynchronous from interface, detect and send transfer request signal when having bus transfer in first clock zone;
The secondary lock unit, the synchronous described transfer request signal of secondary;
Asynchronous main interface receives the transfer request signal of secondary after synchronously, sets up the bus transfer in second clock territory;
Ovonic memory, described ovonic memory one end asynchronously is connected from interface with described, and the other end is connected the data-signal during the memory bus burst transfer with described asynchronous main interface.
2, asynchronous bridge as claimed in claim 1 is characterized in that,
When burst transfer is burst when reading transport-type, described asynchronous main interface writes data-signal in ovonic memory, describedly asynchronously reads described data-signal from interface from described ovonic memory;
Or be burst when writing transport-type when burst transfer, and describedly asynchronously to ovonic memory, writing data-signal from interface, described asynchronous main interface is read described data-signal from described ovonic memory.
3, asynchronous bridge as claimed in claim 1 or 2 is characterized in that, described asynchronous main interface sends answer signal after the bus transfer in second clock territory finishes; The synchronous described answer signal of described secondary lock unit secondary; Describedly asynchronously receive the answer signal of secondary after synchronously, finish the bus transfer of first clock zone from interface.
4, asynchronous bridge as claimed in claim 1 or 2 is characterized in that, described ovonic memory is FIFO or two-port RAM, and described burst transfer is the ahb bus burst transfer of cross clock domain.
5, asynchronous bridge as claimed in claim 4 is characterized in that, described FIFO comprises write data FIFO and read data FIFO.
6, a kind of method of using asynchronous bridge to carry out data transmission, it is characterized in that, described asynchronous bridge is used for the data transmission between the chip internal different clock-domains, described asynchronous bridge comprises asynchronous from interface, secondary lock unit, asynchronous main interface and ovonic memory, and described method comprises the steps:
Asynchronously control signal on the slave unit interface side bus is deposited, send transfer request signal, determine that according to described control signal transport-type is burst when reading to transmit, and waits for reading of data from interface;
It is synchronous that the secondary lock unit carries out secondary to described transfer request signal;
Transfer request signal after asynchronous main interface reception secondary is synchronous determines that according to described control signal of depositing transport-type is that transmission is read in burst;
Asynchronous main interface is set up burst in the host device interface side and is read transmission, writes data-signal in ovonic memory;
Asynchronously from ovonic memory, read described data-signal, utilize the described data-signal of described slave unit interface side bus transfer from interface.
7, the method for the data transmission of asynchronous bridge as claimed in claim 6 is characterized in that, described asynchronous reading from ovonic memory from interface also comprises before the described data-signal:
Asynchronous detecting from interface stored data above predetermined threshold value the ovonic memory.
8, the method for the data transmission of asynchronous bridge as claimed in claim 6 is characterized in that, described asynchronous reading from ovonic memory from interface also comprises before the described data-signal:
Asynchronous main interface sends answer signal after end of transmission (EOT) is read in the burst of host device interface side;
It is synchronous that the secondary lock unit carries out secondary to described response signal;
Asynchronously receive the response signal of secondary after synchronously from interface.
9, a kind of method of using asynchronous bridge to carry out data transmission, it is characterized in that, described asynchronous bridge is used for the data transmission between the chip internal different clock-domains, described asynchronous bridge comprises asynchronous from interface, secondary lock unit, asynchronous main interface and ovonic memory, and described method comprises the steps:
Asynchronously control signal on the slave unit interface side bus is deposited, send transfer request signal, determine that according to described control signal transport-type is burst when writing transmission, the data-signal in ovonic memory on the write bus from interface;
It is synchronous that the secondary lock unit carries out secondary to described transfer request signal;
Asynchronous main interface receives the transfer request signal of secondary after synchronously, determines that according to described control signal of depositing transport-type is burst when writing transmission, waits for reading of data;
Asynchronous main interface detects when the storage data have surpassed predetermined threshold value in the ovonic memory, reads described data-signal from ovonic memory, sets up burst in the host device interface side and writes transmission.
10, the method for the data transmission of asynchronous bridge as claimed in claim 9 is characterized in that, the host device interface pleurapophysis send out write end of transmission (EOT) after, further comprise the steps:
Asynchronous main interface sends answer signal;
It is synchronous that the secondary lock unit carries out secondary to described response signal;
Asynchronously receive the response signal of secondary after synchronously, stop write data signal in ovonic memory, finish slave unit interface side bus transfer from interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100608277A CN100483377C (en) | 2006-05-17 | 2006-05-17 | Asynchronous bridge and data transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100608277A CN100483377C (en) | 2006-05-17 | 2006-05-17 | Asynchronous bridge and data transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1983223A CN1983223A (en) | 2007-06-20 |
| CN100483377C true CN100483377C (en) | 2009-04-29 |
Family
ID=38165775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100608277A Active CN100483377C (en) | 2006-05-17 | 2006-05-17 | Asynchronous bridge and data transmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100483377C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111143264A (en) * | 2019-12-30 | 2020-05-12 | 山东方寸微电子科技有限公司 | APB bridge for realizing synchronous mode, APB bridge for realizing asynchronous mode and control method thereof |
| CN108304333B (en) * | 2017-12-26 | 2021-04-13 | 中国科学院长春光学精密机械与物理研究所 | One-master multi-slave bus |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101493717B (en) * | 2009-02-19 | 2011-04-13 | 浪潮电子信息产业股份有限公司 | Dynamic multi-clock low power consumption AHB bus design method for SOC |
| KR20110061189A (en) * | 2009-12-01 | 2011-06-09 | 삼성전자주식회사 | Asynchronization upsizing circuit in data processing system |
| KR20160118049A (en) * | 2015-04-01 | 2016-10-11 | 삼성전기주식회사 | Electronic apparatus, asynchronous data transmitting method thereof and optical image stabilization module |
| CN110389924A (en) * | 2018-04-19 | 2019-10-29 | 大唐移动通信设备有限公司 | A kind of serial bus device and setting method |
| GB201810785D0 (en) | 2018-06-29 | 2018-08-15 | Nordic Semiconductor Asa | Asynchronous communication |
| CN111177048A (en) * | 2018-11-09 | 2020-05-19 | 珠海格力电器股份有限公司 | AHB bus equipment and data stream transmission method thereof |
| CN111324562B (en) * | 2020-02-16 | 2021-08-06 | 苏州浪潮智能科技有限公司 | Clock domain crossing system of AHB and working method |
| CN111339012B (en) * | 2020-02-20 | 2023-06-20 | 广东博智林机器人有限公司 | Processor system bus structure and system |
| CN112596438B (en) * | 2020-12-14 | 2022-06-21 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | Real-time reliable waveform data transmission circuit between FPGA and microcontroller |
| CN112579486B (en) * | 2020-12-14 | 2023-02-21 | 上海创远仪器技术股份有限公司 | System for realizing cross-clock-domain communication based on dual-port RAM |
| CN113533941B (en) * | 2021-09-15 | 2022-03-01 | 北京国科天迅科技有限公司 | Chip interface testing method and device, computer equipment and storage medium |
-
2006
- 2006-05-17 CN CNB2006100608277A patent/CN100483377C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108304333B (en) * | 2017-12-26 | 2021-04-13 | 中国科学院长春光学精密机械与物理研究所 | One-master multi-slave bus |
| CN111143264A (en) * | 2019-12-30 | 2020-05-12 | 山东方寸微电子科技有限公司 | APB bridge for realizing synchronous mode, APB bridge for realizing asynchronous mode and control method thereof |
| CN111143264B (en) * | 2019-12-30 | 2021-08-03 | 山东方寸微电子科技有限公司 | APB bridge for realizing synchronous mode, APB bridge for realizing asynchronous mode and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1983223A (en) | 2007-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100483377C (en) | Asynchronous bridge and data transmission | |
| US7596641B2 (en) | System and method for transmitting data packets in a computer system having a memory hub architecture | |
| CN109800193B (en) | Bridging device of SRAM on AHB bus access chip | |
| KR101699784B1 (en) | Bus system and operating method thereof | |
| CN103198043A (en) | Improved AHB-to-APB bus bridge and control method thereof | |
| CN112035389B (en) | PLB-AXI bus conversion bridge and working method thereof | |
| CN102420877B (en) | Multi-mode high-speed intelligent asynchronous serial port communication module and realizing method thereof | |
| CN102841869B (en) | Multi-channel I2C controller based on FPGA | |
| CN109634900B (en) | AXI (advanced extensible interface) protocol-based multi-level low-delay interconnection structure | |
| JPH08116348A (en) | High-speed communication equipment | |
| CN114265872B (en) | Interconnection device for bus | |
| CN102207920B (en) | Conversion bridge for conversion from BVCI (basic virtual component interface) bus to AHB (advanced high performance bus) | |
| CN101339541A (en) | DMA data-transmission method and DMA controller | |
| US5067075A (en) | Method of direct memory access control | |
| CN117093157A (en) | DDR high-speed read-write method and system for unidirectional optical transmission | |
| CN115328832B (en) | Data scheduling system and method based on PCIE DMA | |
| CN109145397A (en) | A kind of external memory arbitration structure for supporting parallel pipelining process to access | |
| CN116204465A (en) | Design of multi-channel DDR and PCIE data exchange module | |
| US7039730B2 (en) | Storage device control apparatus and method | |
| CN100587680C (en) | Method and system for managing data stream on separation bus between bus agents | |
| US7296109B1 (en) | Buffer bypass circuit for reducing latency in information transfers to a bus | |
| JPS5979655A (en) | Data transmission system | |
| CN1125866A (en) | Method and apparatus for transmission of signals over a shared line | |
| EP0829095B1 (en) | Method and apparatus for reducing latency time on an interface by overlapping transmitted packets | |
| CN101710310A (en) | AMBA interface circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |