CN101710310A - AMBA interface circuit - Google Patents

Abstract

The invention relates to an AMBA interface circuit which is characterized in that 3 FIFOs are arranged in a Master interface circuit, wherein the Writer Data FIFO and the Writer Address FIFO are used for receiving the data and the address from the transmission of master equipment; if the master equipment does not obtain the right to use the bus temporarily, the data or the address can be first written into the Writer Data FIFO or the Writer Address FIFO, and the data or the address can be transmitted after the master equipment obtains the right to use the bus; the Read Data FIFO is used for sending data to the master equipment; when the master equipment is busy, the data from the transmission of a Slave equipment can be stored temporarily in the Read Data FIFO, then the bus can be release, and the data can be transmitted when the master equipment can receive the data. Compared with the prior art, the invention has the advantages that firstly, because the FIFOs are arranged in the Master interface circuit, the running of the master equipment and the slave equipment and the transmission of the data or the address can be made concurrent, and the bus waiting time and the access-memory delay can be can be shortened, secondly, because the FIFOs are arranged in the Master interface circuit, the resource can be saved in the process of the transmitting the data or the address by the master equipment and the slave equipment, and thirdly, the loss of the data can be avoided when the Master interface circuit is used for transmitting the network on the chip.

Description

A kind of AMBA interface circuit

Technical field

The invention belongs to the SIC (semiconductor integrated circuit) technical field, relate to a kind of AMBA bus interface circuit.

Background technology

Microprocessor core or DSP nuclear, storer, system bus and peripheral hardware have been integrated on the chip piece, and the development along with the SoC technology requires high speed data transfer, reduce bus access and postpone, and reduce memory access latency.Need a kind of bus interface module that can satisfy high speed data transfer of design, make the data transmission of processor core operation and peripheral hardware have concurrency, improve overall system performance.

At present, it as the patent No. method of data-switching between the AHB interface of AMBA in the RISC system of 02130330.4 integrated circuit and 20071004557.7 and parallel processor, mostly the interface circuit based on the AMBA bus that adopts is to adopt the register transfer data, be difficult for overcoming bus access and postpone, easily waste resource.

Summary of the invention

Purpose of the present invention is exactly the defective that postpones, easily wastes resource for the bus access that exists in the interface circuit that overcomes existing AMBA bus, the AMBA interface circuit of a kind of FIFO of the employing storage read-write that provides.

Technical scheme of the present invention:

A kind of AMBA interface circuit, comprise Master Interface circuit, Slave interface circuit and bus arbiter thereof, the Master Interface circuit links to each other with main equipment Master, the Slave interface circuit links to each other with slave unit Slave, determine the bus right to use by the bus arbiter arbitration, carry out the exchanges data between main equipment, slave unit then, it is characterized in that, the data buffer FIFO of built-in 3 first in first out of Master Interface circuit, wherein:

Write Data FIFO is used to receive from the next data of master transmissions, when this main equipment does not obtain the bus right to use temporarily, data can be write earlier among the Write Data FIFO, transmits data when waiting to obtain the bus right to use again;

Write Address FIFO is used to receive the address come from master transmissions, when this main equipment does not obtain the bus right to use temporarily, the address can be write among the Write Address FIFO transport address again when waiting to obtain the bus right to use earlier;

Read Data FIFO is used for sending data to main equipment, and when main equipment was busy, the data of coming from the Slave transmission can be temporary in the Read Data FIFO, discharge bus then, treat to send when main equipment can receive data data again.

FIFO described in the present invention, it is the abbreviation of First In First Out, be the data buffer of first in first out, adopt the AMBA interface circuit design technology of FIFO storage read-write to realize based on communication interface circuit between 32 master-slave equipments of AMBA standard ahb bus.The circuit agent structure is made up of Master host device interface circuit, Slave slave unit interface circuit, ahb bus moderator.Wherein two receptions of built-in three FIFO of Master Interface circuit, a transmission; Use the register transceive data in the Slave interface circuit; By the bus arbiter selecting priority, finish data transmission between master-slave equipment.

Design proposal of the present invention is for different transfer rate between system bus in the balance node and the network-on-chip interface, the bus access or the Network Transmission that reduce data transmission between high-performance and the high-throughput equipment postpone as far as possible, as the data transmission between CPU, DSP or each node of other coprocessors, dma device, on-chip memory and chip multi-core etc.Innovative point is by built-in three FIFO of Master Interface circuit, makes the data transmission of processor core operation and peripheral hardware have concurrency, postpones to reduce bus stand-by period and memory access.

In the technical scheme of the present invention:

1, built-in three FIFO of Master Interface circuit: two FIFO as reception receive data and the address come from master transmissions respectively; Another sends data to main equipment.Ahb bus is supported a plurality of master and slave equipment, the separately transmission of address, data bus when this main equipment does not obtain the bus right to use temporarily, can write data or address among the FIFO earlier, transmit data when waiting to obtain the bus right to use again, main equipment need not be waited for and continue computing; When main equipment was busy, the data of coming from the Slave transmission can be temporary in the FIFO, discharge bus then, treat to send when main equipment can receive data data again.Can economize on resources like this, reduce the bus memory access and postpone.

2, in order to visit as equipment such as on-chip memories, Slave interface circuit inside is provided with several registers such as address, data, transport-type and control.When slave unit is read and write, read and write according to transport-type, control register signal.Slave interface circuit control read data and response signal are selected the equipment that will visit from the slave unit of participating in transmission.

3, ahb bus is supported a plurality of master and slave equipment, sends bus request according to main equipment, determines which main equipment its address and control signal can be sent to all slave units by bus arbiter.

4, support monocycle bus master control conversion.

The present invention and in application, comprise following characteristics:

1, ahb bus is supported broken hairdo data transfer mode and division affairs, three FIFO is set in the Master Interface circuit can makes main equipment when carrying out these two kinds of transmission modes, asks, uses and reduce when discharging bus as far as possible to postpone, and reduces free time.

2, slave unit is an on-chip memory in system, especially during a slave unit,, can improve bus access efficient by data register among the Slave and the transmission of the FIFO among Master data, can reduce the interface circuit chips area again, make interface circuit do forr a short time.

The present invention compared with prior art, its remarkable advantage is:

1, by the Master Interface circuit FIFO is set, makes the operation of master and slave equipment and data or address transfer have concurrency, reduce bus stand-by period and memory access and postpone.

2, by the Master Interface circuit FIFO is set, makes master and slave equipment in transmission data or address process, save resource.

When 3, this Master Interface circuit being used for the network-on-chip transmission, avoid data-bag lost.

The present invention mainly is by built-in FIFO, and adopts the FIFO transmission, changes in the prior art with register transfer data or address, has improved bus access efficient, makes the operation of main equipment, slave unit and data or address transfer have concurrency.Adopt the AMBA interface circuit of FIFO storage read-write to can be used for main equipment and slave unit data or address transfer in the SOC chip, and based on data or address transfer between each node of chip multi-core of bus structure or network-on-chip NOC structure.

Description of drawings

Fig. 1 is an overall construction drawing of the present invention;

Fig. 2 is the Master Interface circuit structure diagram.

Embodiment:

As shown in Figure 1, a kind of AMBA interface circuit of the present invention, comprise Master Interface circuit, Slave interface circuit and bus arbiter thereof, the Master Interface circuit links to each other with main equipment Master, the Slave interface circuit links to each other with slave unit Slave, determine the bus right to use by the bus arbiter arbitration, carry out the exchanges data between main equipment, slave unit then.

As shown in Figure 2, the invention is characterized in, the data buffer FIFO of built-in 3 first in first out of Master Interface circuit, wherein:

Write Data FIFO is used to receive from the next data of master transmissions, when this main equipment does not obtain the bus right to use temporarily, data can be write earlier among the Write Data FIFO, transmits data when waiting to obtain the bus right to use again;

Write Address FIFO is used to receive the address come from master transmissions, when this main equipment does not obtain the bus right to use temporarily, the address can be write among the Write Address FIFO transport address again when waiting to obtain the bus right to use earlier;

Read Data FIFO is used for sending data to main equipment, and when main equipment was busy, the data of coming from the Slave transmission can be temporary in the Read Data FIFO, discharge bus then, treat to send when main equipment can receive data data again.

Above-mentioned three FIFO all link to each other with moderator and Slave interface circuit by AHB BuS.

Claims (1)

1. AMBA interface circuit, comprise Master Interface circuit, Slave interface circuit and bus arbiter thereof, the Master Interface circuit links to each other with main equipment Master, the Slave interface circuit links to each other with slave unit Slave, determine the bus right to use by the bus arbiter arbitration, carry out the exchanges data between main equipment, slave unit then, it is characterized in that, the data buffer FIFO of built-in 3 first in first out of Master Interface circuit, wherein:

Write Data FIFO is used to receive from the next data of master transmissions, when this main equipment does not obtain the bus right to use temporarily, data can be write earlier among the Write Data FIFO, transmits data when waiting to obtain the bus right to use again;

Write Address FIFO is used to receive the address come from master transmissions, when this main equipment does not obtain the bus right to use temporarily, the address can be write among the Write Address FIFO transport address again when waiting to obtain the bus right to use earlier;

Read Data FIFO is used for sending data to main equipment, and when main equipment was busy, the data of coming from the Slave transmission can be temporary in the Read Data FIFO, discharge bus then, treat to send when main equipment can receive data data again.

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