CN112860613A

CN112860613A - Communication system

Info

Publication number: CN112860613A
Application number: CN202110367676.4A
Authority: CN
Inventors: 杜增权; 黄平
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2021-04-06
Filing date: 2021-04-06
Publication date: 2021-05-28
Anticipated expiration: 2041-04-06
Also published as: CN112860613B

Abstract

The utility model relates to a communication system, the system includes first subassembly, second subassembly and at least one third subassembly, communicate through first SPI circuit between second subassembly and the first subassembly, communicate through at least one second SPI circuit between first subassembly and the at least one third subassembly, after the second subassembly sends through first SPI circuit and crosses chip communication beginning instruction to first subassembly, first subassembly establishes first SPI circuit with the relation of connection of second SPI circuit for the second subassembly directly writes the operation or reads the operation to the third subassembly through SPI communication, the third subassembly is under the condition of the read data instruction of receiving the second subassembly through SPI communication, directly send target data to the second subassembly. The receiving and sending communication time of the second assembly and the third assembly can be shortened, cross-chip direct communication can be efficiently realized, the operation is simple and convenient, and the cost is lower.

Description

Communication system

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a communication system.

Background

In the dual chip cascade application, for the requirement (e.g. downloading program code) that the upper computer chip writes the same data into the two cascade lower computer chips, as shown in fig. 1, the common practice in the related art is as follows: the upper computer writes data into a lower computer chip/cascade master chip storage area to complete the data writing into the master chip, then the cascade master chip controls the communication between the cascade chips, the data of the storage area is read and written into the cascade slave chip to complete the data writing into the slave chip, and aiming at the requirement that the upper computer chip reads data from the cascade slave chip, the common method of the related technology is as follows: the host computer communicates with the master chip, sends and reads the slave chip data request to the master chip through a first communication connection, after receiving and reading the slave chip data request, the master chip communicates through a second communication connection, sends and reads the slave chip data request to the slave chip, and the slave chip is ready to read and send the data.

In the related technology, the communication between the upper computer and the lower computer slave chip needs to be stored by the master chip and then transferred to the slave chip, which consumes 2 times of time and needs multi-stage operation.

Disclosure of Invention

In view of this, the present disclosure proposes a communication system comprising a first component, a second component and at least one third component, the first component and the second component communicating with each other via a first serial peripheral interface, SPI, line, the first component and the at least one third component communicating with each other via at least one second SPI line, wherein,

the second component is used for sending SPI communication information, and the SPI communication information is used for writing data into the second component and the third component or only reading or writing data into the third component;

the first component is to: receiving SPI communication information sent by the second component, and establishing a connection relation between the first SPI line and the second SPI line under the condition that the SPI communication information comprises a cross-chip communication starting instruction, so that the second component establishes direct SPI connection with the first component and the third component;

the third component is used for: and directly receiving SPI communication information sent by the second component through the second SPI circuit, and sending target data under the condition that the SPI communication information comprises a read data command.

In one possible implementation, the third component sends the target data N/2 clock cycles ahead of the second component receiving the target data, where N is an integer.

In one possible implementation, the SPI communication information includes an SPI clock signal and a chip select signal, and the third component is further configured to:

and when the chip selection signal is received, sending the first bit of the target data, and starting from the first falling edge of the SPI clock signal, sending the rest data bits of the target data at the falling edge of the SPI clock signal.

In one possible embodiment, the second assembly is further configured to:

the target data is received starting at the first rising edge after the clock signal of the SPI communication information is sent,

the half-period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information, the uplink delay time of the target data and the sampling establishment time when the second component acquires the target data.

In one possible implementation, the SPI communication information includes an SPI clock signal and a chip select signal,

the third component is further to: transmitting the target data from a first rising edge of the SPI clock signal;

the second component is further configured to: the target data is received starting at the first rising edge after the clock signal of the SPI communication information is sent,

wherein a time difference between the second component issuing the SPI communication information and receiving the target data is one half clock cycle,

and when the chip selection signal is received, sending the first bit of the target data, and starting from the first rising edge of the SPI clock signal, sending the rest data bits of the target data at the rising edge of the SPI clock signal.

In one possible embodiment, the second assembly is further configured to:

the period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time from the second component to the third component of the SPI communication information, the uplink delay time from the third component to the second component of the target data and the sampling establishment time when the second component acquires the target data.

the third component is further to: transmitting the target data starting from a first falling edge of the SPI clock signal;

wherein a time difference between the second component issuing the SPI communication information and receiving the target data is one clock cycle,

and after receiving the chip selection signal, counting the SPI clock signal, and starting from the rising edge of the seventh clock period of the SPI clock signal, and sending the target data at the rising edge of the SPI clock signal.

In one possible embodiment, the first component is further configured to:

and temporarily storing the target data sent by the third component, and sending the target data on the rising edge of the next SPI clock signal receiving the target data.

In one possible embodiment, the third component is further configured to:

and after receiving the chip selection signal, sending a first bit of redundant data, and sending the rest bits of the redundant data from a first falling edge or a rising edge to a sixth falling edge or a rising edge of the SPI clock signal.

In one possible embodiment, the second assembly is further configured to:

the target data is received starting at the ninth rising edge after the clock signal of the SPI communication information is transmitted,

wherein the period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time from the first component to the third component of the SPI communication information, the uplink delay time from the third component to the first component of the target data and the sampling setup time when the second component acquires the target data,

the period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information from the second component to the first component, the uplink delay time of the target data from the first component to the second component and the sampling establishment time when the target data is acquired by the second component.

the third component is further to: transmitting the target data at a rising edge of the SPI clock signal starting from a rising edge of a seventh clock cycle of the SPI clock signal;

the first component is further to: temporarily storing the target data sent by the third component, and sending the target data on the rising edge of the next SPI clock signal receiving the target data;

the second component is further configured to: the target data is received starting at a ninth rising edge after the clock signal of the SPI communication information is transmitted,

wherein a time difference between the second component issuing the SPI communication information and receiving the target data is two clock cycles,

In one possible embodiment, the third component is further configured to:

In one possible implementation, when the first SPI line and the second SPI establish a connection, the first component is further configured to:

and under the condition that cross-chip communication stop instructions are included in the received SPI communication information, disconnecting the connection relation between the first SPI line and the second SPI line.

In a possible embodiment, the first component includes a line switch therein, and the first component is further configured to:

and under the condition that the SPI communication information comprises a cross-chip communication starting instruction, establishing the connection relation between the first SPI line and the second SPI line through the selector switch.

In one possible embodiment, the first component is further configured to:

and under the condition that cross-chip communication stop instructions are included in the received SPI communication information, disconnecting the connection relation between the first SPI line and the second SPI line through the selector switch.

In one possible implementation, the first component and the third component comprise a display, a smart phone or a portable device, and the second component comprises an upper computer.

In one possible embodiment, the display includes any one of a liquid crystal display, an organic light emitting diode display, a quantum dot light emitting diode display, a mini light emitting diode display, and a micro light emitting diode display.

The communication system of the embodiment of the disclosure can switch the second component from the first SPI line to the second SPI line according to the cross-chip communication start instruction contained in the SPI communication information of the second component, so that the second component is directly connected to the first component and the third component, and thus, when the second component simultaneously sends the SPI communication information to the first component and the third component, the third component can receive the same SPI communication information sent by the second component synchronously with the first component, thereby achieving the purpose of broadcasting.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a diagram illustrating writing of data to a cascade chip in the related art.

Fig. 2a shows a block diagram of a communication system according to an embodiment of the present disclosure.

Fig. 2b shows a block diagram of a communication system according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of a write data transfer according to an embodiment of the present disclosure.

FIG. 4 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

FIG. 5 illustrates a schematic diagram of read data transfer according to an embodiment of the present disclosure.

FIG. 6 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings, which is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and, therefore, should not be taken as limiting the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Referring to fig. 2a, fig. 2a shows a block diagram of a communication system according to an embodiment of the present disclosure.

As shown in fig. 2a, the system includes a first component 10, a second component 20 and at least one third component 30, the first component 10 and the second component 20 communicate with each other through a first serial peripheral interface SPI (serial peripheral interface) line, the first component 10 and the at least one third component 30 communicate with each other through at least one second SPI line, wherein,

the second component 20 is configured to send SPI communication information, which is used to write data to the second component 20 and the third component 30 or to read data or write data only to the third component 30;

the first assembly 10 is for: receiving SPI communication information sent by the second component 20, and establishing a connection relationship between the first SPI line and the second SPI line so that the second component 20 establishes direct SPI connections with the first component 10 and the third component 30 when the SPI communication information includes a cross-chip communication start instruction;

the third assembly 30 is for: the SPI communication information sent by the second component 20 is directly received through the second SPI line, and the target data is sent when the SPI communication information includes a read data command.

The communication system of the embodiment of the present disclosure may switch the second component 20 from the first SPI line to the second SPI line according to the cross-chip communication start indication included in the SPI communication information of the second component 20, so that the second component 20 is directly connected to both the first component 10 and the third component 30, and thus, when the second component 20 simultaneously transmits the SPI communication information to the first component 10 and the third component 30, the third component 30 may receive the same SPI communication information transmitted by the second component 20 in synchronization with the first component 10, thereby achieving the purpose of broadcasting, and when the second component 20 is to read the data of the third component 30, the second component 20 may transmit the read instruction to the third component 30 more quickly, and the third component 30 may also return the data to the second component 20 in response to the read instruction more quickly, thereby saving the communication time and having high efficiency compared to the related art, and the operation is simple and convenient, and the cost is lower.

Through the above system, the embodiment of the present disclosure can implement the simultaneous data writing of the second component 20 to the first component 10 and the third component 30, that is, the first mode, in which the data written by the second component 20 to the first component 10 and the third component 30 are the same; the second component 20 may perform data reading and writing only on the third component 30, that is, a second mode in which the second component 20 does not read and write data on the first component 10 and the first component 10 does not see data in this mode (data read and written only on the third component 30). In one example, a mode indication flag bit (e.g., 1 for first mode, 0 for second mode) may be set in the SPI communication to distinguish between the two modes, in this regard, the disclosed embodiments are not limited, and in the second mode, communication between the first component 10 and the second component 20 may be cut off, for example, after the first component sends a chip communication indication to the second component through the first SPI line, the second component establishes a connection relationship between the first SPI line and the second SPI line, and cuts off communication between the first component 10 and the second component 20, the first component 10 only serves as a node for transmitting SPI communication information, the second component directly carries out write operation or read operation on the third component through SPI communication, and the third component directly sends target data to the second component under the condition that the third component receives a read data command of the second component through the SPI communication.

The specific implementation manner of communicating by using the SPI is not limited in the embodiments of the present disclosure, and those skilled in the art can implement the SPI according to the related art, and the embodiments of the present disclosure do not limit the specific implementation of the SPI communication protocol, and the SPI communication mentioned in the present disclosure may be based on a four-wire SPI (for example, including a clock signal line CLK, a chip select line CS, a master-input slave-output MISO, and a master-output slave-input MOSI), may also include a three-wire SPI (for example, the clock signal line CLK, the chip select line CS, the master-input slave-output MISO, or the master-output slave-input MOSI, where a data line may be a MISO or a MOSI), and of course, the three-wire SPI may also include the clock signal line CLK, the master-input slave-output MISO.

Of course, the above description of the SPI signal line is exemplary, and in other embodiments, one skilled in the art may set it as desired.

In one example, the SPI communication information may include an SPI clock signal CLK, an SPI chip select signal CS, and SPI data MOSI.

It should be noted that, in the embodiment of the present disclosure, a specific implementation manner of the first component 10, the second component 20, and the third component 30 is not limited, the first component 10 may be referred to as an upper computer, and the second component 20 and the plurality of third components 30 are in a master-slave relationship, where the second component 20 may be a master and the third component 30 may be a slave.

In one example, a component includes, but is not limited to, a single processor, or discrete components, or a combination of a processor and discrete components. The processor may comprise a controller having functionality to execute instructions in an electronic device, which may be implemented in any suitable manner, e.g., by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers, and embedded microcontrollers. In one example, the component may also be a Terminal or a server, where the Terminal is also called a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), and the like, and is a device that provides voice and/or data connectivity to a User, for example, a handheld device with a wireless connection function, a vehicle-mounted device, and the like. Currently, some examples of terminals are: a Mobile Phone (Mobile Phone), a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in Industrial Control (Industrial Control), a wireless terminal in unmanned driving (self driving), a wireless terminal in Remote Surgery (Remote medical Surgery), a wireless terminal in Smart Grid, a wireless terminal in Transportation Safety, a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in car networking, and the like.

In one example, each of the first, second, and

third components

10, 20, and 30 is configured to support SPI communication, wherein the second component 20 serves as a host, and a plurality of SPI units may be provided to correspond to the first and

third components

10 and 30, respectively, and for example, a first SPI line between the first and

second components

10 and 20 may correspond to a first SPI unit, and a second SPI line between the second and

third components

20 and 30 may correspond to a second SPI unit.

The specific implementation manner of communicating by using the SPI is not limited in the embodiments of the present disclosure, and those skilled in the art can implement the embodiments according to the related art.

In one example, the form of the cross-chip communication start indication may be agreed in advance in the SPI communication protocol, and when the second component 20 receives the cross-chip communication start indication, the connection relationship between the first SPI line and the second SPI line may be agreed to establish the direct connection of the first component 10, the respective third components 30, and the second component 20.

Of course, the embodiments of the present disclosure do not limit the specific protocol implementation, and those skilled in the art can implement the method according to the needs and practical situations.

Referring to fig. 2b, fig. 2b shows a block diagram of a communication system according to an embodiment of the present disclosure.

In a possible implementation, as shown in fig. 2b, the first component 10 may include a line switch 130, and in a case that the SPI communication information includes a cross-chip communication start instruction, establishing a connection relationship between the first SPI line and the second SPI line includes:

and under the condition that the SPI communication information comprises a cross-chip communication starting instruction, establishing a connection relation between the first SPI line and the second SPI line through the line selector switch 130.

In one example, as shown in fig. 2b, the first component 10 includes a first SPI unit 110 and a second SPI unit 120 therein, the second component 20 includes a third SPI unit 210, the third component 30 includes a fourth SPI unit 310, the first SPI unit 110 and the third SPI unit 210 establish an SPI connection to form a first SPI line, and the second SPI unit and the fourth SPI unit establish an SPI connection to form a second SPI line.

In one example, upon receiving the cross-chip communication start indication, the line switcher 130 is enabled to connect corresponding ports (e.g., CLK/CS/MISO) of the first SPI line and the second SPI line.

In a possible embodiment, when the first SPI line and the second SPI establish a connection, the first component 10 may further be configured to:

In one example, when the second component 20 does not need to perform broadcast communication or read data of the third component 30 or other situations, the second component 20 may send a cross-chip communication stop indication to the first component 10 through the SPI, and when the first component 10 receives the cross-chip communication stop indication, the first SPI line and the second SPI line are disconnected to disconnect the direct SPI connection between the second component 20 and the third component 30, so that the broadcast communication system exits the unified operation mode, in which case, the first component 10 and the second component 20 may directly perform SPI communication through the first SPI line, and the SPI communication between the first component 10 and the third component 30 may be directly performed through the second SPI line, but the SPI communication between the second component 20 and the third component 30 cannot be performed directly.

In one example, it may be agreed in advance in the form of the cross-chip communication stop instruction in the SPI communication protocol, and it is agreed that when the second component 20 receives the cross-chip communication stop instruction, the connection relationship between the first SPI line and the second SPI line is disconnected to disconnect the direct connection between the first component 10 and each third component 30.

In a possible embodiment, the first assembly 10 can also be used to:

in the case where a cross-chip communication stop instruction is included in the received SPI communication information, the second component 20 is switched to the first SPI line through the line switch 130.

In one example, when the cross-chip communication stop instruction is received, the line switch 130 is enabled to disconnect the connection relationship between the first SPI line and the second SPI line.

Of course, while FIG. 2b and the above description show one example of line switcher 130, in other examples, line switcher 130 may also be configured to switch off the operation of second SPI unit 120 when the system is operating in the second mode, e.g., the connection PAD of second SPI unit 120 to first SPI unit 110 may be directly connected to third SPI unit 210 through line switcher 130, such that second SPI unit 120 does not receive information from the first SPI unit, and first SPI unit 110 sends SPI communication information through the connection PAD of second SPI unit 120 directly to fourth SPI unit 310 through third SPI unit 210.

The specific type of the switch is not limited in the embodiments of the present disclosure, and those skilled in the art can select the switch according to needs and actual situations, and in one example, the switch can be implemented based on a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), and other switching tubes.

The following is an exemplary description of an implementation in which the second component 20 sends the same data to the first component 10 and the third component 30 at the same time.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating a write data transfer according to an embodiment of the disclosure.

In one example, when the second component 20 needs to perform broadcast communication, the second component 20 may send a cross-chip communication start indication to the first component 10 through the SPI, so that the second component 20 establishes a connection relationship between the first SPI line and the second SPI line, and the broadcast communication system thereby enters a unified operation mode in which the second component 20 can write, i.e., send the same SPI communication information, to the first component 10 and each third component 30.

In one example, as shown in fig. 3, in the unified operation mode, the SPI communication information (a) sent by the second component 20 includes the chip select signal CS, the clock signal CLK, and the SPI broadcast data MOSI, the exemplary SPI broadcast data MOSI is 01101100, and since the first component 10 and the second and

third components

20 and 30 are directly connected, the SPI communication information sent by the second component 20 can be received by the first and

third components

10 and 30, wherein the SPI communication information (B) received by the first component 10 has a delay from the SPI communication information (a), and the delay is a transmission delay time from the first component 10 to the second component 20; the SPI communication information (C) received by the third component 30 is delayed from the SPI communication information (a), and the delay time is a transmission delay time from the first component 10 to the third component 30.

In one example, because the data written by the second component 20 to the first component 10 and the third component 30 is the same, the first component 10 and the second component 20 and the first component 10 and the third component 30 are both the same SPI communication protocol; therefore, the SPI signals for communicating the first component 10 and the second component 20 are directly connected to the SPI communication ports of the first component 10 and the third component 30 (the first SPI communication line between the first component 10 and the second component 20 is cut off), the SPI signals of the second component 20 are sent to the first component 10 and the third component 30, both the first component 10 and the third component 30 can receive the same SPI signals and data sent by the second component 20, and one-time SPI write communication completes the write operation of the same data to at least 2 lower computer cascade chips (the first component 10 and at least one third component 30). The SPI signal received by the third component 30 is delayed by tens of ns from the SPI signal received by the first component 10 because the SPI signal received by the third component 30 passes through more of the 2-stage connection PAD (out the PAD output of the first component 10, into the PAD input of the third component 30). However, since the clock signal CLK and the data signal MOSI in the SPI signals both have the same delay, the third component 30 is not affected from receiving correct data.

Referring to table 1, table 1 shows an illustration of the time consumption for transmitting data using the related art and transmitting data using embodiments of the present disclosure.

TABLE 1

As can be seen from table 1, the embodiments of the present disclosure have a significantly reduced time for writing data to the slave compared to the related art.

Through the system, the embodiment of the disclosure can realize instant broadcast communication between the second component and the first component and among the third components, the second component can write the same data into the first component and the third components quickly, and the system is simple to operate and low in cost.

The following describes an exemplary implementation of the second component 20 reading data of the third component 30.

In one example, when the second component 20 needs to read the data of any one of the third components 30, the second component 20 may send a cross-chip communication start indication to the first component 10 through the SPI, so that the second component 20 establishes the connection relationship between the first SPI line and the second SPI line, and the communication system thereby enters a unified operation mode in which the second component 20 can quickly read the data in each of the third components 30.

Referring to FIG. 4, FIG. 4 illustrates a schematic diagram of read data transfer according to an embodiment of the present disclosure.

In one possible implementation, as shown in fig. 4, the SPI communication information may include an SPI clock signal and a chip select signal, and the third component 30 may further be configured to:

In a possible embodiment, the second assembly 20 is also configured to:

wherein the half-period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information, the target data uplink delay time, and the sampling setup time when the second component 20 acquires the target data.

Since the first SPI line is connected to the second SPI line, in this case, the SPI communication information of the second component 20 can be simultaneously transmitted to the first component 10 and the third component 30, and the data of the third component 30 can also be transmitted to the second component 20 and the first component 10, which improves the communication speed between the second component 20 and the third component 30 compared to two-stage transmission in the related art (the data of the second component 20 and the third component 30 are buffered by the first component 10 and then transmitted).

In one example, as shown in fig. 4, the downstream signal delay time of the SPI communication information includes the delay of the SPI communication information (CS-A, CLK-A, MISO-a, etc.) transmitted by the second component 20 to the first component 10 (delay of the third SPI unit 210 to the first SPI unit 110), the delay between the SPI units of the first component 10 (delay of the first SPI unit 110 to the second SPI unit 120), and the delay of the first component 20 to the third component 30 (delay of the second SPI unit 120 to the fourth SPI unit 310), the target data uplink delay time includes a delay from the third component 30 to the first component 10 (a delay from the fourth SPI unit 310 to the second SPI unit 120), a delay between the SPI units of the first component 10 (a delay from the second SPI unit 120 to the first SPI unit 110), and a delay from the first component 10 to the second component 20 (a delay from the first SPI unit 120 to the third SPI unit 210).

In one example, the delay between the SPI units of the first component 10 (the delay from the second SPI unit 120 to the first SPI unit 110) and the sample setup time when the second component 20 acquires the target data are negligible, and the delay for transmitting the SPI communication information (CS-A, CLK-A, MISO-a, etc.) transmitted by the second component 20 to the first component 10 and the delay for transmitting the SPI communication information (CS-A, CLK-A, MISO-a, etc.) by the first component 20 to the third component 30 are assumed to be 50ns, and in this case, the target data transmitted by the third component 30 needs to satisfy T/2> -100 ns, that is, T ≧ 200ns, and the corresponding frequency freq ≦ 5 MHz.

When the conditions that the half-cycle duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information, the target data uplink delay time, and the sampling setup time when the second component 20 acquires the target data are satisfied, as shown in fig. 4, the third component 30 transmits the first bit (i.e., the most significant bit7 ═ 1) of the target data (MISO-C, illustratively 10101100) when receiving the chip select signal (CS-C), transmits the remaining data bits (bit6 to bit0, i.e., 0101100) of the target data from the first falling edge of the SPI clock signal (CLK-C) and starts receiving the target data from the first rising edge of the SPI clock signal after transmitting the SPI communication information, as shown in fig. 4, the second component 20 correctly receives the target datA (MISO-A is 10101100 for example), and it can be seen that the disclosed embodiment can realize fast and correct communication between the second component 20 and the third component 30.

In the above, the schemes corresponding to the mode 0 and the mode 2 in the SPI communication are introduced, and in the related art, the slave in the mode 0 and the slave in the mode 2 transmit data on the falling edge, and the upper computer receives data on the rising edge.

For example, in the case of the mode 1 and the mode 3 in the SPI communication, the slave transmits data on the rising edge, and the host receives data on the falling edge.

the third component 30 is also used for: transmitting the target data from a first rising edge of the SPI clock signal;

the second assembly 20 is also used for: the target data is received starting at the first rising edge after the clock signal of the SPI communication information is sent,

wherein the time difference between the second component 20 sending out the SPI communication information and receiving the target data is one half clock cycle,

It should be noted that, for the SPI communication method, no matter which mode is adopted, as long as it is ensured that a time difference of one half clock cycle is provided between the third component sending target data and the second component receiving target data, that is, the third component sends the target data in one half clock cycle in advance, the upper computer can correctly read the data sent by the third component, and the communication system according to the embodiment of the present disclosure is used to realize the improvement of the reading speed.

Referring to FIG. 5, FIG. 5 illustrates a schematic diagram of read data transfer according to an embodiment of the present disclosure.

In a possible implementation, the SPI communication information includes an SPI clock signal CLK and a chip select signal CS, and the third component 30 is further configured to:

In a possible embodiment, the second assembly 20 can also be used to:

wherein the period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time from the second component 20 to the third component 30 of the SPI communication information, the uplink delay time from the third component 30 to the second component 20 of the target data, and the sampling setup time when the second component 20 acquires the target data.

In one example, the delay between the SPI units of the first component 10 (the delay between the second SPI unit 120 and the first SPI unit 110) and the sample setup time when the second component 20 acquires the target data are negligible, the delay for transmitting SPI communication information (CS-A, CLK-A, MISO-a, etc.) transmitted by the second component 20 to the first component 10 and the delay for transmitting SPI communication information (CS-A, CLK-A, MISO-a, etc.) from the first component 20 to the third component 30 are assumed to be 50ns, and in this case, the delay T for transmitting target data by the third component 30 is greater than or equal to 100ns, and the corresponding frequency freq is less than or equal to 10MHz from the time of transmitting a read request to acquiring target data by the second component 20, which increases the communication rate compared to the former method.

When the condition that the period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time from the second component 20 to the third component 30, the uplink delay time from the third component 30 to the second component 20 of the target data, and the sampling setup time when the second component 20 acquires the target data is satisfied, as shown in fig. 5, when the third component 30 receives the chip select signal (CS-C), it sends the first bit (i.e., the most significant bit7 ═ 1) of the target data (MISO-C, illustratively 10101100), starting from the first rising edge of the SPI clock signal (CLK-C), the remaining data bits of the target data (bit 6-bit 0, i.e., 0101100) are sent on the falling edge of the SPI clock signal, as shown in fig. 5, and the target data (MISI-a, illustratively 10101100) is correctly received by the second component 20. The third component of the disclosed embodiment sends the target data (generally, data at a falling edge) one-half clock Cycle (CLK) in advance, can reduce the lower limit of the cycle, thereby increasing the upper limit of the communication rate, and the second component 20 can start receiving the target data at the first rising edge after sending the clock signal of the SPI communication information, so as to achieve fast and accurate reception of data.

It should be noted that, for the SPI communication method, no matter which mode is adopted, as long as it is ensured that a time difference of one clock cycle is provided between the third component sending target data and the second component receiving target data, that is, the third component sends the target data 1 clock cycle in advance, the upper computer can correctly read the data sent by the third component, and the communication system according to the embodiment of the present disclosure is used to realize the improvement of the reading speed.

Referring to FIG. 6, FIG. 6 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

In a possible implementation, as shown in fig. 6, the SPI communication information includes an SPI clock signal and a chip select signal, and the third component 30 is further configured to:

In a possible embodiment, as shown in fig. 6, the first assembly 10 is also configured to:

the target data sent by the third component 30 is temporarily stored, and the target data is sent on the rising edge of the next SPI clock signal on which the target data is received.

In an example, the first component 10 may be provided with a register module, which includes a plurality of registers, to implement temporary storage of the received target data, and of course, the specific implementation manner of the register module is not limited in this disclosure.

This disclosed embodiment is kept in the target data of receiving through first subassembly 10, can further improve SPI communication rate, promotes the rate of SPI reading operation.

In a possible embodiment, as shown in fig. 6, the third assembly 30 is also used for:

after receiving the chip select signal, a first bit of redundancy data (DUMMY Byte) is transmitted, and the remaining bits of the redundancy data are transmitted from a first falling edge or a rising edge to a sixth falling edge or a rising edge of the SPI clock signal.

It should be noted that when the first component receives the redundant data, a discard process is performed, that is, the received data of the first byte is discarded.

In one possible embodiment, as shown in fig. 6, the second assembly 20 may also be used to:

wherein the period duration of the SPI clock signal is greater than or equal to the sum of the downstream signal delay time from the first component 10 to the third component 30 of the SPI communication information, the upstream delay time from the third component 30 to the first component 10 of the target data and the sampling setup time when the second component 20 acquires the target data,

wherein the period duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time from the second component 20 to the first component 10 of the SPI communication information, the uplink delay time from the first component 10 to the second component 20 of the target data, and the sampling setup time when the second component 20 acquires the target data.

For the second component 20, the third component 30 sends data 2 CLK cycles ahead (including sending data on the rising edge half (0.5) cycle ahead of default, and 1.5 additional cycles ahead, for a total of 2 cycles ahead), the first Byte data cannot be sent correctly, so the first Byte data is DUMMY Byte. The third component 30SPI starts to send the first valid Byte highest data bit7 (subsequent bits are sent in sequence) on the 7th (7th) CLK rising edge of the first Byte, the SPI of the first component 10 latches (DFF) and sends out the bit7 (subsequent bits are sent in sequence) on the 8th (8th) CLK rising edge of the first Byte, the SPI of the upper computer adopts the bit7 (subsequent bits are received in sequence) on the 1st (1st) CLK rising edge of the second Byte, and the data is correctly received.

In one example, the second component 20 receives the first byte of data as redundant data, and the second component 20 discards the received first byte and starts to receive valid data on the rising edge of the first CLK (i.e., the ninth rising edge after the clock signal of the SPI communication information is sent) beginning with the second byte.

In one example, the delay between SPI units of the first component 10 (the delay between the second SPI unit 120 and the first SPI unit 110) and the sample setup time when the target data is acquired by the second component 20 are negligible, the delay of SPI communication information (CS-A, CLK-A, MISO-a, etc.) sent by the second component 20 to the first component 10 and the delay of the first component 20 to the third component 30 are assumed to be 50ns, and then, in this case, since the embodiment of the present disclosure temporarily stores the target data transmitted from the third component 30 through the first component 10, through a pipeline data transmission mode, the third component 30 only needs to delay 50ns to send target data, namely, the third component sends target data with the period T more than or equal to 50ns, the corresponding frequency freq is less than or equal to 20MHz, it can be seen that this way greatly increases the rate of communication between the third component 30 and the second component 20.

It should be noted that, in the drawings of the embodiments of the present disclosure, in order to show that the second component 20 has a sufficient holding time when sampling MISO-C, and to represent the delay between the respective clock signals and the delay between the respective data signals MISO, the embodiments of the present disclosure adopt an alignment manner between the signals when drawing the drawings, and the transmission time of the data is not strictly aligned with the clock signal CLK, which should not be considered as a limitation of the present disclosure.

The embodiment of the present disclosure satisfies the condition that the cycle duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information from the first component 10 to the third component 30, the uplink delay time of the target data from the third component 30 to the first component 10 and the sampling setup time when the second component 20 acquires the target data, the cycle duration of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information from the second component 20 to the first component 10, the uplink delay time of the target data from the first component 10 to the second component 20 and the sampling setup time when the second component 20 acquires the target data, as shown in fig. 6, so that the third component 30, after receiving the chip select signal (CS-C), transmitting a first bit of redundant data (DUMMY Byte) and transmitting the remaining bits of the redundant data from a first falling edge or rising edge to a sixth falling edge or rising edge of the SPI clock signal (CLK-C), and, after receiving the chip select signal, counting the SPI clock signal, transmitting the target data (MISO-C is 10101100, for example) from a rising edge of a seventh clock cycle of the SPI clock signal at a rising edge of the SPI clock signal, and causing the first component 10 to temporarily store the target data (data MISO-B0 received by the first component 10) transmitted by the third component 30, obtaining temporarily stored target data (MISO-B1), and transmitting the target data at a rising edge of the SPI clock signal next to the reception of the target data, enabling the second component 20 to receive the target data at a ninth rising edge after the transmission of the SPI communication information clock signal datA, as shown in fig. 6, the second component 20 correctly receives the target datA (MISO-A is illustratively 10101100), and it can be seen that the disclosed embodiments can achieve accurate and fast communication of the various components of the system.

In one possible embodiment, the third component is further configured to:

It should be noted that, for the SPI communication method, no matter which mode is adopted, as long as it is ensured that a time difference of two clock cycles exists between the third component sending target data and the second component receiving target data, that is, the third component sends the target data 2 clock cycles in advance, the upper computer can correctly read the data sent by the third component, and the communication system according to the embodiment of the present disclosure is used to realize the improvement of the reading speed.

Referring to table 2, table 2 shows an illustration of the time consumption for reading data using the related art and reading data using the embodiments of the present disclosure.

TABLE 2

As shown in table 2, when the scheme corresponding to fig. 6 is adopted, the time for reading the data of the third component 30 by the second component 20 of the embodiment of the present disclosure is much shorter than the time for reading the data by the related art.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A communication system, comprising a first component, a second component, and at least one third component, the first component and the second component communicating via a first SPI line, the first component and the at least one third component communicating via at least a second SPI line, wherein,

2. The system of claim 1, wherein the third component sends the target data N/2 clock cycles ahead of the second component receiving the target data, wherein N is an integer.

3. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal, the third component further configured to:

4. The system of claim 3, wherein the second component is further configured to:

wherein a time difference between the third component issuing the target data and the second component receiving the target data is one half clock cycle,

5. The system of claim 1, wherein said SPI communication information includes an SPI clock signal and a chip select signal,

6. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal, the third component further configured to:

7. The system of claim 6, wherein the second component is further configured to:

wherein a time difference between the third component issuing the target data and the second component receiving the target data is one clock cycle,

8. The system of claim 1, wherein said SPI communication information includes an SPI clock signal and a chip select signal,

9. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal, the third component further configured to:

10. The system of claim 9, wherein the first component is further configured to:

11. The system of claim 10, wherein the third component is further configured to:

12. The system of any of claims 9-11, wherein the second component is further configured to:

wherein a time difference between the third component issuing the target data and the second component receiving the target data is two clock cycles,

13. The system of claim 1, wherein said SPI communication information includes an SPI clock signal and a chip select signal,

14. The system of claim 13, wherein the third component is further configured to:

15. The system of claim 1, wherein when the first SPI line and the second SPI establish a connection, the first component is further configured to:

16. The system of claim 15, wherein the first component comprises a line switch, the first component further configured to:

17. The system of claim 16, wherein the first component is further configured to:

18. The system of claim 1, wherein the first component, the third component comprises a display, a smartphone, or a portable device, and the second component comprises an upper computer.