CN111597134A - Data transmission device and method - Google Patents
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- CN111597134A CN111597134A CN202010436413.XA CN202010436413A CN111597134A CN 111597134 A CN111597134 A CN 111597134A CN 202010436413 A CN202010436413 A CN 202010436413A CN 111597134 A CN111597134 A CN 111597134A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Abstract
The present disclosure relates to a data transmission device and method, the device includes a first module and at least one second module, the first module and the second module communicate through a serial peripheral interface, the second module is electrically connected to the first module through a main input and a slave output signal line, wherein: the second module is used for determining a first time length according to a set clock frequency and sending data to be sent to the master-input slave-output signal line in advance of the first time length, and the first module is used for receiving the data to be sent through the master-input slave-output signal line. According to the embodiment of the disclosure, by determining the first duration corresponding to the clock frequency, the second module sends the data to be sent to the first module in advance of the first duration, the clock frequency delay can be eliminated, and the accuracy and the effectiveness of data transmission at the clock frequency are ensured.
Description
Technical Field
The present disclosure relates to the field of data transmission, and in particular, to a data transmission apparatus and method.
Background
SPI (Serial Peripheral Interface) is a high-speed, full-duplex communication bus. It uses three buses and one or more chip select lines for data transfer between master and slave devices. The three buses are SCK (Serial Clock), MOSI (Master Output/Slave Input), MISO (Master Input/Slave Output), and chip select line cs (chip select) for the Master device to select and communicate with a Slave device on the bus.
However, when the SPI is used for data transmission in the related art, data transmission errors are often generated due to large delay, and the data transmission accuracy and the data transmission effectiveness are low.
Disclosure of Invention
In view of the above, the present disclosure provides a data transmission device, which includes a first module and at least one second module, wherein the first module and the second module communicate through a serial peripheral interface, and the second module is electrically connected to the first module through a master-input slave-output signal line, wherein:
the second module is used for determining a first time length according to the set clock frequency and sending the data to be sent to the master-input slave-output signal line in advance of the first time length,
the first module is used for receiving the data to be transmitted through the main input and output signal line.
In a possible embodiment, the determining the first duration according to the set clock frequency includes:
determining a delay parameter according to the set clock frequency and a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the clock frequency and the delay parameter;
and determining the first duration according to the delay parameter and the period corresponding to the clock frequency.
In a possible implementation manner, the determining the first duration according to the delay parameter and the period corresponding to the clock frequency includes:
and taking one half of the product of the delay parameter and the period as the first duration.
In a possible implementation, the second module includes a plurality of test registers, the second module is further electrically connected to the first module through a main output slave input signal line, wherein the first module is further configured to:
writing test data from an input signal line to the test register through the master output at a first clock frequency;
receiving data sent by the second module through the main input-output signal line;
and comparing the test data with the data sent by the second module, and sending a first instruction to the second module when the test data and the data are the same, or sending a second instruction to the second module when the test data and the data are not the same.
In one possible implementation, the second module is further configured to:
determining one or more first test durations by using a period of one or more test delay parameters corresponding to the first clock frequency;
and when the second instruction is received, sending the data in the test register to the first module in advance of the first test duration.
In one possible implementation, the second module is further configured to:
and adjusting the preset delay parameters according to the preset step length to obtain a plurality of test delay parameters.
In one possible implementation, the second module is further configured to:
under the condition of receiving the second instruction, adjusting the adjacent previous test delay parameter by using a preset step length;
determining a second test duration by using the period corresponding to the adjusted test delay parameter and the first clock frequency;
and sending the data in the test register to the first module in advance of the second test duration.
In one possible implementation, the second module is further configured to:
and determining a test delay parameter corresponding to the first clock frequency under the condition of receiving the first instruction to obtain a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the first clock frequency and the corresponding test delay parameter.
In a possible implementation, the first module and the second module are terminals.
According to another aspect of the present disclosure, a data transmission method is provided, where the data transmission method is applied to a data transmission device, the device includes a first module and at least one second module, the first module and the second module communicate through a serial peripheral interface, and the second module is electrically connected to the first module through a master-input slave-output signal line, where the method includes:
the second module determines a first time length according to the set clock frequency and sends data to be sent to the master-input slave-output signal line in advance of the first time length,
and the first module receives the data to be transmitted through the main input and slave output signal line.
In a possible embodiment, the determining the first duration according to the set clock frequency includes:
determining a delay parameter according to the set clock frequency and a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the clock frequency and the corresponding delay parameter;
and determining the first duration according to the delay parameter and the period corresponding to the clock frequency.
According to the embodiment of the disclosure, by determining the first duration corresponding to the clock frequency, the second module sends the data to be sent to the first module in advance of the first duration, the clock frequency delay can be eliminated, and the accuracy and the effectiveness of data transmission at the clock frequency are ensured.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 illustrates a data transmission apparatus according to an embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a data transmission device according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of data transmission of a data transmission device according to an embodiment of the present disclosure.
Fig. 4 shows a schematic diagram of data transmission according to an embodiment of the present disclosure.
Fig. 5 shows a schematic diagram of data transmission according to an embodiment of the present disclosure.
Fig. 6 and 7 are schematic diagrams illustrating data transmission according to an embodiment of the present disclosure.
Fig. 8 shows a schematic diagram of determining a test delay parameter according to an embodiment of the present disclosure.
Fig. 9 shows a schematic diagram of data transmission according to an embodiment of the present disclosure.
Fig. 10, 11, and 12 show data transmission diagrams according to an embodiment of the present disclosure.
Fig. 13 shows a flow chart of a data transmission method according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Referring to fig. 1, fig. 1 illustrates a data transmission apparatus according to an embodiment of the disclosure.
The device comprises a first module 10 and at least one second module 20, wherein the first module 10 and the second module 20 communicate through a serial peripheral interface, the second module 20 is electrically connected to the first module 10 through a main input and output signal line MISO, and the device comprises:
the second module 20 is configured to determine a first duration according to the set clock frequency, send data to be sent to the master-input-slave-output signal line MISO in advance of the first duration,
the first module is used for receiving the data to be transmitted through the main input slave output signal line MISO.
Through the device, the first duration corresponding to the clock frequency is determined, and the second module sends the data to be sent to the first module in advance of the first duration, so that the clock frequency delay can be eliminated, and the accuracy and the effectiveness of data transmission at the clock frequency are ensured.
In one example, the first module 10 and the second module 20 may include terminals including, but not limited to, User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), and the like, including devices providing voice, video, and/or data and the like with connectivity to a user, such as handheld devices with wireless connection capability, vehicle-mounted devices, and the like. Currently, some examples of terminals are: a mobile phone (mobile phone), a tablet computer, a notebook computer, a palm top computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self), a wireless terminal in remote surgery (remote medical supply), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in city (smart city), a wireless terminal in smart home (smart home), a wireless terminal in vehicle networking, and the like.
In one example, the first module may be a master module and the second module may be a slave module.
Referring to fig. 2, fig. 2 is a schematic diagram of a data transmission device according to an embodiment of the disclosure.
In one example, as shown in fig. 2, a chip select signal line CS, a clock signal line SCK, and a master output slave input signal line MOSI may be further included between the first module 10 and the second module 20, wherein the chip select signal line CS and the clock signal line SCI may be controlled by the first module.
In one example, the first module 10 may transmit a chip select signal through a chip select signal line CS to select the corresponding second module 20, the first module 10 may control a clock frequency of the second module 20 through a clock signal line SCK, the first module 10 may transmit data to the second module 20 through a main output slave input signal line MOSI, and the second module 20 may transmit data to the first module through a main input slave output signal line MISO.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating data transmission of a data transmission device according to an embodiment of the disclosure.
In one example, as shown in fig. 3, the data transmission device may include 4 communication modes through the serial peripheral interface SPI, which are determined by CPOL (clock polarity) and CPHA (clock phase). The clock polarity is used to determine the level state of the clock when idle, and the clock phase is used to determine whether the SPI samples on the first edge or the second edge.
In one example, as shown in fig. 3, when both CPOL and CPHA are 0, both the first module and the second module drive data (or transmit data) at the falling edge of the clock signal, and sample data at the rising edge; when the CPOL is 0 and the CPHA is 1, the first module and the second module drive data at the rising edge of the clock signal and sample data at the falling edge; when the CPOL is 1 and the CPHA is 0, the first module and the second module drive data at a rising edge and sample data at a falling edge; when both CPOL and CPHA are 1, both the first and second modules drive data on the falling edge of the clock signal and sample data on the rising edge.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating data transmission according to an embodiment of the disclosure.
Taking CPOL and CPHA as 0 as an example, as shown in fig. 4, the first module drives data to the main input/output slave input signal line MOSI on the falling edge of the clock signal, and samples data on the main input/output slave signal line MISO on the rising edge of the clock signal; the second block drives data to the master-in slave-out signal line MISO on the falling edge of the clock signal and samples data on the master-out slave-in signal MOSI on the rising edge of the clock signal.
The following is an exemplary description of the delay in the transmission of data between the first module and the second module.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating data transmission according to an embodiment of the disclosure.
In practical applications, since there is a delay in the transmission of data (or SPI signals) between the first module and the second module and in the transmission of signals within the second module, the actual arrival of data at the first module will cause a delay.
In one example, as shown in fig. 5, the DELAY may include a transmission DELAY between board levels, which may be described specifically as a DELAY1(B2B _ DELAY) between the SPI signal being transmitted from a pin (pad) of the first module to a pin of the second module or from the pin of the second module to the pin of the first module.
In one example, as shown in fig. 5, the Delay may also include a Delay2(Trans _ Delay) between the transmission of the SPI signal from the pin to the processing module inside the second module chip in the second module.
In one example, as shown in fig. 5, the DELAY may also include a DELAY3(D2B _ DELAY) from a processing module (e.g., SPI chip) inside the second module to a pin of the second module.
Referring to fig. 6 and 7 together, fig. 6 and 7 show schematic diagrams of data transmission according to an embodiment of the disclosure.
In one example, as shown in fig. 6 and 7, if the clock frequency is too high or the delay of the signal during transmission is high, the data transmitted in the MISO signal cannot meet the timing requirement of the SPI, so that the first module may have an error in sampling the MISO signal, for example, the first module may sample the wrong data on the MISO signal line or may have a metastable state. Therefore, due to hardware limitations, it is often difficult to achieve a desired clock frequency, limiting the increase in clock frequency.
The upper half of fig. 6 (and fig. 7) shows the SPI signaling of the first module, and the lower half shows the SPI signaling of the second module. In one example, assume that for both the first and second modules, data is sampled on the rising edge of SCK and driven on the falling edge of SCK. From the perspective of the second module (the lower half of fig. 6 and 7), the data on CS, SCK, and MOSI, which are the data transmitted from the first module to the second module, are the same, and assuming that the transmission delays of the signals of the three signal lines are the same at each stage, the time of arrival of the three signals CS, SCK, and MOSI at the second module is the same. The MISO signal of the MISO signal line is transmitted from the second module to the first module. Because the three signal lines CS, SCK, and MOSI have a delay before reaching the second module, and the MISO signal is transmitted from the second module to the first module after a delay, the MISO signal has a larger delay than CS, SCK, and MOSI. If the delay of the signal on the MISO signal line is large, the first module should sample the corresponding data at the rising edge of SCK, for example, BIT6 at SCK 2, but because the delay is large, MBIT is sampled at SCK 2, and more seriously, an indeterminate state is sampled, which results in the failure of SPI transmission (fig. 6, ERR MISO). And referring to fig. 7, the second module drives the data to the MISO in advance by a certain time, the first module can collect the correct data, and the SPI is transmitted successfully (through the MISO).
According to the embodiment of the disclosure, by determining the first duration corresponding to the clock frequency, the second module sends the data to be sent to the first module in advance of the first duration, the clock frequency delay can be eliminated, and the accuracy and the effectiveness of data transmission at the clock frequency are ensured. When the clock frequency needs to be increased, a higher clock frequency can be set through the first module, and after the clock frequency is determined by the second module, the corresponding first time length can be determined according to the set clock frequency, so that the delay is eliminated.
In a possible implementation, the determining the first duration according to the set clock frequency may include:
determining a delay parameter according to the set clock frequency and a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the clock frequency and the delay parameter;
and determining the first duration according to the delay parameter and the period corresponding to the clock frequency.
In a possible implementation manner, the determining the first duration according to the delay parameter and the period corresponding to the clock frequency includes:
and taking one half of the product of the delay parameter and the period as the first duration.
In an example, the preset mapping relationship may include mapping relationships between a plurality of clock frequencies and corresponding delay parameters, and a specific number of the mapping relationships in the preset mapping relationship is not limited in the embodiment of the present disclosure, and may be set by a person skilled in the art as needed.
In addition, the specific form of the preset mapping relationship is not limited in the embodiment of the present disclosure, and the preset mapping relationship may be in a form of a table or other forms.
Through the device, the delay parameter and the corresponding first time length can be quickly determined according to the clock frequency, so that the delay is eliminated.
The preset mapping relationship may be obtained by testing in advance, and a possible implementation of determining the preset mapping relationship is described below.
In a possible implementation, the second module may include a plurality of test registers (for example, may be 4), and the first module may further be configured to:
writing test data from an input signal line to the test register through the master output at a first clock frequency;
receiving data sent by the second module through the main input-output signal line;
and comparing the test data with the data sent by the second module, and sending a first instruction to the second module when the test data and the data are the same, or sending a second instruction to the second module when the test data and the data are not the same.
In one example, assuming that the test register includes a register with an address of 0xaa, the first module may access the test register (0xaa) and write data 0x5a5a5a (or others), when the second module sends the data in the test register (0xaa) to the first module, if the data is 0x5a5a5a, the first module may determine that the written data and the read data are the same and that the data transfer is correct, and the first module may send a first instruction to the second module; if the data returned by the second module is other, the data transmission error is determined, and the first module can send a second instruction to the second module.
The embodiment of the present disclosure does not limit the specific form of the first instruction and the second instruction, and those skilled in the art can set the specific form as needed.
The second module may change the time for sending the MISO signal during the test, for example, may send data in the test register to the MISO signal line in advance of a first test duration, select another first test duration to send again upon receiving the second instruction, and iterate a plurality of times until the first instruction is received to determine the first test duration or delay parameter corresponding to the clock frequency. An exemplary description follows.
In one possible implementation, the second module may be further configured to:
determining one or more first test durations by using a period of one or more test delay parameters corresponding to the first clock frequency;
and when the second instruction is received, sending the data in the test register to the first module in advance of the first test duration.
In one possible implementation, the second module is further configured to:
and adjusting the preset delay parameters according to the preset step length to obtain a plurality of test delay parameters.
In the embodiment of the present disclosure, a combination of test delay parameters may be determined in advance, a combination of first test durations is determined according to the combination of the test delay parameters, and one combination of the first test durations is selected from the combinations of the first test durations each time for sending data in advance, where the selection mode may be from large to small, or from small to large, or may be a random selection, and thus, the embodiment of the present disclosure is not limited.
For example, assuming that the initial preset delay parameter is 0 and the preset step size is 1, the preset delay parameter is adjusted by the preset step size to obtain a plurality of test delay parameters, the preset delay parameter and the preset step size may be accumulated to obtain a combination {0, 1, 2 … } of the plurality of test delay parameters, one or more first test durations may be determined by using a period corresponding to the first clock frequency of the one or more test delay parameters, and each test delay parameter in the combination of test delay parameters may be multiplied by T/2, respectively, to obtain a combination {0, T/2, T … } of the plurality of first test durations.
In an example, for an initial condition, the first module may send the second instruction to the second module, so that the second module selects one of the first test durations to send data, or the second module may select one of the first test durations by default to send data, for example, in the initial condition, the second module may select the first test duration to be 0, that is, not send in advance.
In a possible implementation manner, the second module may also determine only the currently required test delay parameter and the first test duration when receiving the second instruction.
In one possible implementation, the second module may be further configured to:
under the condition of receiving the second instruction, adjusting the adjacent previous test delay parameter by using a preset step length;
determining a second test duration by using the period corresponding to the adjusted test delay parameter and the first clock frequency;
and sending the data in the test register to the first module in advance of the second test duration.
In one possible implementation, the second module is further configured to:
and determining a test delay parameter corresponding to the first clock frequency under the condition of receiving the first instruction to obtain a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the first clock frequency and the corresponding test delay parameter.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating determination of a test delay parameter according to an embodiment of the disclosure.
In an example, as shown in fig. 8, when the second module is powered on and receives a second instruction (or default to an initial condition), the second module may determine a first test duration by using an initial test delay parameter, and if the initial test delay parameter is 0, determine that data is not driven to the MISO signal line in advance, the second module normally sends data to the first module, the first module compares the received data with the stored data, determines whether the received data is the same as the stored data, if the received data is different from the stored data, the first module sends the second instruction, and if the received data is the same as the stored data, the first module sends the first instruction.
When the second module receives the second instruction, the second module adjusts the previous test delay parameter (0) by using a preset step length (assumed to be 1), where N is N +1, a new test delay parameter can be obtained to be 1, the second test duration is determined to be T/2 by using the period corresponding to the adjusted test delay parameter and the first clock frequency, the second module sends data to the MISO signal line in advance by T/2, and the first module compares the data with the stored data again after acquiring the data on the MISO signal line.
And continuously iterating the processes until the first module determines that the acquired data is the same as the stored data, sending a first instruction to the second module by the first module, and if the test delay parameter is 2 at the moment, determining that the test delay parameter at the current clock frequency is 2 or the time length required to be sent in advance is T by the second module.
Of course, the above description is exemplary, the preset step size may be other, and the embodiment of the present disclosure is not limited thereto.
After the mapping relationship between the clock frequency and the delay parameter is determined, the next clock frequency can be set, and the preset mapping relationship between a plurality of clock frequencies and the corresponding delay parameters can be obtained through the above description.
In one possible embodiment, when the second module determines the first duration according to the set clock frequency and transmits data to the MISO in advance of the first duration, the first module may take the data of the received first byte (byte) as redundant data (dummy) when receiving the data.
From the perspective of the first module, the first byte data on the MOSI signal line is valid. Generally, we use the first byte as the address of the test register, for example, (0xaa), and the second module sends the data of the corresponding address to the MISO signal line after receiving the address, that is, the data in the test register is sent only after the second byte, so the first byte can be used as dummy data.
Because SPI communication is full duplex, data can be sent and received simultaneously. From the perspective of the first module, the first byte transmits and receives data on the MISO, but the second module does not receive the address at this time, so that the first byte data can be regarded as dummy data, and the second byte starts to be the data in the true test register, thereby ensuring the accuracy of data transmission.
Referring to fig. 9, fig. 9 is a schematic diagram illustrating data transmission according to an embodiment of the disclosure.
As shown in fig. 9, fig. 9 is divided into a first module transmission diagram (upper first module), a comparison group second module transmission diagram (middle second module), and an experiment group second module transmission diagram (lower second module), where the comparison group second module does not use a mode of sending data in advance (MISOA), and it can be seen in the first module transmission diagram that, for the data transmitted by the comparison group second module, the first module receives an error (ERR MISOA); while the second module in the experimental group drives the data to the MISOB N T/2 in advance, the data received by the first module through the MISOB is correct (through the MISOB).
This disclosed embodiment is through confirming and configuring the time delay parameter N of second module, on N T2 drives the data of second module to SPI MISO signal line in advance, under SPI high-speed transmission, can guarantee the reliability of SPI transmission.
Referring to fig. 10, 11, and 12, fig. 10, 11, and 12 show schematic diagrams of data transmission according to an embodiment of the disclosure.
In one example, fig. 10 shows a data transmission diagram with a delay parameter of 0, and as shown in fig. 10, when the second module determines that the delay parameter is 0, data is normally sent to the MISO, i.e., data is not driven to the MISO in advance.
In one example, fig. 11 shows a data transmission diagram with a delay parameter of 1, as shown in fig. 11, when the second module determines that the delay parameter is 1, the second module drives data onto the MISO signal line in advance by T/2 to meet the requirement of high-speed SPI transmission, and as can be seen from fig. 11, it should originally drive BIT6 out at the falling edge of the 1 st CLK, and the second module drives BIT6 onto the MISO signal line in advance by T/2, that is, at the rising edge of the 1 st CLK.
In one example, fig. 12 shows a data transmission diagram with a delay parameter of 2, and as shown in fig. 12, when the second module determines that the delay parameter is 2, the second module drives data onto the MISO signal line in advance of T to meet the requirement of high-speed SPI transmission.
Through the above description, by determining the first duration and driving the second duration data onto the MISO signal line in advance by the second module, the error caused by delay can be eliminated, thereby ensuring the accuracy and reliability of SPI transmission.
Referring to fig. 13, fig. 13 is a flowchart illustrating a data transmission method according to an embodiment of the disclosure.
The method is applied to a data transmission device, the device comprises a first module and at least one second module, the first module and the second module are communicated through a serial peripheral interface, and the second module is electrically connected to the first module through a main input and output signal line, wherein as shown in fig. 13, the method comprises the following steps:
step S11, the second module determines a first time length according to the set clock frequency and sends the data to be sent to the master-input slave-output signal line in advance of the first time length,
step S12 is that the first module receives the data to be transmitted through the master input slave output signal line.
By the method, the first duration corresponding to the clock frequency is determined, and the second module sends the data to be sent to the first module in advance of the first duration, so that the clock frequency delay can be eliminated, and the accuracy and the effectiveness of data transmission at the clock frequency are ensured.
In a possible implementation, the determining the first duration according to the set clock frequency may include:
determining a delay parameter according to the set clock frequency and a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the clock frequency and the corresponding delay parameter;
and determining the first duration according to the delay parameter and the period corresponding to the clock frequency.
It should be noted that the output transmission method is a method corresponding to the data transmission apparatus, and for the specific description, reference is made to the introduction of the data transmission apparatus, which is not described herein again.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (11)
1. A data transmission device is characterized in that the device comprises a first module and at least one second module, the first module and the second module are communicated through a serial peripheral interface, the second module is electrically connected to the first module through a main input and output signal line, wherein:
the second module is used for determining a first time length according to the set clock frequency and sending the data to be sent to the master-input slave-output signal line in advance of the first time length,
the first module is used for receiving the data to be transmitted through the main input and output signal line.
2. The apparatus of claim 1, wherein the determining the first duration according to the set clock frequency comprises:
determining a delay parameter according to the set clock frequency and a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the clock frequency and the delay parameter;
and determining the first duration according to the delay parameter and the period corresponding to the clock frequency.
3. The apparatus of claim 2, wherein determining the first duration according to the delay parameter and a period corresponding to the clock frequency comprises:
and taking one half of the product of the delay parameter and the period as the first duration.
4. The apparatus of claim 1, wherein the second module comprises a plurality of test registers, the second module further electrically connected to the first module through a main output from an input signal line, wherein the first module is further configured to:
writing test data from an input signal line to the test register through the master output at a first clock frequency;
receiving data sent by the second module through the main input-output signal line;
and comparing the test data with the data sent by the second module, and sending a first instruction to the second module when the test data and the data are the same, or sending a second instruction to the second module when the test data and the data are not the same.
5. The apparatus of claim 4, wherein the second module is further configured to:
determining one or more first test durations by using a period of one or more test delay parameters corresponding to the first clock frequency;
and when the second instruction is received, sending the data in the test register to the first module in advance of the first test duration.
6. The apparatus of claim 5, wherein the second module is further configured to:
and adjusting the preset delay parameters according to the preset step length to obtain a plurality of test delay parameters.
7. The apparatus of claim 4, wherein the second module is further configured to:
under the condition of receiving the second instruction, adjusting the adjacent previous test delay parameter by using a preset step length;
determining a second test duration by using the period corresponding to the adjusted test delay parameter and the first clock frequency;
and sending the data in the test register to the first module in advance of the second test duration.
8. The apparatus of any of claims 4-7, wherein the second module is further configured to:
and determining a test delay parameter corresponding to the first clock frequency under the condition of receiving the first instruction to obtain a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the first clock frequency and the corresponding test delay parameter.
9. The apparatus of claim 1, wherein the first module and the second module are terminals.
10. A data transmission method is applied to a data transmission device, the device comprises a first module and at least one second module, the first module and the second module are communicated through a serial peripheral interface, and the second module is electrically connected to the first module through a main input and output signal line, wherein the method comprises the following steps:
the second module determines a first time length according to the set clock frequency and sends data to be sent to the master-input slave-output signal line in advance of the first time length,
and the first module receives the data to be transmitted through the main input and slave output signal line.
11. The method of claim 10, wherein determining the first duration based on the set clock frequency comprises:
determining a delay parameter according to the set clock frequency and a preset mapping relation, wherein the preset mapping relation comprises the mapping relation between the clock frequency and the corresponding delay parameter;
and determining the first duration according to the delay parameter and the period corresponding to the clock frequency.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112860613A (en) * | 2021-04-06 | 2021-05-28 | 北京集创北方科技股份有限公司 | Communication system |
| CN115333667A (en) * | 2022-10-12 | 2022-11-11 | 中科声龙科技发展（北京）有限公司 | Method for adjusting time sequence and communication system |
| CN112860613B (en) * | 2021-04-06 | 2024-04-19 | 北京集创北方科技股份有限公司 | Communication system |
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- 2020-05-21 CN CN202010436413.XA patent/CN111597134A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112860613A (en) * | 2021-04-06 | 2021-05-28 | 北京集创北方科技股份有限公司 | Communication system |
| CN112860613B (en) * | 2021-04-06 | 2024-04-19 | 北京集创北方科技股份有限公司 | Communication system |
| CN115333667A (en) * | 2022-10-12 | 2022-11-11 | 中科声龙科技发展（北京）有限公司 | Method for adjusting time sequence and communication system |
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