CN114064554A - Slave equipment and method for configuring MIPI (Mobile industry processor interface) line sequence thereof - Google Patents

Slave equipment and method for configuring MIPI (Mobile industry processor interface) line sequence thereof Download PDF

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Publication number
CN114064554A
CN114064554A CN202010761002.8A CN202010761002A CN114064554A CN 114064554 A CN114064554 A CN 114064554A CN 202010761002 A CN202010761002 A CN 202010761002A CN 114064554 A CN114064554 A CN 114064554A
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China
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mipi
line
value
slave device
register
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CN202010761002.8A
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Chinese (zh)
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汪瀚
王富中
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Galaxycore Shanghai Ltd Corp
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Galaxycore Shanghai Ltd Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
    • G06F2015/763—ASIC

Abstract

The embodiment of the invention provides a slave device and a method for configuring a MIPI (Mobile industry processor interface) line sequence thereof, wherein the method comprises the following steps: step a, writing a first sequence of MIPI of preset slave equipment into a first register; step b, setting a second register as a first value, and enabling all MIPI lines of the slave equipment and enabling pull-up resistors corresponding to all MIPI lines respectively based on the first value; step c, receiving an initialization instruction sent by the host equipment; and d, if the initialization instruction comprises the second thread sequence of the MIPI of the host device, writing the second thread sequence into the first register, setting the second register to be a second value, and configuring the thread sequence of the MIPI of the slave device based on the second value and the second thread sequence. According to the technical scheme of the embodiment of the invention, a special pad is not required to be set for configuring the MIPI of the slave equipment, so that the pad resource on the slave IC is saved.

Description

Slave equipment and method for configuring MIPI (Mobile industry processor interface) line sequence thereof
Technical Field
The invention relates to the technical field of communication, in particular to slave equipment and a method for configuring the MIPI (Mobile industry processor interface) sequence of the slave equipment.
Background
A Mobile Industry Processor Interface (MIPI) is an open standard and specification established by the MIPI alliance for a Mobile application Processor, and is used for standardizing an Interface inside a Mobile device (which may also be referred to as a slave device) into a standard internal Interface, and includes a Camera Interface (CSI), a Display Screen Interface (DSI), a Radio Frequency Interface (DigRF), and the like. An external device (which may also be referred to as a master device) that communicates with the standard internal interface of the slave device includes a processor that controls communication with the slave device.
The standard internal interface of the mobile device has a physical layer module (e.g., either a D-PHY module or a C-PHY module); the physical layer module has a plurality of lanes (Lane) including a data Lane and a clock Lane, the data Lane including two modes of operation: a High-Speed (HS) mode and a Low-Power (LP) mode.
The line sequence of the host device MIPI may be different from that of the slave device MIPI, and in the existing scheme, a dedicated pad (pad) is disposed on an Integrated Circuit (IC) of the slave device to implement the configuration of the MIPI line sequence, for example, for 4-line MIPI application, 4 pads are generally occupied. However, setting a dedicated pad occupies a large amount of pad resources on the slave IC.
Disclosure of Invention
The invention solves the technical problem that setting a special pad occupies pad resources on a slave IC and the like.
To solve the foregoing technical problem, an embodiment of the present invention provides a method for configuring a MIPI thread sequence of a slave device, including: step a, writing a first sequence of MIPI of preset slave equipment into a first register; step b, setting a second register as a first value, and enabling all MIPI lines of the slave equipment and enabling pull-up resistors corresponding to all MIPI lines respectively based on the first value; step c, receiving an initialization instruction sent by the host equipment; and d, if the initialization instruction comprises the second thread sequence of the MIPI of the host device, writing the second thread sequence into the first register, setting the second register to be a second value, and configuring the thread sequence of the MIPI of the slave device based on the second value and the second thread sequence.
Optionally, the method further comprises: step e, if the initialization instruction does not include the line sequence information of the MIPI of the host equipment, setting a second register to be a second value; and configuring a line order of the MIPI of the slave device based on the second value and the first line order.
Optionally, the sequence of the MIPI lines includes the number of MIPI lines and the arrangement sequence thereof.
Optionally, the first value is one of 0 or 1 and the second value is the other of 0 or 1.
Optionally, comprising: and keeping the pull-up resistor corresponding to the non-enabled MIPI circuit enabled and removing the pull-up resistor corresponding to the enabled MIPI circuit from the enabled MIPI circuit based on the second value and the wire sequence of the MIPI required to be configured by the slave device.
Optionally, step c includes receiving an initialization command sent by the host device in the lp (low power) mode, where the initialization command includes a second line sequence.
Optionally, step a comprises: configuring an LP output logic unit in the slave device as an AND logic based on the first value; the step c comprises the following steps: an LP receiving unit in the slave equipment receives and outputs an initialization instruction on one MIPI line and outputs a high level on the rest MIPI lines; the step d comprises the following steps: one input end of the LP output logic unit receives the initialization command output by the LP receiving unit, the other input ends receive the high level output by the LP receiving unit, the data at each input end is subjected to AND logic calculation to output the initialization command, and the data processing unit in the slave equipment receives the initialization command output by the LP output logic unit to obtain a second line sequence and writes the second line sequence into the first register.
Optionally, comprising: the AND logic of the LP output logic unit is de-configured based on the second value to enable the enabled MIPI line to directly output data transmitted by the host device through the LP mode to the data processing unit.
Optionally, step c comprises: the HS enabling control unit in the slave device detects an HS enabling sequence sent by the host device, and the HS receiving unit in the slave device receives an initialization command sent by the host device through an HS (high speed) mode.
Optionally, comprising: and when the HS enabling control unit detects the HS enabling sequence, the pull-up resistor corresponding to the MIPI line where the HS enabling sequence is located is enabled to be removed so as to receive the initialization command.
Optionally, comprising: and enabling a pull-up resistor corresponding to the MIPI circuit where the HS enabling sequence is located after the initialization command is received.
Optionally, step c comprises: the HS receiving unit in the slave equipment receives and outputs an initialization instruction to the data processing unit in the slave equipment; the initialization instruction comprises a data packet in an HS format; step e comprises: and the data processing unit processes the initialization instruction according to the first thread to obtain the processed initialization instruction.
An embodiment of the present invention further provides a slave device, including: the first register is suitable for storing the line sequence of the MIPI, and the received line sequence of the MIPI is written into the first register as the line sequence of the MIPI of the slave equipment; a second register adapted to store an instruction issued by the data processing unit and to configure the second register to a first value or a second value based on the instruction; a plurality of receiving units which are respectively arranged on each MIPI line of the slave equipment and are suitable for receiving and outputting an initialization instruction sent by the host equipment and enabling each MIPI line based on a first value; a plurality of pull-up resistors respectively corresponding to the MIPI lines and adapted to enable the plurality of pull-up resistors based on a first value; the data processing unit is suitable for receiving the initialization instruction sent by the receiving unit; and if the initialization instruction comprises the line sequence of the MIPI of the host equipment, writing the line sequence of the MIPI of the host equipment into the first register.
Optionally, the pull-up resistor is adapted to keep the pull-up resistor corresponding to the non-enabled MIPI line enabled and to de-enable the pull-up resistor corresponding to the enabled MIPI line based on the second value and the MIPI line order of the slave device.
Optionally, the receiving unit is an LP receiving unit, which is adapted to receive and output an initialization instruction sent by the host device through an LP mode on one MIPI line and output a high level on the remaining MIPI lines, where the initialization instruction includes a line order of the MIPI of the host device; the slave device also comprises an LP output logic unit which is suitable for being configured into an AND logic based on the first value, one input end of the LP output logic unit receives the initialization command output by the LP receiving unit, and the other input ends of the LP output logic unit receive the high level output by the LP receiving unit, and data of each input end is subjected to AND logic calculation to output the initialization command; the data processing unit is adapted to receive the initialization instruction output by the LP output logic unit.
Optionally, the LP output logic unit is adapted to deconfigure its and logic based on the second value to enable the enabled MIPI line to output data sent by the host device over the LP mode directly to the data processing unit.
Optionally, the receiving unit is an HS receiving unit adapted to receive an initialization instruction sent by the host device through HS mode.
Optionally, the method further comprises: the HS enabling control unit is suitable for detecting an HS enabling sequence in the initialization command, sending a release command of enabling release to a pull-up resistor corresponding to an MIPI (Mobile industry processor interface) circuit where the HS enabling sequence is located, and sending a recovery command of enabling recovery to the pull-up resistor corresponding to the MIPI circuit where the HS enabling sequence is located after the initialization command is sent; the pull-up resistor corresponding to the MIPI line where the HS enabling sequence is located is suitable for receiving a releasing instruction to release the enabling and receiving a restoring instruction to restore the enabling.
Compared with the prior art, the technical scheme of the embodiment of the invention does not need to set a special pad for configuring the line sequence of the slave equipment MIPI, thereby saving pad resources on the slave IC.
Drawings
FIG. 1 is a schematic diagram of a slave device in an embodiment of the present invention;
fig. 2 is a schematic diagram of a communication system including a slave device and a master device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another slave device in an embodiment of the present invention;
FIG. 4 is a schematic diagram of yet another slave device in an embodiment of the present invention;
fig. 5 is a schematic diagram of a method for configuring MIPI sequence of a slave device according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another MIPI line sequence method for configuring a slave device in an embodiment of the present invention.
Detailed Description
In the embodiment of the invention, the slave device can communicate with the host device through one or more MIPI lines, and the communication mode can be LP mode or HS mode.
The slave device may be a mobile device containing a standard internal interface MIPI (e.g. CSI, DSI, DigRF); the master device may be a device that contains a processor to control communication with the slave devices.
In the drawings of the present invention, the same reference numerals denote the same components or steps, and the same or similar functions, positional relationships, and connection relationships are provided.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic diagram of a slave device 100 according to an embodiment of the present invention; fig. 2 is a schematic diagram of a communication system including the slave device 100 and the master device 200 according to an embodiment of the present invention.
Slave device 100 may communicate with host device 200 over one or more MIPI lines D0, D1, an.
The slave device 100 includes a first register 110, a second register 120, a plurality of receiving units 130, a plurality of pull-up resistors 140, and a data processing unit 150.
The first register 110, which may also be referred to as a line-sequential register, may receive a line sequence of the MIPI and write the received line sequence of the MIPI to the first register 110 as a line sequence of the MIPI of the slave device 100.
The thread order (i.e., the first thread order) of the MIPI of the slave device may be pre-configured before the slave device communicates with the host device. The MIPI line order may include the number of MIPI lines and the arrangement order thereof.
In a specific implementation, after obtaining the initialization command sent by the host device 200, the data processing unit 150 may send a command to the first register 110, and after receiving the command, the first register 110 may obtain the sequence of the MIPI, for example, obtain the sequence of the MIPI stored in a memory (e.g., a One Time Programmable (OTP)) and then write the received sequence of the MIPI into the slave device 100 as the sequence of the MIPI.
Based on the line order of the MIPI configured by the first register 110, the data processing unit 150 may determine the non-enabled MIPI line and the enabled MIPI line; the data processing unit 150 may directly or through the first register 110 maintain the pull-up resistor 140 corresponding to the non-enabled MIPI line enabled to avoid a fault such as power leakage caused by hanging of a pad of the MIPI line not connected to the host device 200 in the slave device 100, and disable the pull-up resistor 140 corresponding to the enabled MIPI line, so that the slave device 100 and the host device 200 may communicate based on the enabled MIPI line.
The second register 120, which may also be referred to as a flag register, may store one or more bits of data.
The second register 120 may receive an instruction sent by the data processing unit 150 and configure the second register 120 (e.g., its flag bit) to a first value or a second value based on the instruction, where the first value may be one of 0 or 1 and the second value is the other of 0 or 1.
For example, before the slave device 100 communicates with the host device 200, the data processing unit 150 may send an instruction to the second register 120, and the second register 120 may set the second register 120 to the first value after receiving the instruction.
For another example, after obtaining the initialization instruction sent by the host device 200, the data processing unit 150 may send an instruction to the second register 120, and the second register 120 sets the second register 120 to the second value after receiving the instruction.
When the value of the second register 120 is set to the first value, since the slave device 100 does not know which MIPI lines the host device 200 will send the initialization instruction from, the data processing unit 150 may enable all MIPI lines of the slave device 100 (for example, enable the receiving units 130 on all MIPI lines) directly or through the second register 120 to ensure that the slave device 100 can receive the initialization instruction of the host device 200, and may also enable the pull-up resistors 140 respectively corresponding to all MIPI lines directly or through the second register 120 to avoid faults such as power leakage caused by hanging up of pads of MIPI lines not connected to the host device in the slave device 100.
When the value of the second register 120 is set to the second value, the data processing unit 150 may configure the line order of the MIPI of the slave device 100; also, the non-enabled MIPI line and the enabled MIPI line may be determined based on the line order of the MIPI currently configured by the first register 110. The data processing unit 150 may directly or through the second register 120 maintain the pull-up resistor 140 corresponding to the disabled MIPI line enabled to avoid a fault such as power leakage caused by hanging of a pad of the MIPI line not connected to the host device 200 in the slave device 100, and disable the pull-up resistor 140 corresponding to the enabled MIPI line to enable the slave device 100 and the host device 200 to communicate based on the enabled MIPI line.
The plurality of receiving units 130 are respectively disposed on each MIPI line of the slave device 100, and can receive and output an initialization instruction transmitted by the host device 200.
When the host device 200 transmits the initialization instruction in the LP mode, the receiving unit 130 may include an LP receiving unit (as indicated by reference 131 of fig. 3); when the host device 200 transmits the initialization instruction in the HS mode, the reception unit 130 may include an HS reception unit (as indicated by reference numeral 132 of fig. 4).
The plurality of receiving units 130 may enable all MIPI lines based on the first value. The plurality of receiving units 130 may also enable a corresponding MIPI line, which may be an enabled MIPI line determined according to the order of the MIPI currently configured by the first register 110, based on the second value.
In a specific implementation, the data processing unit 150 may enable one or more receiving units 130 directly or through the second register 120, thereby enabling the corresponding MIPI line.
A plurality of pull-up resistors 140 may correspond to the respective MIPI lines.
Pull-up resistors 140 corresponding to all MIPI lines, respectively, may be enabled based on the first value.
In a specific implementation, when the second register 120 is set to the first value, the data processing unit 150 may enable the pull-up resistors 140 corresponding to all MIPI lines, respectively, directly or through the second register 120.
Pull-up resistors 140 corresponding to the associated MIPI line may also be enabled and disabled based on the second value.
In a specific implementation, when the second register 120 is set to the second value, the data processing unit 150 determines the non-enabled MIPI line and the enabled MIPI line based on the line sequence of the MIPI currently configured by the first register 110, where the data processing unit 150 may directly or through the second register 120 keep the pull-up resistor 140 corresponding to the non-enabled MIPI line enabled to avoid leakage caused by hanging of a pad of the MIPI line not connected to the host device 200 in the slave device 100, and de-enable the pull-up resistor 140 corresponding to the enabled MIPI line to enable the slave device 100 and the host device 200 to communicate based on the enabled MIPI line.
In an embodiment of the present invention, enabling pull-up resistor 140 includes connecting pad 160 of slave device 100 to a high level.
The data processing unit 150 may receive the initialization instruction transmitted by the receiving unit 130; if the initialization instruction includes the line order of the MIPI of the host device 200, the line order of the MIPI of the host device 200 is written into the first register 110.
The data processing unit 150 may send an instruction to the first register 110, and the first register 110 may receive and obtain the order of MIPIs based on the instruction, and then write the received order of MIPIs therein as the order of MIPIs of the slave device 100.
The data processing unit 150 may also send an instruction to the second register 120, and the second register 120 may receive and configure the second register 120 (e.g., its flag bit) to the first value or the second value based on the instruction.
Fig. 3 is a schematic diagram of another slave device 300 according to an embodiment of the present invention, where the slave device 300 may communicate with the host device 200 through one or more MIPI lines D0, D1, and the communication mode is LP mode.
Fig. 3 differs from fig. 1 in that the receiving unit 130 includes an LP receiving unit 131 and further includes an LP output logic unit 170.
The LP receiving unit 131 may receive and output an initialization instruction transmitted by the host device 200 through the LP mode on one MIPI line and output a high level on the remaining MIPI lines; wherein the initialization instruction includes or does not include the line order information of the MIPI of the host device 200.
The LP output logic unit 170 may be configured as an and logic based on the first value, one input terminal of which receives the initialization command output by the LP receiving unit 131, and the remaining input terminals of which receive the high level output by the LP receiving unit 131, and performs an and logic calculation on data at each input terminal to output the initialization command.
The data processing unit 150 may receive the initialization instruction output by the LP output logic unit 170.
If the received initialization instruction includes a second thread order of the MIPI of the host device 200, writing the second thread to the first register 110, setting the second register 120 to a second value, and configuring the thread order of the MIPI of the slave device 100 based on the second value and the second thread order.
Setting the second register 120 to a second value if the received initialization instruction does not include the line order information of the MIPI of the host device 200; and configuring a line order of the MIPI of the slave device 100 based on the second value and the first line order.
The LP output logic unit 170 may also deconfigure its and logic based on the second value so that data subsequently transmitted by the host device 200 in the LP mode may be output directly through the LP output logic unit 170 to the data processing unit 150.
Fig. 4 is a schematic diagram of a slave device 400 according to another embodiment of the present invention, where the slave device 400 may communicate with the host device 200 through one or more MIPI lines D0, D1, and the communication mode is an HS mode.
Fig. 4 differs from fig. 1 in that the reception unit 130 includes an HS reception unit 132 and further includes an HS enable control unit 180.
The HS receiving unit 132 may receive an initialization instruction transmitted by the host apparatus 200 through the HS mode.
The HS enable control unit 180 may detect the HS enable sequence in the initialization instruction to determine the line order used by the host device 200; then, a release instruction of the release of the enable is sent to the pull-up resistor 140 corresponding to the MIPI line on which the HS enable sequence is located, so that the slave device 400 and the host device 200 can communicate based on the MIPI line on which the HS enable sequence is located, and thus the data processing unit 150 can receive the initialization instruction sent by the host device 200 through the HS receiving unit 132.
After receiving the initialization command, subsequent communication between the slave device 400 and the host device 200 may be based not on the HS mode but on the LP mode, that is, data transmitted by the host device 200 in the LP mode is output to the data processing unit 150 via the LP receiving unit and directly through the LP output logic unit, and therefore, an enable recovery command may be transmitted to the pull-up resistor 140 corresponding to the MIPI line where the HS enable sequence is located after the initialization command is transmitted.
In the embodiment shown in fig. 4, since the initialization instruction does not include the line order information of the MIPI of the host device 200, the second register 120 may be set to the second value, and the line order of the MIPI of the slave device 100 may be configured based on the second value and the first line order, so that the enabled MIPI line outputs data, which is subsequently transmitted by the host device 200 in the LP mode, directly to the data processing unit 150 through the LP receiving unit 131.
Fig. 5 is a flowchart of a method 500 for configuring MIPI endianness of a slave device in an embodiment of the present invention; fig. 6 is a flowchart of another method 600 for configuring MIPI endianness of a slave device in an embodiment of the present invention.
Both methods 500, 600 comprise the steps of:
step a, writing a first sequence of MIPI of preset slave equipment into a first register;
step b, setting a second register as a first value, and enabling all MIPI lines of the slave equipment and enabling pull-up resistors corresponding to all MIPI lines respectively based on the first value;
and step c, receiving an initialization instruction sent by the host equipment.
In the execution of step a, the slave device has a preset MIPI sequence (i.e. a first sequence); the slave device may include a first register that may store a MIPI thread order of the slave device. The MIPI line order may include the number of MIPI lines and the arrangement order thereof.
Setting a second register to a first value during the execution of step b; the slave device may include a second register that may store one or more bits of data.
Specifically, the value of the second register may be set to a first value or a second value, where the first value is one of 0 or 1 and the second value is the other of 0 or 1.
When the value of the second register is set to the first value, the slave device does not know which MIPI lines the host device will send the initialization instruction from, so that all MIPI lines of the slave device can be enabled to ensure that the slave device can receive the initialization instruction of the host device, and pull-up resistors respectively corresponding to all MIPI lines can be enabled to avoid faults such as power leakage and the like caused by hanging of pads of MIPI lines which are not connected with the host device in the slave device.
When the value of the second register is set to be a second value, the line order of the MIPI of the slave equipment can be configured; furthermore, the disabled MIPI line and the enabled MIPI line may be determined based on the MIPI line sequence (which is the line sequence currently configured by the first register) configured by the slave device, the pull-up resistor corresponding to the disabled MIPI line is kept enabled to avoid a fault such as leakage caused by hanging of a pad of the MIPI line not connected to the host device in the slave device, and the pull-up resistor corresponding to the enabled MIPI line is disabled to enable the slave device and the host device to communicate based on the enabled MIPI line.
In the execution of step c, an initialization instruction sent by the host device is received.
Specifically, the host device may transmit the initialization instruction through the LP mode or the HS mode.
Before the host device and the slave device communicate, whether the MIPI sequences of the host device and the slave device are consistent or not can be manually judged in advance through hardware information of the host device and the slave device. When the linear order of the MIPI of the host device and the slave device is judged to be inconsistent manually, the initialization instruction must include the linear order of the MIPI of the host device, and the host device needs to be selected manually to generate the initialization instruction to the slave device through the LP mode. When the line sequence of the MIPI of the host equipment and the MIPI of the slave equipment are judged to be consistent manually, the line sequence of the MIPI of the host equipment does not need to be included in the initialization instruction, and the host equipment is manually selected to generate the initialization instruction to the slave equipment through the HS mode or the LP mode.
In some embodiments, the slave device may perform step d based on the determination result, as shown in fig. 5.
Specifically, if the judgment result is that the initialization instruction includes the second thread order of the MIPI of the host device, the second thread order is written into the first register, the second register is set to the second value, and the thread order of the MIPI of the slave device is configured based on the second value and the second thread order.
For example, when the second register is set to the second value, the non-enabled MIPI line and the enabled MIPI line are determined according to the second order, the pull-up resistor corresponding to the non-enabled MIPI line is kept enabled, and the pull-up resistor corresponding to the enabled MIPI line is disabled.
In a specific implementation, if the second line order is included in the initialization command as a result of the determination, the host device may send the initialization command in the LP mode, and may include specific execution of the following steps.
In the execution of step a, the LP output logic unit in the slave device may be configured as and logic based on the first value.
In the execution of step c, the LP receiving unit in the slave device may receive and output an initialization instruction transmitted by the host device through the LP mode on one MIPI line, and output a high level on the remaining MIPI lines.
In the step d, the value of the second register is set to a second value, the non-enabled MIPI line and the enabled MIPI line may be determined based on the second thread currently configured by the first register, and the pull-up resistor corresponding to the non-enabled MIPI line is kept enabled. Optionally, the pull-up resistor corresponding to the enabled MIPI line is disabled.
In the step d, the value of the second register is set to a second value, one input end of the LP output logic unit may receive the initialization instruction output by the LP receiving unit, the other input ends may receive the high level output by the LP receiving unit, and perform an and logic calculation on data at each input end to output the initialization instruction, and the data processing unit in the slave device receives the initialization instruction output by the LP output logic unit to obtain a second line sequence, and writes the second line sequence into the first register.
After step d is performed, the and logic of the LP output logic unit may be de-configured based on the second value, so that data subsequently transmitted by the host device in the LP mode may be directly output to the data processing unit through the LP output logic unit.
In other embodiments, the slave device may perform step e based on the determination result, as shown in fig. 6.
Specifically, if the judgment result is that the initialization instruction does not include the second line sequence of the MIPI of the host device, the second register is set to the second value; and configuring the line order of the MIPI of the slave device based on the second value and the first line order.
For example, when the second register is set to the second value, the non-enabled MIPI line and the enabled MIPI line are determined according to the first sequence, the pull-up resistor corresponding to the non-enabled MIPI line is kept enabled, and the pull-up resistor corresponding to the enabled MIPI line is disabled.
In a specific implementation, if the determination result is that the second line order is not included in the initialization instruction, the host device may send the initialization instruction in the LP mode, and may include specific execution of the following steps.
In the execution of step a, the LP output logic unit in the slave device may be configured as and logic based on the first value.
In the execution of step c, the LP receiving unit in the slave device may receive and output an initialization instruction transmitted by the host device through the LP mode on one MIPI line, and output a high level on the remaining MIPI lines.
In the execution of step e, the value of the second register is set to a second value, the non-enabled MIPI line and the enabled MIPI line may be determined based on the first thread currently configured by the first register, and the pull-up resistor corresponding to the non-enabled MIPI line is kept enabled, so as to avoid faults such as leakage caused by hanging of a pad of the MIPI line that is not connected with the host in the slave device. Optionally, a pull-up resistor corresponding to the enabled MIPI line is disabled, so that the slave device and the host device can communicate based on the enabled MIPI line.
In the step e, the value of the second register is set to a second value, one input end of the LP output logic unit may receive the initialization command output by the LP receiving unit, the other input ends may receive the high level output by the LP receiving unit, and perform an and logic calculation on data at each input end to output the initialization command, and the data processing unit in the slave device receives the initialization command output by the LP output logic unit.
After step e is performed, the and logic of the LP output logic unit may be de-configured based on the second value, so that data subsequently transmitted by the host device in the LP mode may be directly output to the data processing unit through the LP output logic unit.
In a specific implementation, if the determination result is that the second line order is not included in the initialization instruction, the host device may further include an initialization instruction sent in the HS mode, and may include specific execution of the following steps.
In the step c, the host device may send an HS enable sequence first, and an HS enable control unit in the slave device may detect the HS enable sequence, so that a pull-up resistor corresponding to an MIPI line where the HS enable sequence is located is disabled to receive an initialization instruction; the HS enable control unit may also control whether the HS reception unit receives the initialization instruction based on the detected HS enable sequence; the HS receiving unit in the slave device may receive and output an initialization instruction transmitted by the host device through the HS mode.
For example, the HS receiving unit receives and outputs an initialization instruction to the data processing unit in the slave device, wherein the initialization instruction includes a packet in HS format.
In the execution of step e, the data processing unit may process the initialization instruction to obtain a processed initialization instruction.
In the step e, since the subsequent communication between the host device and the slave device after receiving the initialization command may be based not on the HS mode but on the LP mode, the pull-up resistor corresponding to the MIPI line on which the HS enable sequence is located may be enabled.
In the execution of step e, the non-enabled MIPI line and the enabled MIPI line may be determined according to the line sequence (i.e. the first line sequence) currently configured by the first register, and the pull-up resistor corresponding to the enabled MIPI line is disabled.
In the execution of step e, the pull-up resistor corresponding to the non-enabled MIPI line can be kept enabled to avoid faults such as leakage caused by hanging of pad of the MIPI line which is not connected with the host in the slave device.
After step e is performed, the data subsequently sent by the host device in the LP mode may be output to the data processing unit via the LP receive unit and directly through the LP output logic unit.
Each method for configuring the MIPI sequence of the slave device in the embodiment of the present invention may be implemented based on the slave device described above with reference to fig. 1 to 4, and therefore, the execution of each step in the method and the relationship between them may also refer to the description about the slave device, and details are not described here again.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of configuring MIPI sequencing of a slave device, comprising:
step a, writing a first sequence of MIPI of preset slave equipment into a first register;
step b, setting a second register as a first value, and enabling all MIPI lines of the slave equipment and enabling pull-up resistors corresponding to all MIPI lines respectively based on the first value;
step c, receiving an initialization instruction sent by the host equipment;
step d, if the initialization instruction includes a second thread order of the MIPI of the host device, writing the second thread order into the first register, setting the second register to be a second value, and configuring the thread order of the MIPI of the slave device based on the second value and the second thread order.
2. The method of claim 1, further comprising: step e, if the initialization instruction does not include the line sequence information of the MIPI of the host equipment, setting the second register to be a second value; and configuring a line order of MIPI of the slave device based on the second value and the first line order.
3. The method of claim 1 or 2, wherein the sequence of the MIPI lines includes the number of MIPI lines and the arrangement order thereof.
4. The method of claim 1 or 2, wherein the first value is one of 0 or 1 and the second value is the other of 0 or 1.
5. The method according to claim 1 or 2, comprising: and keeping the pull-up resistor corresponding to the non-enabled MIPI circuit enabled and removing the pull-up resistor corresponding to the enabled MIPI circuit from the enabled MIPI circuit based on the second value and the wire sequence of the MIPI required to be configured by the slave device.
6. The method of claim 1, wherein step c comprises receiving the initialization command sent by the host device in an lp (low power) mode, wherein the initialization command comprises the second line order.
7. The method of claim 6,
the step a comprises the following steps: configuring an LP output logic unit in the slave device as AND logic based on the first value;
the step c comprises the following steps: an LP receiving unit in the slave device receives and outputs the initialization instruction on one MIPI line, and outputs a high level on the rest MIPI lines;
the step d comprises the following steps: one input end of the LP output logic unit receives the initialization command output by the LP receiving unit, the other input ends receive the high level output by the LP receiving unit, and perform and logic calculation on data at each input end to output the initialization command, and a data processing unit in the slave device receives the initialization command output by the LP output logic unit to obtain the second line order and writes the second line order into the first register.
8. The method of claim 7, comprising: and de-configuring the LP output logic based on the second value to enable the enabled MIPI line to directly output data transmitted by the host device through LP mode to the data processing unit.
9. The method of claim 2, wherein step c comprises: an HS enabling control unit in the slave device detects an HS enabling sequence transmitted by the master device, and an HS receiving unit in the slave device receives the initialization instruction transmitted by the master device through an HS (high speed) mode.
10. The method of claim 9, comprising: and when the HS enabling control unit detects the HS enabling sequence, enabling a pull-up resistor corresponding to the MIPI line where the HS enabling sequence is located to be disabled to receive the initialization instruction.
11. The method of claim 10, comprising: and enabling a pull-up resistor corresponding to the MIPI line where the HS enabling sequence is located after the initialization command is received.
12. The method of claim 2,
the step c comprises the following steps: an HS receiving unit in the slave device receives and outputs the initialization instruction to a data processing unit in the slave device; wherein the initialization instruction comprises a data packet in HS format;
step e comprises: and the data processing unit processes the initialization instruction according to the first thread to obtain a processed initialization instruction.
13. A slave device, comprising:
a first register adapted to receive a line order of MIPIs and write the received line order of MIPIs as the line order of MIPIs of the slave device into the first register;
a second register adapted to receive an instruction sent by a data processing unit and to configure the second register to a first value or a second value based on the instruction;
a plurality of receiving units, which are respectively arranged on each MIPI line of the slave equipment and are suitable for receiving and outputting an initialization instruction sent by the host equipment and enabling each MIPI line based on the first value;
a plurality of pull-up resistors respectively corresponding to the MIPI lines and adapted to be enabled based on the first value;
a data processing unit, which is suitable for receiving the initialization instruction sent by the receiving unit; and if the initialization instruction comprises the line sequence of the MIPI of the host equipment, writing the line sequence of the MIPI of the host equipment into the first register.
14. The slave device of claim 13, wherein the pull-up resistor is adapted to hold a pull-up resistor corresponding to an disabled MIPI line enabled and to disable a pull-up resistor corresponding to an enabled MIPI line based on the second value and a MIPI line order of the slave device.
15. The slave device of claim 13,
the receiving unit is an LP receiving unit and is suitable for receiving and outputting the initialization instruction sent by the host device through an LP mode on one MIPI line and outputting a high level on the rest MIPI lines, and the initialization instruction comprises the line sequence of the MIPI of the host device;
the slave device further comprises an LP output logic unit which is suitable for configuring into an AND logic based on the first value, one input end of the LP output logic unit receives the initialization instruction output by the LP receiving unit, the other input ends of the LP output logic unit receive the high level output by the LP receiving unit, and data of each input end are subjected to AND logic calculation to output the initialization instruction;
the data processing unit is adapted to receive the initialization instruction output by the LP output logic unit.
16. The slave device of claim 15, wherein the LP output logic unit is adapted to de-configure its and logic based on the second value to cause the enabled MIPI line to output data sent by the host device in LP mode directly to the data processing unit.
17. The slave device according to claim 13, wherein the receiving unit is an HS receiving unit adapted to receive the initialization instruction sent by the master device through HS mode.
18. The slave device of claim 17, further comprising:
the HS enabling control unit is suitable for detecting an HS enabling sequence in the initialization command, sending a release command of releasing the enabling to a pull-up resistor corresponding to an MIPI (mobile industry processor interface) line where the HS enabling sequence is located, and sending a recovery command of restoring the enabling to the pull-up resistor corresponding to the MIPI line where the HS enabling sequence is located after the initialization command is sent;
and the pull-up resistor corresponding to the MIPI line of the HS enabling sequence is suitable for receiving the release instruction to release the enable and receiving the recovery instruction to recover the enable.
CN202010761002.8A 2020-07-31 2020-07-31 Slave equipment and method for configuring MIPI (Mobile industry processor interface) line sequence thereof Pending CN114064554A (en)

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CN202010761002.8A CN114064554A (en) 2020-07-31 2020-07-31 Slave equipment and method for configuring MIPI (Mobile industry processor interface) line sequence thereof

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