CN112860613B

CN112860613B - Communication system

Info

Publication number: CN112860613B
Application number: CN202110367676.4A
Authority: CN
Inventors: 杜增权; 黄平
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2021-04-06
Filing date: 2021-04-06
Publication date: 2024-04-19
Anticipated expiration: 2041-04-06
Also published as: CN112860613A

Abstract

The system comprises a first component, a second component and at least one third component, wherein the second component is communicated with the first component through a first SPI line, the first component is communicated with the at least one third component through at least one second SPI line, after the second component sends a cross-chip communication starting instruction to the first component through the first SPI line, the first component establishes a connection relation between the first SPI line and the second SPI line, the second component directly performs write operation or read operation on the third component through SPI communication, and the third component directly sends target data to the second component under the condition that a read data instruction of the second component is received through SPI communication. The method and the device can shorten the transceiving communication time of the second component and the third component, can realize cross-chip direct communication with high efficiency, and are simple and convenient to operate and low in cost.

Description

Communication system

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a communications system.

Background

In a dual chip cascade application, for the requirement of the upper chip to write the same data to two cascade lower chips (e.g., to download program codes), as shown in fig. 1, the related art generally has the following steps: the upper computer firstly writes data into the lower chip/cascade main chip storage area to finish writing data into the main chip, then the cascade main chip controls communication among cascade chips, reads storage area data to write into the cascade slave chip to finish writing data into the slave chip, and aiming at the requirement that the upper computer chip reads data from the cascade slave chip, the common method of the related technology is as follows: the upper computer is communicated with the master chip, a slave chip data reading request is sent to the master chip through a first communication connection, the master chip receives the slave chip data reading request and then communicates through a second communication connection, the slave chip is ready to read data and send, the master chip communicates through a second communication connection, a reading operation is sent, slave chip data is read, master chip storage exists, and after the upper computer determines that the master chip data reading is completed, the reading operation is sent again, and slave chip data stored in the master chip is read.

In the related art, after the communication between the upper computer and the lower computer slave chip is stored through the master chip, the communication is transferred to the slave chip, 2 times of time is required, and multi-stage operation is required, so that the related art has the problems of long time consumption, low efficiency, troublesome operation and the like.

Disclosure of Invention

In view of this, the present disclosure proposes a communication system comprising a first component, a second component, and at least one third component, the first component and the second component communicating over a first serial peripheral interface, SPI, line, the first component and the at least one third component communicating over at least one second SPI line, wherein,

The second component is used for sending SPI communication information, and the SPI communication information is used for writing data into the second component and the third component or only reading data or writing data into the third component;

The first component is used for: receiving SPI communication information sent by the second component, and under the condition that the SPI communication information comprises a cross-chip communication start instruction, establishing a connection relation between the first SPI line and the second SPI line so that the second component establishes direct SPI connection with the first component and the third component;

The third component is used for: and directly receiving SPI communication information sent by the second component through the second SPI line, and sending target data under the condition that the SPI communication information comprises a data reading instruction.

In one possible implementation, the third component transmits the target data N/2 clock cycles earlier than the second component receives the target data, where N is an integer.

In one possible implementation, the SPI communication information includes an SPI clock signal and a chip select signal, and the third component is further configured to:

And when the chip selection signal is received, the first bit of the target data is sent, and the rest data bits of the target data are sent on the falling edge of the SPI clock signal from the first falling edge of the SPI clock signal.

In one possible embodiment, the second component is further configured to:

the first rising edge after the clock signal that sent the SPI communication begins to receive the target data,

The half period time of the SPI clock signal is longer than or equal to the sum of the downlink signal delay time of the SPI communication information, the target data uplink delay time and the sampling establishment time when the second component acquires the target data.

In one possible implementation, the SPI communication information includes an SPI clock signal and a chip select signal,

The third component is further configured to: transmitting the target data from a first rising edge of the SPI clock signal;

the second assembly is further configured to: the first rising edge after the clock signal that sent the SPI communication begins to receive the target data,

Wherein the time difference between the second component sending the SPI communication information and receiving the target data is one half clock period,

And when the chip selection signal is received, the first bit of the target data is sent, and the rest data bits of the target data are sent on the rising edge of the SPI clock signal from the first rising edge of the SPI clock signal.

In one possible embodiment, the second component is further configured to:

The period time of the SPI clock signal is longer than or equal to the sum of the delay time of the downlink signal of the SPI communication information from the second component to the third component, the uplink delay time of the target data from the third component to the second component and the sampling establishment time when the second component acquires the target data.

The third component is further configured to: transmitting the target data from a first falling edge of the SPI clock signal;

Wherein the time difference between the second component sending the SPI communication information and receiving the target data is one clock period,

after receiving the chip selection signal, counting the SPI clock signal, and starting from the rising edge of the seventh clock period of the SPI clock signal, sending the target data on the rising edge of the SPI clock signal.

In one possible embodiment, the first component is further configured to:

and temporarily storing the target data sent by the third component, and sending the target data on the rising edge of the next SPI clock signal receiving the target data.

In one possible embodiment, the third component is further configured to:

After receiving the chip select signal, a first bit of redundancy data is transmitted, and the remaining bits of redundancy data are transmitted from a first falling edge or rising edge to a sixth falling edge or rising edge of the SPI clock signal.

In one possible embodiment, the second component is further configured to:

The ninth rising edge after the clock signal for the SPI communication is sent begins to receive the target data,

Wherein the period time of the SPI clock signal is longer than or equal to the sum of the delay time of the downlink signal of the SPI communication information from the first component to the third component, the uplink delay time of the target data from the third component to the first component and the sampling establishment time when the second component acquires the target data,

The period time of the SPI clock signal is longer than or equal to the sum of the delay time of the downlink signal of the SPI communication information from the second component to the first component, the uplink delay time of the target data from the first component to the second component and the sampling establishment time when the second component acquires the target data.

The third component is further configured to: transmitting the target data at a rising edge of the SPI clock signal from a rising edge of a seventh clock cycle of the SPI clock signal;

the first component is further configured to: temporarily storing the target data sent by the third component, and sending the target data on the rising edge of the next SPI clock signal for receiving the target data;

The second assembly is further configured to: the ninth rising edge after the clock signal for the SPI communication is sent begins to receive the target data,

Wherein the time difference between the second component sending the SPI communication information and receiving the target data is two clock cycles,

In one possible embodiment, the third component is further configured to:

In one possible implementation, when the first SPI line and the second SPI establish a connection, the first component is further configured to:

And under the condition that the received SPI communication information comprises a cross-chip communication stop instruction, disconnecting the connection relation between the first SPI line and the second SPI line.

In a possible implementation manner, the first component includes a line change-over switch, and the first component is further configured to:

And under the condition that the SPI communication information comprises a cross-chip communication starting instruction, establishing a connection relation between the first SPI line and the second SPI line through the change-over switch.

In one possible embodiment, the first component is further configured to:

And under the condition that the received SPI communication information comprises a cross-chip communication stop instruction, disconnecting the connection relation between the first SPI line and the second SPI line through the change-over switch.

In one possible implementation, the first component, the third component includes a display, a smart phone, or a portable device, and the second component includes a host computer.

In one possible embodiment, the display includes any one of a liquid crystal display, an organic light emitting diode display, a quantum dot light emitting diode display, a mini light emitting diode display, and a micro light emitting diode display.

According to the communication system and the communication method, the second assembly can be switched from the first SPI line to the second SPI line according to the cross-chip communication starting instruction contained in the SPI communication information of the second assembly, so that the second assembly is directly connected with the first assembly and the third assembly, when the second assembly simultaneously sends the SPI communication information to the first assembly and the third assembly, the third assembly can synchronously receive the same SPI communication information sent by the second assembly with the first assembly, the broadcasting purpose is achieved, and when the second assembly needs to read the data of the third assembly, the second assembly can send the reading instruction to the third assembly more quickly, and the third assembly can also respond to the reading instruction to return the data to the second assembly more quickly.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of writing data to a cascaded chip in the related art.

Fig. 2a shows a block diagram of a communication system according to an embodiment of the present disclosure.

Fig. 2b shows a block diagram of a communication system according to an embodiment of the present disclosure.

FIG. 3 illustrates a schematic diagram of write data transfer according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Referring to fig. 2a, fig. 2a shows a block diagram of a communication system according to an embodiment of the present disclosure.

As shown in fig. 2a, the system comprises a first component 10, a second component 20 and at least one third component 30, the first component 10 and the second component 20 communicate via a first serial peripheral interface, SPI, line, the first component 10 and the at least one third component 30 communicate via at least one second SPI line, wherein,

The second component 20 is configured to send SPI communication information, where the SPI communication information is used to write data to the second component 20 and the third component 30 or read data or write data to the third component 30 only;

the first assembly 10 is for: receiving SPI communication information sent by the second component 20, and establishing a connection relationship between the first SPI line and the second SPI line when the SPI communication information includes a cross-chip communication start instruction, so that the second component 20 establishes direct SPI connection with the first component 10 and the third component 30;

The third component 30 is configured to: and directly receiving SPI communication information sent by the second component 20 through the second SPI line, and sending target data under the condition that the SPI communication information comprises a data reading instruction.

According to the communication system disclosed by the embodiment of the disclosure, the second component 20 can be switched from the first SPI line to the second SPI line according to the cross-chip communication starting instruction contained in the SPI communication information of the second component 20, so that the second component 20 is directly connected with the first component 10 and the third component 30, when the second component 20 simultaneously transmits the SPI communication information to the first component 10 and the third component 30, the third component 30 can synchronously receive the same SPI communication information transmitted by the second component 20 with the first component 10, the broadcasting purpose is achieved, and when the second component 20 is to read the data of the third component 30, the second component 20 can more quickly transmit the reading instruction to the third component 30, and the third component 30 can also more quickly respond to the reading instruction to return the data to the second component 20.

Through the above system, the embodiments of the present disclosure can implement a first mode, which is a mode in which the second component 20 writes data to the first component 10 and the third component 30 simultaneously, and in this first mode, the data written to the first component 10 and the third component 30 by the second component 20 are the same; in addition, the second module 20 may read and write data only to the third module 30, that is, the second mode in which the second module 20 does not read and write data to and from the first module 10, and the first module 10 is not visible to data in this mode (data read and written only to and from the third module 30). In one example, a mode indication flag bit may be set in the SPI communication information (e.g., 1 represents a first mode, and 0 represents a second mode) to distinguish between the two modes, where in the second mode, communication between the first component 10 and the second component 20 may be cut off, e.g., after the first component sends a chip communication indication to the second component through a first SPI line, the second component establishes a connection relationship between the first SPI line and the second SPI line, cuts off communication between the first component 10 and the second component 20, and the first component 10 only serves as a node for communicating the SPI communication information, so that the second component directly performs a write operation or a read operation on the third component through the SPI communication, and the third component directly sends target data to the second component in a case that a read command of the second component is received through the SPI communication.

The embodiments of the present disclosure are not limited to specific implementation manners of communicating by using the SPI, and those skilled in the art may implement the embodiments of the present disclosure without limiting specific implementation manners of the SPI communication protocol, and the SPI communication referred to in the present disclosure may be based on four-wire SPI (including, for example, a clock signal line CLK, a chip select line CS, a master input and slave output MISO, and a master output and slave input MOSI), or may include three-wire SPI (including, for example, a clock signal line CLK, a chip select line CS, a master input and slave output MISO, or a master output and slave input MOSI, where a data line may be MISO or MOSI), and of course, three-wire SPI may also include a clock signal line CLK, a master input and slave output MISO, and a master output and slave input MOSI.

Of course, the above description of SPI signal lines is exemplary, and in other embodiments, one of ordinary skill in the art may set as desired.

In one example, the SPI communication information can include SPI clock signal CLK, SPI chip select signal CS, and SPI data MOSI.

It should be noted that, the specific implementation manner of the first component 10, the second component 20, and the third component 30 in the embodiments of the present disclosure is not limited, the first component 10 may be referred to as an upper computer, the second component 20 and the plurality of third components 30 are in a master-slave relationship, where the second component 20 may be a master, and the third component 30 may be a slave.

In one example, the components include, but are not limited to, a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller in an electronic device having the functionality to execute instructions, and may be implemented in any suitable manner, for example, by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic controllers, and embedded microcontrollers. In one example, the component may also be a Terminal or a server, where the Terminal is also called a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc., which is a device that provides voice and/or data connectivity to a User, such as a handheld device, an in-vehicle device, etc., with wireless connection capability. Currently, some examples of terminals are: a mobile phone, a tablet, a notebook, a palm, a mobile internet device (Mobile Internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an augmented reality (Augmentedreality, AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in unmanned (SELFDRIVING), a wireless terminal in teleoperation (Remote medical Surgery), a wireless terminal in smart grid (SMART GRID), a wireless terminal in transportation security (Transportation Safety), a wireless terminal in smart city (SMART CITY), a wireless terminal in smart home, a wireless terminal in the internet of vehicles, and the like.

In one example, the first component 10, the second component 20, and the third component 30 are configured to support SPI communications, where the second component 20 hosts multiple SPI units may be configured to correspond to the first component 10 and the multiple third components 30, respectively, and illustratively, a first SPI line between the first component 10 and the second component 20 may correspond to the first SPI unit, and a second SPI line between the second component 20 and the third component 30 may correspond to the second SPI unit.

The embodiments of the present disclosure are not limited to a specific implementation of communication using SPI, and those skilled in the art may implement the embodiments according to the related art.

In one example, the form of the off-chip communication start indication may be agreed in the SPI communication protocol in advance, and when the second component 20 receives the off-chip communication start indication, a connection relationship between the first SPI line and the second SPI line may be established, so as to establish direct connection of the first component 10, each third component 30, and the second component 20.

Of course, the embodiment of the disclosure is not limited to a specific protocol implementation, and those skilled in the art may implement the protocol implementation according to needs and practical situations.

Referring to fig. 2b, fig. 2b shows a block diagram of a communication system according to an embodiment of the present disclosure.

In a possible implementation, as shown in fig. 2b, the first component 10 may include a line switch 130, where in the SPI communication information includes a cross-chip communication start instruction, establishing a connection between the first SPI line and the second SPI line includes:

And when the inter-chip communication start instruction is included in the SPI communication information, establishing a connection relationship between the first SPI line and the second SPI line through the line change-over switch 130.

In one example, as shown in FIG. 2b, first component 10 includes a first SPI unit 110, a second SPI unit 120, second component 20 includes a third SPI unit 210, third component 30 includes a fourth SPI unit 310, first SPI unit 110 establishes an SPI connection with third SPI unit 210 to form a first SPI line, and second SPI unit establishes an SPI connection with fourth SPI unit to form a second SPI line.

In one example, upon receipt of a cross-chip communication initiation indication, line switch 130 is enabled to connect corresponding ports (e.g., CLK/CS/MISO) of the first SPI line, the second SPI line.

In one possible implementation, when the first SPI line and the second SPI establish a connection, the first component 10 can also be used to:

In one example, when the second component 20 does not need to perform broadcast communication or does not need to read data or other conditions of the third component 30, the second component 20 may send a cross-chip communication stop instruction to the first component 10 through the SPI, and when the first component 10 receives the cross-chip communication stop instruction, the connection relationship between the first SPI line and the second SPI line is disconnected, so that the direct SPI connection between the second component 20 and the third component 30 is disconnected, so that the broadcast communication system exits the unified operation mode, in which case the first component 10 and the second component 20 may directly perform SPI communication through the first SPI line, and the first component 10 and the third component 30 may directly perform SPI communication through the second SPI line, but no direct SPI communication between the second component 20 and the third component 30 may be performed.

In one example, the form of the off-chip communication stop indication may be agreed in the SPI communication protocol in advance, and when the off-chip communication stop indication is received by the second component 20, the connection relationship between the first SPI line and the second SPI line is defined to be disconnected, so that the direct connection between the first component 10 and each third component 30 is disconnected.

In one possible embodiment, the first assembly 10 may also be used to:

in the event that a cross-chip communication stop indication is included in the received SPI communication, second component 20 is switched to the first SPI line by way of line switch 130.

In one example, upon receipt of a cross-chip communication stop indication, line switch 130 is enabled to disconnect the first SPI line from the second SPI line.

Of course, fig. 2b and the above description illustrate an example of the line switch 130, in other examples, the line switch 130 may also be configured to cut off the operation of the second SPI unit 120 when the system is operating in the second mode, for example, the connection PAD of the second SPI unit 120 to the first SPI unit 110 may be directly connected to the third SPI unit 210 through the line switch 130, such that the second SPI unit 120 does not receive the information of the first SPI unit, and the first SPI unit 110 sends the SPI communication information to the fourth SPI unit 310 through the connection PAD of the second SPI unit 120 directly through the third SPI unit 210.

The specific type of the switch according to the embodiments of the present disclosure is not limited, and those skilled in the art may select the switch according to needs and practical situations, and in one example, the switch may be implemented based on a switching transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), or the like.

An exemplary description of an implementation in which the second component 20 simultaneously transmits the same data to the first component 10 and the third component 30 is provided below.

Referring to fig. 3, fig. 3 shows a schematic diagram of write data transfer according to an embodiment of the present disclosure.

In one example, when the second component 20 needs to perform broadcast communication, the second component 20 may send a cross-chip communication start instruction to the first component 10 through the SPI, so that the second component 20 establishes a connection relationship between the first SPI line and the second SPI line, and the broadcast communication system thereby enters a unified operation mode, in which the second component 20 may perform write operation on the first component 10 and each third component 30, that is, send the same SPI communication information.

In one example, as shown in fig. 3, in the unified operation mode, the SPI communication information (a) sent by the second component 20 includes a chip select signal CS, a clock signal CLK, and SPI broadcast data MOSI, where the exemplary SPI broadcast data MOSI is 01101100, and since the first component 10, the second component 20, and the third component 30 are directly connected, the SPI communication information sent by the second component 20 may be received by the first component 10 and the third component 30, where there is a delay between the SPI communication information (B) received by the first component 10 and the SPI communication information (a), and the delay time is a transmission delay time from the first component 10 to the second component 20; the SPI communication (C) and the SPI communication (a) received by the third component 30 are delayed by the transmission delay time from the first component 10 to the third component 30.

In one example, because the second component 20 writes the same data to the first component 10 and the third component 30, the first component 10 and the second component 20 and the first component 10 and the third component 30 are the same SPI communication protocol; so the SPI signals of the first component 10 and the second component 20 are directly connected to the SPI communication ports of the first component 10 and the third component 30 (the first SPI communication lines of the first component 10 and the second component 20 are cut off), the SPI signals of the second component 20 are sent to the first component 10 and the third component 30, the first component 10 and the third component 30 can both receive the same SPI signals and data sent by the second component 20, and one SPI write communication completes the write operation of the same data of at least 2 lower computer cascade chips (the first component 10 and at least one third component 30). The SPI signal received by the third component 30 is delayed by several tens of ns from the SPI signal received by the first component 10, because the SPI signal received by the third component 30 passes through the 2-stage connection PAD (the PAD output passing out of the first component 10, the PAD input passing into the third component 30). However, since the clock signal CLK and the data signal MOSI in the SPI signal have the same delay, the third component 30 is not affected to receive the correct data.

Referring to table 1, table 1 shows a time-consuming schematic of transmitting data using the related art and transmitting data using embodiments of the present disclosure.

TABLE 1

As can be seen from table 1, the embodiments of the present disclosure have significantly reduced time when writing data to the slave machine, compared to the related art.

Through the system, the embodiment of the disclosure can realize the instant broadcast communication between the second component and the first component and between the second component and each third component, and the second component can quickly write the same data into the first component and the third component, and has simple operation and lower cost.

An exemplary description of an implementation of the second component 20 to read the data of the third component 30 is provided below.

In one example, when the second component 20 needs to read data of any one of the third components 30, the second component 20 may send a cross-chip communication start instruction to the first component 10 through the SPI, so that the second component 20 establishes a connection relationship between the first SPI line and the second SPI line, and the communication system thereby enters a unified operation mode, in which the second component 20 may read data in each of the third components 30 simultaneously and quickly.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating read data transfer according to an embodiment of the present disclosure.

In one possible implementation, as shown in fig. 4, the SPI communication information may include an SPI clock signal and a chip select signal, and the third component 30 may be further configured to:

In one possible embodiment, the second assembly 20 is further configured to:

Wherein the half period time of the SPI clock signal is greater than or equal to the sum of the downlink signal delay time of the SPI communication information, the target data uplink delay time, and the sampling setup time when the second component 20 acquires the target data.

Because the first SPI line is connected to the second SPI line, in this case, the SPI communication information of the second component 20 can be sent to the first component 10 and the third component 30 at the same time, and the data of the third component 30 can also be sent to the second component 20 and the first component 10, which increases the communication speed between the second component 20 and the third component 30 compared to the two-stage transmission (the data of the second component 20 and the third component 30 are buffered by the first component 10) in the related art.

In one example, as shown in fig. 4, the downlink signal delay time of the SPI communication information includes the delay of the SPI communication information (CS-A, CLK-A, MISO-a, etc.) transmitted by the second component 20 to the first component 10 (the delay of the third SPI unit 210 to the first SPI unit 110), the delay between the SPI units of the first component 10 (the delay of the first SPI unit 110 to the second SPI unit 120), and the delay of the first component 20 to the third component 30 (the delay of the second SPI unit 120 to the fourth SPI unit 310), the target data uplink delay time includes the delay of the third component 30 to the first component 10 (the delay of the fourth SPI unit 310 to the second SPI unit 120), the delay between the SPI units of the first component 10 (the delay of the second SPI unit 120 to the first SPI unit 110), and the delay between the first component 10 to the second component 20 (the delay of the first SPI unit 120 to the third SPI unit 210).

In one example, the delay between the SPI units of the first component 10 (the delay between the second SPI unit 120 and the first SPI unit 110) and the sampling setup time when the second component 20 acquires the target data are negligible, the delay of the SPI communication information (CS-A, CLK-A, MISO-a, etc.) sent by the second component 20 sent to the first component 10 and the delay of the first component 20 to the third component 30 are assumed to be 50ns, and in this case, the third component 30 needs to send the target data satisfying T/2> =100 ns, i.e., T is greater than or equal to 200ns, and the corresponding frequency freq is less than or equal to 5MHz.

When the period of the SPI clock signal is longer than or equal to the sum of the downlink signal delay time of the SPI communication information, the uplink delay time of the target datA, and the sampling setup time when the second component 20 acquires the target datA, as shown in fig. 4, the third component 30 sends the first bit (i.e., the highest bit of bit 7=1) of the target datA (MISO-C is illustrated as 10101100) when receiving the chip select signal (CS-C), starts from the first falling edge of the SPI clock signal (CLK-C), and sends the remaining datA bits (bit 6 to bit0, i.e., 0101100) of the target datA on the falling edge of the SPI clock signal, so that the first rising edge of the second component 20 after sending the SPI communication information clock signal starts to receive the target datA, as shown in fig. 4, and the second component 20 correctly receives the target datA (o-A is illustrated as 10101100).

In the above description, the schemes corresponding to the mode 0 and the mode 2 in SPI communication are described, and in the related art, the slaves in the mode 0 and the mode 2 transmit data on the falling edge, and the upper computer receives data on the rising edge.

Other modes are described below, for example, for mode 1 and mode 3 in SPI communications, the slave sends data on the rising edge and the upper receives data on the falling edge.

The third assembly 30 is further configured to: transmitting the target data from a first rising edge of the SPI clock signal;

The second assembly 20 is also for: the first rising edge after the clock signal that sent the SPI communication begins to receive the target data,

Wherein the time difference between the second component 20 sending the SPI communication information and receiving the target data is one half clock period,

It should be noted that, for any mode of SPI communication, as long as it is ensured that there is a time difference of one half clock period between the sending target data by the third component and the receiving target data by the second component, that is, the third component sends the target data one half clock period in advance, the upper computer may correctly read the data sent by the third component, and the communication system according to the embodiment of the present disclosure may achieve an improvement in the reading speed.

Referring to fig. 5, fig. 5 shows a schematic diagram of read data transmission according to an embodiment of the present disclosure.

In one possible implementation, the SPI communication information includes an SPI clock signal CLK and a chip select signal CS, and the third component 30 is further configured to:

In one possible embodiment, the second assembly 20 may also be used to:

The period time of the SPI clock signal is greater than or equal to the sum of the delay time of the downlink signal of the SPI communication information from the second component 20 to the third component 30, the delay time of the uplink signal of the target data from the third component 30 to the second component 20, and the sampling setup time when the second component 20 acquires the target data.

In one example, the delay between the SPI units of the first component 10 (the delay between the second SPI unit 120 and the first SPI unit 110) and the sampling setup time when the second component 20 acquires the target data are negligible, the delay of the SPI communication information (CS-A, CLK-A, MISO-a, etc.) sent by the second component 20 sent to the first component 10 and the delay of the first component 20 to the third component 30 are assumed to be 50ns, and in this case, the delay T of the third component 30 sent the target data is greater than or equal to 100ns, and the time from the sending of the read request to the acquisition of the target data by the second component 20 is less than or equal to 10MHz, which is the corresponding frequency freq, compared with the former method, the communication rate is improved.

The disclosed embodiments, when satisfying the conditions that the period of the SPI clock signal is longer than or equal to the sum of the downstream signal delay time of the SPI communication information from the second component 20 to the third component 30, the upstream delay time of the target data from the third component 30 to the second component 20, and the sampling setup time when the second component 20 acquires the target data, as shown in fig. 5, when the third component 30 receives the chip select signal (CS-C), transmits the first bit (i.e., the highest bit 7=1) of the target data (MISO-C) which is exemplified by 10101100, and transmits the remaining data bits (misbit 6 to bit0, i.e., 0101100) of the target data (i-a) which is exemplified by 10101100) from the first falling edge of the SPI clock signal (CLK-C) on the falling edge of the SPI clock signal. The third component of the disclosed embodiments transmits the target data one half clock period (CLK) in advance (generally, transmits the data on a falling edge), the lower limit of the period can be reduced, thereby increasing the upper limit of the communication rate, and the second component 20 can start to receive the target data on the first rising edge after the clock signal of the SPI communication information is transmitted, so as to achieve fast and accurate reception of the data.

It should be noted that, for any mode of SPI communication, as long as it is ensured that there is a time difference of one clock cycle between the sending target data by the third component and the receiving target data by the second component, that is, the third component sends the target data 1 clock cycle in advance, the upper computer may correctly read the data sent by the third component, and the communication system according to the embodiment of the disclosure may achieve improvement of the reading speed.

Referring to fig. 6, fig. 6 shows a schematic diagram of read data transfer according to an embodiment of the present disclosure.

In one possible implementation, as shown in fig. 6, the SPI communication information includes an SPI clock signal and a chip select signal, and the third component 30 may be further configured to:

In one possible embodiment, as shown in fig. 6, the first assembly 10 is further configured to:

The target data sent by the third component 30 is temporarily stored, and the target data is sent on the rising edge of the next SPI clock signal in which the target data is received.

In one example, the first component 10 may be provided with a register module including a plurality of registers to implement temporary storage of the received target data, and of course, the specific implementation of the register module is not limited by the embodiment of the present disclosure.

According to the embodiment of the disclosure, the first component 10 temporarily stores the received target data, so that the SPI communication rate can be further improved, and the SPI reading operation rate is improved.

In one possible embodiment, as shown in fig. 6, the third component 30 is further configured to:

After receiving the chip select signal, a first bit of redundant data (DUMMY Byte) is transmitted, and remaining bits of the redundant data are transmitted from a first falling or rising edge to a sixth falling or rising edge of the SPI clock signal.

It should be noted that when the first component receives the redundant data, it performs a discard process, i.e., discards the received first byte of data.

In one possible embodiment, as shown in fig. 6, the second assembly 20 may also be used to:

Wherein the period time of the SPI clock signal is longer than or equal to the sum of the delay time of the downlink signal of the SPI communication information from the first component 10 to the third component 30, the uplink delay time of the target data from the third component 30 to the first component 10 and the sampling establishment time when the second component 20 acquires the target data,

The period time of the SPI clock signal is greater than or equal to the sum of the delay time of the downlink signal of the SPI communication information from the second component 20 to the first component 10, the delay time of the uplink signal of the target data from the first component 10 to the second component 20, and the sampling setup time when the second component 20 acquires the target data.

For the second component 20, the third component 30 transmits data 2 CLK cycles earlier (including transmitting data on the rising edge and transmitting data half (0.5) cycles earlier than the default, and transmitting data 1.5 cycles earlier in total, transmitting data 2 cycles earlier), the first Byte data cannot be transmitted correctly, so the first Byte data is DUMMY Byte. The SPI of the third component 30 starts to send the highest data bit 7 (the subsequent bits are sent in sequence) of the first valid Byte at the 7th (7 th) CLK rising edge of the first Byte, the SPI of the first component 10 latches (DFF) and sends out the bit 7 (the subsequent bits are sent in sequence) at the 8th (8 th) CLK rising edge of the first Byte, and the SPI of the upper computer adopts the bit 7 (the subsequent bits are received in sequence) at the 1st (1 st) CLK rising edge of the second Byte, so that the data is received correctly.

In one example, the first byte of data received by the second component 20 is redundant data, the second component 20 discards the first byte received and begins receiving valid data on the rising edge of the first CLK beginning with the second byte (i.e., the ninth rising edge after the clock signal for the SPI communication is sent).

In an example, the delay between the SPI units of the first component 10 (the delay between the second SPI unit 120 and the first SPI unit 110) and the sampling setup time when the second component 20 acquires the target data are negligible, the delay when the SPI communication information (CS-A, CLK-A, MISO-a, etc.) sent by the second component 20 is sent to the first component 10 and the delay when the delay between the first component 20 and the third component 30 are assumed to be 50ns, and in this case, since the embodiment of the disclosure temporarily stores the target data transmitted by the third component 30 through the first component 10, the third component 30 only needs to send the target data in a delay of 50ns through a pipe (pipeline) data transmission manner, that is, the third component sends the target data in a period of T being greater than or equal to 50ns, and the corresponding frequency freq is less than or equal to 20MHz, so that the communication rate between the third component 30 and the second component 20 is greatly improved.

It should be noted that, in the drawings of the various embodiments of the present disclosure, in order to show that the second component 20 has enough hold time when sampling MISO-C, and in order to represent the delay between the respective clock signals, the delay between the respective data signals MISO, the embodiments of the present disclosure use a manner of alignment between signals when drawing the drawings, and the transmission time of the data is not strictly aligned with the clock signal CLK, which should not be construed as limiting the present disclosure.

The presently disclosed embodiments provide for the conditions that the period of the SPI clock signal is greater than or equal to the sum of the downstream signal delay time of the SPI communication information from the first component 10 to the third component 30, the upstream delay time of the target data from the third component 30 to the first component 10, and the sampling setup time when the second component 20 acquires the target data, the period of the SPI clock signal is greater than or equal to the sum of the downstream signal delay time of the SPI communication information from the second component 20 to the first component 10, the upstream delay time of the target data from the first component 10 to the second component 20, and the sampling setup time when the second component 20 acquires the target data, as shown in fig. 6, the third component 30 is caused to transmit the first bit of redundancy data (DUMMY Byte) after receiving the chip select signal (CS-C) and transmit the remaining bits of redundancy data from the first falling edge or rising edge to the sixth falling edge or rising edge of the SPI clock signal (CLK-C), and after receiving the chip select signal, count the SPI clock signal, transmit the target data (MISO-C is exemplified as 10101100) at the rising edge of the SPI clock signal starting from the rising edge of the seventh clock cycle of the SPI clock signal, and cause the first component 10 to temporarily store the target data (data MISO-B0 received by the first component 10) transmitted by the third component 30, resulting in temporarily stored target data (MISO-B1), and the target datA is sent at the rising edge of the next SPI clock signal that receives the target datA, so that the second component 20 can start to receive the target datA at the ninth rising edge after sending the clock signal of the SPI communication information, as shown in fig. 6, the second component 20 correctly receives the target datA (MISO-A is illustrated as 10101100), which can realize accurate and rapid communication of each component of the system according to the embodiments of the present disclosure.

In one possible embodiment, the third component is further configured to:

It should be noted that, for any mode of SPI communication, as long as it is ensured that there is a time difference of two clock cycles between the sending target data by the third component and the receiving target data by the second component, that is, the third component sends the target data 2 clock cycles in advance, the upper computer may correctly read the data sent by the third component, and the communication system according to the embodiment of the disclosure may achieve improvement of the reading speed.

Referring to table 2, table 2 shows a time-consuming illustration of reading data using the related art and reading data using embodiments of the present disclosure.

TABLE 2

As shown in table 2, when the scheme corresponding to fig. 6 is adopted, the second component 20 of the embodiment of the present disclosure reads data of the third component 30 in a much shorter time than the data read using the related art.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A communication system comprising a first component, a second component, and at least one third component, the first component and the second component communicating via a first serial peripheral interface, SPI, line, the first component and the at least one third component communicating via at least one second SPI line, the first component comprising a line switch, wherein,

The first component is used for: receiving SPI communication information sent by the second component, and under the condition that the SPI communication information comprises a cross-chip communication start instruction, establishing a connection relation between the first SPI line and the second SPI line through the line change-over switch so that the second component establishes direct SPI connection with the first component and the third component;

2. The system of claim 1, wherein the third component transmits the target data N/2 clock cycles earlier than the second component receives the target data, wherein N is an integer.

3. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal, the third component further operable to:

4. The system of claim 3, wherein the second component is further configured to:

Wherein the time difference between the third component sending out the target data and the second component receiving the target data is one half clock period,

5. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal,

6. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal, the third component further operable to:

7. The system of claim 6, wherein the second component is further configured to:

Wherein the time difference between the third component sending out the target data and the second component receiving the target data is one clock cycle,

8. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal,

9. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal, the third component further operable to:

10. The system of claim 9, wherein the first component is further configured to:

11. The system of claim 10, wherein the third component is further configured to:

12. The system of any one of claims 9-11, wherein the second component is further configured to:

Wherein the time difference between the third component sending out the target data and the second component receiving the target data is two clock cycles,

13. The system of claim 1, wherein the SPI communication information comprises an SPI clock signal and a chip select signal,

14. The system of claim 13, wherein the third component is further configured to:

15. The system of claim 1, wherein when the first SPI line and the second SPI line establish a connection, the first component is further operative to:

16. The system of claim 1 or 15, wherein the first component is further configured to:

17. The system of claim 1, wherein the first component, the third component, and the second component comprise a display, a smart phone, or a portable device.