CN116107790A - I2C communication exception handling method, electronic equipment, system and storage medium - Google Patents

I2C communication exception handling method, electronic equipment, system and storage medium Download PDF

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Publication number
CN116107790A
CN116107790A CN202310172134.0A CN202310172134A CN116107790A CN 116107790 A CN116107790 A CN 116107790A CN 202310172134 A CN202310172134 A CN 202310172134A CN 116107790 A CN116107790 A CN 116107790A
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slave device
bus
communication
slave
line scl
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李钜辉
叶少强
陈浩
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Jihai Microelectronics Co ltd
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Jihai Microelectronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0748—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a remote unit communicating with a single-box computer node experiencing an error/fault
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)

Abstract

The present invention relates to the field of I2C communications technologies, and in particular, to a method, an electronic device, a system, and a storage medium for processing an I2C communication exception. The method comprises the following steps: the slave device determines a clock signal period T transmitted by the master device on the clock line SCL; when the slave device determines that the I2C bus communication is abnormal, the slave device periodically pulls down the clock line SCL according to the clock signal period T to generate a first clock signal on the clock line SCL, wherein the first clock signal is used for recovering the communication on the I2C bus. In the embodiment of the invention, the communication on the I2C bus can be restored by the slave device when the I2C bus is in the abnormal communication state.

Description

I2C communication exception handling method, electronic equipment, system and storage medium
Technical Field
The present invention relates to the field of I2C communications technologies, and in particular, to a method, an electronic device, a system, and a storage medium for processing an I2C communication exception.
Background
The Inter-Integrated Circuit (I2C) bus is a synchronous serial bus in two-wire system. The I2C bus includes a Serial Data line (Serial Data, abbreviated as Data line SDA) and a Serial clock line (Serial Clock Line, abbreviated as Data line SCL). The master and slave devices connected to the I2C bus complete communication via both the data line SDA and the clock line SCL. In the actual communication process, the I2C bus sometimes has a communication abnormality problem. For example, when the slave replies ACK or replies data bit 0, the master is abnormally reset, the data line SDA is in a pulled-down state by the slave, and the clock line SCL is in a high state. At this point, the slave will wait for the master to pull down the clock line SCL to take the ACK or data bit 0 and the master will wait for the slave to release the data line SDA. The master device and the slave device wait for each other and enter a communication abnormal state. When the I2C bus enters a communication abnormal state, how to resume normal communication between the master and slave devices becomes a technical problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a processing method, electronic equipment, a system and a storage medium for I2C communication abnormality, wherein communication on an I2C bus can be restored through operation from the equipment side when the I2C bus is in a communication abnormal state.
In a first aspect, an embodiment of the present invention provides a method for processing an I2C communication exception, including:
the slave device determines a clock signal period T transmitted by the master device on the clock line SCL;
when the slave determines that the I2C bus communication is abnormal, the slave periodically pulls down the clock line SCL according to the clock signal period T to generate a first clock signal on the clock line SCL, the first clock signal being used to resume communication on the I2C bus.
Optionally, the determining, by the slave device, that the I2C bus communication is abnormal includes:
the slave device determines that I2C bus communication is abnormal when it detects that the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to an abnormality detection threshold.
Optionally, the slave device periodically pulls down the clock line SCL according to the clock signal period T to generate the first clock signal on the clock line SCL, including:
the period of the first clock signal is T, the first m period of each period T of the first clock signal is low level, and m is a preset known value.
Optionally, the method further comprises: the slave device stops control of the clock line SCL when it detects that the master device resumes sending the second clock signal on the clock line SCL.
Optionally, the slave device is provided with an anomaly detection threshold for determining that the I2C bus is abnormal in communication, and the method further includes:
and the slave equipment determines the total duration of the I2C bus communication abnormality according to the abnormality detection threshold and the duration of the first clock signal.
Optionally, the slave device is any slave device connected to the I2C bus.
Optionally, when the slave device determines that the I2C bus communication is abnormal, the slave device periodically pulls down the clock line SCL according to the clock signal period T to generate the first clock signal on the clock line SCL, including:
each slave device connected to the I2C bus has a respective anomaly detection threshold;
each slave device determines whether the I2C bus is abnormal in communication according to the abnormality detection threshold value of the slave device, and when any slave device connected to the I2C bus determines that the I2C bus is abnormal in communication, the corresponding slave device periodically pulls down the clock line SCL; or,
the slave device which does not establish communication with the master device at present determines whether the I2C bus is abnormal according to the abnormality detection threshold value of the slave device, and when any slave device which does not establish communication with the master device at present determines that the I2C bus is abnormal, the corresponding slave device periodically pulls down the clock line SCL.
In a second aspect, an embodiment of the present invention provides an electronic device, which is a slave device connected to an I2C bus, including:
the interface module is used for being connected to the I2C bus;
a memory module for storing information including program instructions;
and a control module for controlling execution of program instructions which, when loaded and executed by the control module, implement the method of the first aspect or any one of the first aspects.
In a third aspect, an embodiment of the present invention provides an I2C device system, including: a master device and a slave device, both connected to an I2C bus, the slave device being adapted to perform the method of the first aspect or any one of the first aspects.
Optionally, the number of slave devices connected to the I2C bus is plural, and any one slave device connected to the I2C bus is configured to perform the method of the first aspect or any one of the first aspects.
In a fourth aspect, an embodiment of the present invention provides a computer readable storage medium, where the computer readable storage medium includes a stored program, where the program when executed controls a device in which the computer readable storage medium is located to perform the method according to the first aspect or any one of the first aspects.
In the embodiment of the invention, when the slave device determines that the I2C bus communication is abnormal, the slave device can periodically pull down the clock line SCL according to the clock signal period T of the master device to recover the clock signal on the clock line SCL. After triggering a clock signal on the clock line SCL based on the control of the slave device, the master device may take the ACK or data bit on the data line SDA and thus may resume communication on the I2C bus. It can be seen that in the embodiment of the present invention, when the I2C bus is in communication abnormality, the communication on the I2C bus can be restored by the operation from the device side.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an I2C-based device system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of data transmission timing sequences of a master device and a slave device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a start signal according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an I2C bus with abnormal communication according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method for handling I2C communication anomalies according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a restoration of communications on an I2C bus according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For a better understanding of the technical solutions of the embodiments of the present invention, the following describes the embodiments of the present invention in detail with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all embodiments of the present invention. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the invention, are intended to be within the scope of the embodiments of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
I2C communication is a serial communication scheme. The I2C communication uses a master-slave architecture, which is convenient for the main board, the embedded system or the electronic equipment to establish communication with the peripheral equipment component. Because of the simplicity of the I2C protocol, it is widely used for communication between microcontrollers and sensor arrays, displays, ioT devices or EEPROMs, etc. Referring to fig. 1, a schematic diagram of an I2C-based device system is provided in an embodiment of the present invention. As shown in fig. 1, the I2C bus includes a data line SDA and a clock line SCL. The master and slave devices are both connected to the data line SDA and the clock line SCL. The master-slave architecture of the I2C may be a one-to-one architecture, i.e. comprising one master device and one slave device, or a one-to-many architecture, i.e. comprising one master device and a plurality of slave devices. Fig. 1 shows a one-to-many architecture, where one master corresponds to a plurality of slaves, such as slave 1, slave 2, and slave 3.
The I2C communication is initiated and dominant by the master device. The master device may decide which slave device to communicate with at a certain time. The slave passively accepts and responds to the master's communication.
Referring to fig. 2, a schematic diagram of data transmission timing of a master device and a slave device according to an embodiment of the present invention is provided. As shown in fig. 2, the data transmission timing between the master device and the slave device is mainly divided into: start transmission, data transmission and end transmission.
(1) Transmission is started. The start transmission is initiated by the master device for transmitting a start signal initiated by the master device. As shown in fig. 3, when the I2C bus is idle, both the data line SDA and the clock line SCL are in a high state. When the master device initiates communication, the master device switches the data line SDA from the high level to the low level, and a transition signal that the data line SDA switches from the high level to the low level may be used as a start signal for starting data transmission. The slave devices, such as slave device 1, slave device 2, and slave device 3 in fig. 1, enter the active state from the sleep state after detecting the start signal transmitted by the master device. Slave 1, slave 2 and slave 3 wait to receive the address signal sent by the master after entering the active state.
(2) And (5) data transmission. As shown in fig. 2, after the master device transmits the start signal, data transmission between the master device and the slave device starts. As shown in fig. 2, the data transmission between the master device and the slave device includes: address bits, read/write bits, and data bits, wherein each time data is transmitted, the peer device sends a response bit. Specifically, as shown in fig. 3, after the master triggers the start signal on the data line SDA, the master pulls down the level of the clock line SCL and transmits the clock signal on the clock line SCL. During the process of the master device transmitting a clock signal on the clock line SCL, the master device may transmit address bits and read/write bits on the data line SDA. Wherein each slave device connected to the I2C bus has a respective slave device address. The address bits sent by the master device on the data line SDA are used to represent the address of the target slave device to be communicated. The read/write bit sent by the master on the data line SDA is used to indicate whether the master needs to read or write to the target slave.
After each slave device detects the address bit and the read/write bit sent by the master device on the data line SDA, it is determined whether the address bit sent on the data line SDA is identical to the own slave device address. If so, the slave pulls down the data line SDA to return an ACK to the master in response to the communication with the master. Alternatively, a slave device whose address coincides with an address bit transmitted by the master device may also be referred to as a target slave device, or may also be referred to as a slave device that is currently establishing communication with the master device. If the address bits sent on the SDA do not match the slave device address of the slave device itself, the slave device does not respond at this time. Alternatively, a slave device whose address does not coincide with the address bits transmitted by the master device may be referred to as a slave device that is not currently establishing communication with the master device.
After the master device determines the target slave device according to the ACK signal, transmission of data bits between the master device and the target slave device is started. Optionally, the data bit transfer between the master and the slave device includes the master writing data to the target slave device and the master reading data to the target slave device. Alternatively, each transfer of data between the master device and the target slave device is typically a fixed number of bits followed by a response bit. In some examples, 8 bits are transmitted between the master device and the target slave device each time, with the response bit being transmitted at the 9 th bit. For example, the master device transmits 8 bits on the data line SDA each time when writing data to the target slave device. The target slave pulls down the data line SDA at bit 9 to send an ACK signal to the master. Similarly, when the master device reads data from the target slave device, the target slave device transmits 8 bits on the data line SDA each time, and the master device pulls down the data line SDA at the 9 th bit to send an ACK signal to the target slave device.
(3) Ending the transmission. When the transmission of the data bits between the master device and the slave device ends, the master device sends an end signal to the target slave device. If the data line SDA is not occupied by the slave device, the data line SDA is controlled to be at a low level by the master device, and the clock line SCL is at a high level, when the master device switches the data line SDA from a low level to a high level, a transition signal generated when the data line SDA is switched from a low level to a high level may be used as an end signal.
In the process of the I2C data transmission, the following situation may sometimes occur, 1, when the slave device replies with an ACK, the master device is abnormally reset. 2. The slave device is abnormally reset when replying to data bit 0. The same points for both cases are: as shown in fig. 4, the data line SDA is in a pulled-down state by the slave device at the time of the master device abnormal reset, and the clock line SCL is in a high state after the master device reset. At this point the slave will wait for the master to pull down the clock line SCL to take the ACK or data bit 0 and the master will wait for the slave to release the data line SDA. As shown in fig. 4, from the time t1, the clock line SCL and the data line SDA enter a mutually waiting state, and if the duration of the state reaches a preset abnormality detection threshold, it is determined that the I2C bus communication is abnormal. When I2C bus communication is abnormal, I2C communication is normally resumed by the operation of the master device side in the related art. Unlike the related art, the embodiment of the invention provides a method for processing I2C communication exception. The method of the embodiment of the invention operates the I2C bus at the slave device side to restore the communication on the I2C bus.
Referring to fig. 5, a flowchart of a method for processing an I2C communication exception is provided in an embodiment of the present invention. As shown in fig. 5, the processing steps of the method include:
the slave determines 201 the clock signal period T transmitted by the master on the clock line SCL.
202, when the slave determines that the I2C bus communication is abnormal, the slave periodically pulls down the clock line SCL according to the clock signal period T to generate a first clock signal on the clock line SCL, the first clock signal being used to resume communication on the I2C bus.
In the embodiment of the present invention, when the slave device determines that the I2C bus is abnormal in communication, the slave device periodically pulls down the clock line SCL according to the clock signal period T triggered by the master device before the communication abnormality to recover the clock signal on the clock line SCL. After the master device detects the clock signal on the clock line SCL, the master device may take away the data bits transmitted on the data line SDA, thereby resuming communication on the I2C bus.
In step 202, the slave device determines that the I2C bus communication is abnormal, including: when the slave device detects that the clock line SCL remains high and the data line SDA remains low and the duration of this state is greater than or equal to the abnormality detection threshold, the slave device determines that the I2C bus communication is abnormal. In the embodiment of the present invention, when the clock line SCL is kept high and the data line SDA is kept low, it is possible that the I2C bus is transmitting the data bit 0, and that the communication of the I2C bus is abnormal. Thus, when the slave detects that the clock line SCL remains high and the data line SDA remains low, the I2C bus is not immediately operated, but the duration of this state is clocked. If the duration of the clock line SCL remaining high and the data line SDA remaining low is greater than or equal to the abnormality detection threshold, the slave determines that a communication abnormality has occurred in the I2C bus. The slave device periodically pulls down the clock line SCL at this time according to the clock signal period T to generate the first clock signal on the clock line SCL. Alternatively, the abnormality detection threshold may be set as needed. In some embodiments, the anomaly detection threshold may be n1×t, where n1 is a positive integer. I.e. the duration of the clock line SCL remaining high and the data line SDA remaining low is greater than or equal to n1 clock signal periods T, the slave periodically pulls down the clock line SCL to generate the first clock signal on the clock line SCL.
In some embodiments, the slave periodically pulling down the clock line SCL to generate the first clock signal on the clock line SCL comprises: the period of the first clock signal is T. Periodically pulling down the clock line SCL from the device comprises: the first m period of each period T pulled down by the slave device is low, m being a preset known value. In some embodiments, the slave device may pull down the first 30%, the first 50%, the first 70%, or other possible periods of time of each cycle T low, thereby generating the first clock signal on the clock line SCL.
In some embodiments, the slave device stops control of the clock line SCL when the slave device detects that the master device resumes transmitting the second clock signal on the clock line SCL. That is, the slave device stops control of the clock line SCL after determining that the master device resumes transmitting the clock signal on the clock line SCL.
In some embodiments, the slave device further counts the total duration of the I2C bus being in communication anomaly. Optionally, the counting, by the slave device, the total duration that the I2C bus is in abnormal communication includes: the slave device determines the total duration of the I2C bus in communication abnormality according to the abnormality detection threshold and the duration of the first clock signal. As shown in fig. 6, at time t1, the slave detects that the clock line SCL is in a high state and the data line SDA is in a low state. At this time, the I2C bus may be transmitting data bit 0, and the I2C bus may be abnormal in communication. To determine if the I2C bus is communicating abnormally, the slave device continues to detect the states of SCL and SDA and counts the duration that the clock line SCL remains high and the data line SDA remains low. If the duration of the high level on the clock line SCL and the low level on the data line SDA is greater than or equal to the set abnormality detection threshold n 1T at time T2, the slave determines that the I2C bus communication is abnormal at time T2. Optionally, after the slave device determines that the I2C bus is abnormal in communication at time t2, the slave device may determine that the I2C bus may determine time t1 as an initial time of the I2C bus abnormal in communication. By the time T2, the duration of the I2C bus communication abnormality is t2—t1=abnormality detection threshold n1×t.
In the example given in fig. 6, the slave determines that the I2C bus communication is abnormal at time t2, and the slave periodically pulls down the clock line SCL to recover the clock signal on the clock line SCL starting at time t 2. When the duration of n2×t from the time T2 reaches the time T3, the slave detects that the master starts to resume transmitting the second clock signal on the clock line SCL, and the time T3 is the communication resume time for resuming the communication on the I2C bus, and the duration of the first clock signal is T3-t2=n2×t. As can be seen from the above, the I2C bus is in the abnormal communication state in the period T1-T3, and the total duration of the I2C bus in abnormal communication=the abnormal detection threshold+the duration of the first clock signal=n1×t+n2×t. Alternatively, n1 may be set according to actual needs, and n2 is determined according to the time when the master device resumes clock signal transmission. Optionally, the slave device may provide the total duration of the I2C bus in communication abnormality to the user, so that the user may obtain the communication abnormality information of the I2C bus.
In the system of devices of I2C shown in fig. 1, any slave device connected to the I2C bus may perform the method of the embodiment of the present invention. The arbitrary device may be a slave device that is currently in communication with the master device, or may be a slave device that is connected to the I2C bus and is not currently in communication with the master device. The following will respectively describe the embodiments.
In one example, a slave device currently in communication with a master device is used to perform the method of embodiments of the present invention. The slave device currently establishing communication with the master device refers to a slave device with a slave device address consistent with an address bit sent by the master device. Referring to the device system shown in fig. 1, after the master device transmits a start signal, the master device transmits address bit information. If the slave address of the slave 1 coincides with the address bit sent by the master, the slave 1 is the slave currently establishing communication with the master. During communication between the master and the slave 1, the slave 1 determines the period T of the clock signal transmitted by the master on the clock line SCL. Alternatively, the slave device 1 may sample the clock signal transmitted from the master device during communication with the master device, so as to obtain the clock signal period T and store the clock signal period T. Optionally, the slave device 1 also detects the level state of the I2C bus during communication with the master device. If the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to the abnormality detection threshold n1 x T, the slave device 1 determines that the I2C bus communication is abnormal. When the slave device 1 determines that the I2C bus communication is abnormal, the slave device 1 periodically pulls down the clock line SCL according to the clock signal period T that has been stored to generate the first clock signal on the clock line SCL, n1 being a preset known value. After the master device detects the clock signal on the clock line SCL, the data bits on the data line SDA may be taken away and the transmission of the clock signal on the clock line SCL is resumed. When the slave 1 detects that the master resumes transmitting the clock signal on the clock line SCL, the slave 1 stops the control of the clock line SCL. Optionally, the slave device 1 may further determine a total duration of the I2C bus being in abnormal communication according to the abnormality detection threshold and the duration of the first clock signal.
In one example, a slave device in a system of devices that is not currently in communication with a master device is used to perform the method of embodiments of the present invention. Wherein, the slave device which does not establish communication with the master device currently refers to the slave device of which the address of the slave device is inconsistent with the address bit sent by the master device. Referring to the device system shown in fig. 1, after the master device transmits a start signal, the master device transmits address bit information. If the slave address of the slave 1 coincides with the address bit sent by the master, the slave 1 is the slave currently establishing communication with the master. If the address bits sent by the slaves 2 and 3 and the master do not coincide, then the slaves 2 and 3 are not currently a slave that establishes communication with the master. During communication between the master and slave 1, the slave 2 and/or slave 3 may detect the communication status of the I2C bus. Alternatively, one of the device 2 and the slave device 3 may be used to perform the method of the embodiment of the invention. Taking the slave device 2 as an example, the slave device 2 determines the period T of the clock signal transmitted by the master device according to the history of communication with the master device. When the slave device 2 detects an I2C bus communication anomaly, the slave device 2 periodically pulls down the clock line SCL to recover the first clock signal on the clock line SCL. When the slave device 2 detects that the master device resumes transmitting the clock signal on the clock line SCL, the slave device 2 stops the control of the clock line SCL. Optionally, the slave device 2 may further determine a total duration of the I2C bus in abnormal communication according to the abnormality detection threshold and the duration of the first clock signal. In the embodiment of the invention, the communication of the I2C bus can be recovered through the slave device which is not communicated with the master device currently in the device system, so that the communication state between the master device and the target slave device is recovered as soon as possible.
In some examples, each slave device in the device system shown in fig. 1 has a respective anomaly detection threshold. The abnormality detection threshold values of the respective slave devices may be the same or different. When the master device communicates with one of the slave devices, each slave device may determine whether the I2C bus is abnormal in communication according to its own abnormality detection threshold, and when any one of the slave devices connected to the I2C bus determines that the I2C bus is abnormal in communication, the corresponding slave device periodically pulls down the clock line SCL. In this manner, each slave device connected to the I2C bus competes for opportunities to resume communication with the I2C bus in accordance with its own anomaly detection threshold.
For example, the abnormality detection threshold value corresponding to the slave device 1 is n1×t, the abnormality detection threshold value corresponding to the slave device 2 is (n1+1) ×t, and the abnormality detection threshold value corresponding to the slave device 3 is (n1+2) ×t. If the slave device 1 is currently communicating with the master device. When the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to n1 x T, the slave device 1 generates a first clock signal on the clock line SCL to resume communication between the master device and the slave device 1. At this point, communication on the I2C bus is restored by the slave device that is currently in communication with the master device. If the slave device 2 is currently in communication with the master device. When the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to n 1T, the slave device 1 generates a first clock signal on the clock line SCL to resume communication between the master device and the slave device 2. At this point, communication on the I2C bus is restored by the slave device that is not currently communicating with the master device.
In some examples, each slave device in the device system shown in fig. 1 has a respective anomaly detection threshold. The abnormality detection threshold values of the respective slave devices may be the same or different. When the I2C bus communication is abnormal, the slave device which does not establish communication with the master device at present determines whether the I2C bus communication is abnormal according to the abnormality detection threshold value of the slave device, and when any slave device which does not establish communication with the master device at present determines that the I2C bus communication is abnormal, the corresponding slave device periodically pulls down the clock line SCL. In this manner, communication on the I2C bus is always restored by a slave device that is not currently communicating with the master device.
For example, the abnormality detection threshold value corresponding to the slave device 1 is n1×t, the abnormality detection threshold value corresponding to the slave device 2 is (n1+1) ×t, and the abnormality detection threshold value corresponding to the slave device 3 is (n1+2) ×t. If the slave device 1 is currently communicating with the master device. When the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to (n1+1) T, the slave device 2 generates a first clock signal on the clock line SCL to resume communication between the master device and the slave device 1. If the slave device 2 is currently in communication with the master device. When the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to n1 x T, the slave device 1 generates a first clock signal on the clock line SCL to resume communication between the master device and the slave device 2. If the slave device 3 is currently in communication with the master device. When the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to n 1T, the slave device 1 generates a first clock signal on the clock line SCL to resume communication between the master device and the slave device 3.
Referring to fig. 7, a schematic diagram of an electronic device according to an embodiment of the present invention is provided. The electronic device shown in fig. 7 is a slave device connected to the I2C bus. Alternatively, the electronic device shown in fig. 7 may be a slave device that is currently establishing communication with the master device, or may be a slave device that is not currently establishing communication with the master device. As shown in fig. 7, the electronic device includes: the device comprises an interface module, a storage module and a control module. The interface module is used for being connected to the I2C bus. The interface module establishes a connection with the master device via the data line SDA and the clock line SCL. And the storage module is used for storing information comprising program instructions. Optionally, the storage module may be further configured to store a clock signal period T sent by the master device. And the control module is used for controlling the execution of program instructions, and the processing method of the I2C communication abnormality is realized when the program instructions are loaded and executed by the control module.
The embodiment of the invention also protects an I2C equipment system. The I2C equipment system comprises a master equipment and a slave equipment, wherein the master equipment and the slave equipment are both connected to an I2C bus, and the slave equipment is used for executing the I2C communication exception processing method.
In some embodiments, the number of the slave devices connected to the I2C bus is plural, and any slave device connected to the I2C bus may be used to perform the method for handling the I2C communication exception.
Embodiments of the present invention also protect a computer-readable storage medium. The computer readable storage medium comprises a stored program, wherein the program is used for controlling equipment where the computer readable storage medium is located to execute the method for processing the I2C communication abnormality when running.
Any combination of one or more computer readable media may be utilized as the above-described computer readable storage media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory; EPROM) or flash Memory, an optical fiber, a portable compact disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein. The foregoing is merely specific embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A method for handling an I2C communication exception, comprising:
the slave device determines a clock signal period T transmitted by the master device on the clock line SCL;
when the slave determines that the I2C bus communication is abnormal, the slave periodically pulls down the clock line SCL according to the clock signal period T to generate a first clock signal on the clock line SCL, the first clock signal being used to resume communication on the I2C bus.
2. The method of claim 1, wherein the slave device determining that an I2C bus communication is abnormal comprises:
the slave device determines that I2C bus communication is abnormal when it detects that the clock line SCL remains high and the data line SDA remains low and the duration is greater than or equal to an abnormality detection threshold.
3. The method of claim 1, wherein the slave device periodically pulling down a clock line SCL to generate a first clock signal on the clock line SCL according to the clock signal period T, comprising:
the period of the first clock signal is T, the first m period of each period T of the first clock signal is low level, and m is a preset known value.
4. The method according to claim 1, wherein the method further comprises:
the slave device stops control of the clock line SCL when it detects that the master device resumes sending the second clock signal on the clock line SCL.
5. The method according to claim 1, wherein the slave device is provided with an anomaly detection threshold for determining an I2C bus communication anomaly, the method further comprising:
and the slave equipment determines the total duration of the I2C bus communication abnormality according to the abnormality detection threshold and the duration of the first clock signal.
6. The method of claim 1, wherein the slave device is any slave device connected to an I2C bus.
7. The method of claim 1 or 6, wherein when the slave device determines that an I2C bus communication is abnormal, the slave device periodically pulls down a clock line SCL according to the clock signal period T to generate a first clock signal on the clock line SCL, comprising:
each slave device connected to the I2C bus has a respective anomaly detection threshold;
each slave device determines whether the I2C bus is abnormal in communication according to the abnormality detection threshold value of the slave device, and when any slave device connected to the I2C bus determines that the I2C bus is abnormal in communication, the corresponding slave device periodically pulls down the clock line SCL; or,
the slave device which does not establish communication with the master device at present determines whether the I2C bus is abnormal according to the abnormality detection threshold value of the slave device, and when any slave device which does not establish communication with the master device at present determines that the I2C bus is abnormal, the corresponding slave device periodically pulls down the clock line SCL.
8. An electronic device, wherein the electronic device is a slave device connected to an I2C bus, comprising:
the interface module is used for being connected to the I2C bus;
a memory module for storing information including program instructions;
control module for controlling the execution of program instructions which, when loaded and executed by the control module, implement the method of any one of claims 1 to 7.
9. An I2C device system, comprising: a master device and a slave device, both connected to an I2C bus, the slave device being adapted to perform the method of any of claims 1 to 7.
10. The system of claim 9, wherein the number of slave devices connected to the I2C bus is a plurality, and any slave device connected to the I2C bus is configured to perform the method of any of claims 1 to 7.
11. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored program, wherein the program, when run, controls a device in which the computer readable storage medium is located to perform the method of any one of claims 1 to 7.
CN202310172134.0A 2023-02-24 2023-02-24 I2C communication exception handling method, electronic equipment, system and storage medium Pending CN116107790A (en)

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