CN115268572B - Real-time clock circuit - Google Patents
Real-time clock circuit Download PDFInfo
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- CN115268572B CN115268572B CN202210911687.9A CN202210911687A CN115268572B CN 115268572 B CN115268572 B CN 115268572B CN 202210911687 A CN202210911687 A CN 202210911687A CN 115268572 B CN115268572 B CN 115268572B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application discloses a real-time clock circuit, which relates to the technical field of electronic circuits and comprises an oscillating circuit for outputting a first clock signal, a second alternative switch, a first frequency divider, a clock detection circuit and a control unit, wherein the clock detection circuit is connected with the oscillating circuit; the clock detection circuit is used for calculating the frequency of an input second clock signal according to the first clock signal, judging whether the frequency of the second clock signal is in a preset frequency range, if so, outputting a detection result to the control unit, and outputting the second clock signal to the frequency divider I; the input end of the first frequency divider is connected with the clock detection circuit, the output end of the first frequency divider is connected with the alternative switch, and the output end of the oscillating circuit and the output end of the first frequency divider are connected with the alternative switch; the method and the device have the effect of improving the reliability of the real-time clock circuit.
Description
Technical Field
The present application relates to the field of electronic circuits, and more particularly to a real-time clock circuit.
Background
Real-time clocks, which provide a time reference for various electronic systems, are used in almost every electronic device manufactured today.
In the related art, referring to fig. 1, a general real-time clock circuit includes a crystal oscillator, an oscillation circuit, a temperature detection compensation circuit, a frequency divider, and an output driving stage, wherein the output terminal of the crystal oscillator and the input terminal of the temperature detection compensation circuit are both connected to the input terminal of the oscillation circuit, the output terminal of the oscillation circuit is connected to the input terminal of the frequency divider, and the output terminal of the frequency divider is connected to the input terminal of the output driving stage. The real time clock circuit is battery powered, the operating current in the circuit is typically less than 800nA, and the oscillation frequency of the crystal oscillator is typically 32.768KHz.
For the above related art, the inventors found that: the real-time clock circuit has only one clock source, namely the crystal oscillator clock source OSC, so that the reliability of the whole real-time clock circuit is low.
Disclosure of Invention
In order to improve the reliability of the real-time clock circuit, the application provides the real-time clock circuit.
The real-time clock circuit adopts the following technical scheme:
the real-time clock circuit comprises an oscillating circuit for outputting a first clock signal, a second switch, a first frequency divider, a clock detection circuit and a control unit, wherein the clock detection circuit is connected with the oscillating circuit; the clock detection circuit is used for calculating the frequency of an input second clock signal according to the first clock signal, judging whether the frequency of the second clock signal is in a preset frequency range, if so, outputting a detection result to the control unit, and outputting the second clock signal to the frequency divider I;
the input end of the frequency divider I is connected with the clock detection circuit, and the output end of the frequency divider I is connected with the alternative switch;
the output end of the oscillating circuit and the output end of the frequency divider I are connected with the alternative switch;
the clock detection circuit, the first frequency divider and the second switch are all connected with the control unit, and the control unit is used for adjusting the frequency division ratio of the first frequency divider according to the detection result and controlling the second switch to switch and output the first clock signal and the second clock signal.
By adopting the technical scheme, when the clock detection circuit detects that the input second clock signal is in the preset frequency range according to the first clock signal, the clock detection circuit outputs a detection result to the control unit and outputs the second clock signal to the first frequency divider, and the control unit adjusts the frequency division ratio of the first frequency divider according to the detection result and controls the two-to-one switch to switch and output the first clock signal and the second clock signal; the real-time clock circuit has two clock sources of the first clock signal and the second clock signal, so that the reliability of the real-time clock circuit is improved, and the application flexibility of the real-time clock circuit is improved.
Optionally, the clock detection circuit includes a counter and a decoder;
the first input end of the counter is connected with the oscillating circuit, the second input end of the counter is used for inputting a second clock signal, and the counter is used for calculating and obtaining frequency codes corresponding to the frequency of the second clock signal according to the first clock signal and the second clock signal;
the first input end of the decoder is connected with the output end of the counter, the second input end of the decoder is connected with the control unit, and the decoder is used for outputting a detection result code corresponding to the detection result to the control unit according to the frequency code and the frequency offset code output by the control unit.
By adopting the technical scheme, the counter can calculate the frequency code corresponding to the frequency of the second clock signal according to the first clock signal and the second clock signal, after the decoder receives the frequency code, the decoder outputs the corresponding detection result code to the control unit according to the frequency code and the frequency offset code input by the control unit, and the control unit adjusts the frequency division ratio of the frequency divider II according to the detection result code and controls the alternative switch to switch and output the first clock signal and the second clock signal.
Optionally, the real-time clock circuit further includes a power management circuit, the power management circuit is connected with an external power supply VDD and a battery VBAT, and the power management circuit is respectively connected with the control unit and the clock detection circuit; the power management circuit is used for periodically detecting whether the external power supply VDD is powered or not, if the external power supply VDD is powered off, the first clock signal is switched to be a clock source, the clock detection circuit is closed, and if the external power supply VDD is powered on, the clock detection circuit is started.
By adopting the technical scheme, the power management circuit can periodically detect whether the external power supply VDD supplies power, if the external power supply VDD is powered down, the control unit is switched to the first clock signal as a clock source and turns off the clock detection circuit, and if the external power supply VDD supplies power, the control unit turns on the clock detection circuit, so that the probability of the battery VBAT being exhausted due to higher frequency of the second clock signal is reduced.
Optionally, the power management circuit includes a MOS transistor and a power detection circuit for controlling on-off of the MOS transistor, a drain electrode of the MOS transistor is connected to an external power supply VDD, and a source electrode of the MOS transistor is connected to a battery VBAT; the power supply detection circuit is connected with an enable end EN provided by the control unit, and comprises:
one end of the first resistor R1 is connected with the drain electrode of the MOS tube;
a second resistor R2, one end of which is connected to the other end of the first resistor R1, and the other end of which is grounded;
a comparator, one input pin is connected with the other end of the first resistor R1, and the other input pin is connected with a voltage reference source VREF; and the input end of the switch control circuit is connected with the output end of the comparator, and the output end of the switch control circuit is connected with the grid electrode of the MOS tube.
Through adopting above-mentioned technical scheme, the controller opens the power detection circuitry through enable end EN timing, after the power detection circuitry opened, switch control circuit cuts off the MOS pipe, then the comparator compares the voltage of external power supply VDD with the voltage of voltage reference source VREF, if the voltage of external power supply VDD is higher than the voltage of voltage reference source VREF, then indicate VDD normal power supply, switch control circuit then control MOS pipe switches on for clock detection circuitry opens, if the voltage of external power supply VDD is lower than the voltage of voltage reference source VREF, then indicate VDD and fall the power, switch control circuit then control MOS pipe switches off, so that clock detection circuitry closes.
Optionally, the real-time clock circuit further includes a second frequency divider, an input end of the second frequency divider is connected with an output end of the second switch, the second frequency divider is connected with the second switch, and the second frequency divider is used for dividing the frequency of the first clock signal or the second clock signal and outputting the divided frequency.
By adopting the technical scheme, the frequency divider II is used for carrying out frequency division processing on the first clock signal or the second clock signal output by the alternative switch, namely, converting the high-frequency clock signal into the low-frequency clock signal and outputting the first clock signal or the second clock signal after frequency division.
Optionally, the output end of the second frequency divider is connected with an output driving stage, and the output driving stage is used for amplifying and outputting the first clock signal or the second clock signal.
Optionally, the first frequency divider and the second frequency divider are programmable frequency dividers.
By adopting the technical scheme, the control unit can adjust the frequency division ratio of the first frequency divider and the second frequency divider.
Optionally, the MOS transistor includes a P-channel MOS transistor.
In summary, the present application includes at least one of the following beneficial technical effects: when the clock detection circuit detects that the input second clock signal is in a preset frequency range according to the first clock signal, the clock detection circuit outputs a detection result to the control unit and outputs the second clock signal to the first frequency divider, and the control unit adjusts the frequency division ratio of the first frequency divider according to the detection result and controls the two-to-one switch to switch and output the first clock signal and the second clock signal; the real-time clock circuit has two clock sources of the first clock signal and the second clock signal, so that the reliability of the real-time clock circuit is improved, and the application flexibility of the real-time clock circuit is improved.
Drawings
Fig. 1 is a circuit diagram of a real-time clock circuit in the background art.
Fig. 2 is a circuit diagram of the real time clock circuit of the present application.
Fig. 3 is a circuit diagram of a clock detection circuit of the real-time clock circuit of the present application.
Fig. 4 is a circuit diagram of a power management circuit of the real-time clock circuit of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to fig. 2 to 4 and the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The embodiment of the application discloses a real-time clock circuit.
Referring to fig. 2, a real-time clock circuit includes an oscillating circuit for outputting a first clock signal, and further includes a second alternative switch, a first frequency divider, a clock detection circuit, and a control unit, where the clock detection circuit is connected to the oscillating circuit; the clock detection circuit is used for calculating the frequency of the input second clock signal according to the first clock signal, judging whether the frequency of the second clock signal is in a preset frequency range, if so, outputting a detection result to the control unit, and outputting the second clock signal to the frequency divider I;
the input end of the first frequency divider is connected with the clock detection circuit, and the output end of the first frequency divider is connected with the alternative switch;
the output end of the oscillating circuit and the output end of the frequency divider I are connected with the alternative switch;
the clock detection circuit, the first frequency divider and the second switch are connected with the control unit, and the control unit is used for adjusting the frequency division ratio of the first frequency divider according to the detection result and controlling the second switch to switch and output the first clock signal and the second clock signal.
The oscillating circuit is connected with a crystal oscillator and a temperature detection compensation circuit, wherein the first clock signal is a crystal oscillator clock OSC and is a reference clock of the clock detection circuit; the second clock signal is an external clock CLK supporting a high-speed clock frequency, typically on the order of MHz.
It should be further noted that, in the present embodiment, if the frequency of the external clock CLK is within the preset frequency range, the clock source selectable by the alternative switch is the external clock CLK and the crystal oscillator clock OSC; since there may be a large error in the use of the crystal oscillator clock OSC over a long period of time, the default external clock CLK is preferentially used as the clock source, thereby improving flexibility in the application of the real-time clock circuit.
It should be further noted that, the switching between the first clock signal and the second clock signal is usually required to be completed within half a period of the crystal oscillator clock OSC, so as to reduce the influence on the real-time clock circuit; the frequency detection accuracy is determined by the period of the external clock CLK and the period of the crystal oscillator clock OSC, and the theoretical detection error=n (±t) CLK )/T OSC N=1/detection interval period (half period: n=2; one period: n=1; two periods: n=1/2; … …), the detection interval period being a ratio of a time difference of the clock detection circuit adjacent two times to detect the external clock CLK to a period of the crystal oscillator clock OSC.
Referring to fig. 3, as one embodiment of the clock detection circuit, the clock detection circuit includes a counter and a decoder; the first input end of the counter is connected with the oscillating circuit, the second input end of the counter is used for inputting a second clock signal, and the counter is used for calculating and obtaining frequency codes corresponding to the frequency of the second clock signal according to the first clock signal and the second clock signal; the first input end of the decoder is connected with the output end of the counter, the second input end of the decoder is connected with the control unit, and the decoder is used for outputting a detection result code corresponding to the detection result according to the frequency code and the frequency offset code output by the control unit to the control unit.
In this embodiment, referring to table 1, the preset frequency range is 1MHz to 32MHz, and the interval between adjacent frequency detection points is about 1 MHz.
The number of bits of the counter is 10 bits, D [9:0] represents frequency coding; d [9:0] corresponds to the binary encoding of the counted clock counts during a detection period, different clock counts corresponding to different clock frequencies. C4:0 represents the frequency offset code, and F4:0 represents the detection result code.
The counter is triggered by the rising edge of the external clock CLK; the rising edge counter counts the crystal oscillator clock OSC and outputs D [9:0] to the decoder, and the falling edge decoder outputs F [4:0] to the control unit according to D [9:0] and C [4:0 ]. If the detection precision needs to be improved, the output bit number of the decoder can be improved; if the range of the preset frequency needs to be increased, the number of bits of the counter can be increased.
The adjusting range of C4:0 corresponds to the range between two adjacent frequency detection points, taking output F4:0=00001 as an example, when C4:0=00000, the counter determining point D9:0= 00001 00000, the frequency detection point is 1.049MHz; when C [4:0] =11111, the counter decision point D [9:0] = 00001 11111, the frequency detection point is close to 2.097MHz, i.e. when D [9:5] =00001, C [4:0] is adjusted in the range of 00000-11111, the detectable frequency range is 1.049 MHz-2.097 MHz.
Table 1
| D[9:0] | Clock counting | Frequency detection point (MHz) | F[4:0] |
| 00000 00000 | 0 | 0.000 | 00000 |
| 00001 00000 | 1x32 | 1.049 | 00001 |
| 00010 00000 | 2x32 | 2.097 | 00010 |
| 00011 00000 | 3x32 | 3.146 | 00011 |
| …… | …… | …… | …… |
| …… | …… | …… | …… |
| 11100 00000 | 28x32 | 29.360 | 11100 |
| 11101 00000 | 29x32 | 30.409 | 11101 |
| 11110 00000 | 30x32 | 31.457 | 11110 |
| 11111 00000 | 31x32 | 32.506 | 11111 |
Referring to fig. 2, in order to reduce the probability of the second clock signal having a higher frequency, which leads to the exhaustion of the electric quantity of the battery VBAT, the real-time clock circuit further includes a power management circuit connected to the external power supply VDD and the battery VBAT, the power management circuit being connected to the control unit and the clock detection circuit, respectively; the power management circuit is used for periodically detecting whether the external power supply VDD is powered or not, if the external power supply VDD is powered down, the first clock signal is switched to be a clock source, the clock detection circuit is closed, and if the external power supply VDD is powered down, the clock detection circuit is started.
It should be noted that, since the external clock CLK supports a high-speed clock frequency, when the frequency of the external clock CLK is high, the current in the real-time clock circuit is far greater than 800nA, and if the battery VBAT is powered, the battery may be exhausted, so that the external power VDD is needed to supply power when the frequency of the external clock CLK is high.
Referring to fig. 2, as one implementation manner of the power management circuit, the power management circuit includes a MOS transistor and a power detection circuit for controlling on/off of the MOS transistor, in this embodiment, the MOS transistor is a P-channel MOS transistor, a drain electrode of the MOS transistor is connected to an external power supply VDD, and a source electrode of the MOS transistor is connected to a battery VBAT; the power supply detection circuit is connected to an enable terminal EN provided by the control unit. The power supply detection circuit comprises a first resistor R1, a second resistor R2, a comparator and a switch control circuit, wherein one end of the first resistor R1 is connected with the drain electrode of the MOS tube; one end of the second resistor R2 is connected with the other end of the first resistor R1, and the other end of the second resistor R2 is grounded; one input pin of the comparator is connected with the other end of the first resistor R1, and the other input pin of the comparator is connected with a voltage reference source VREF; the input end of the switch control circuit is connected with the output end of the comparator, and the output end of the switch control circuit is connected with the grid electrode of the MOS tube.
Referring to fig. 2, the real-time clock circuit further includes a second frequency divider, an input end of the second frequency divider is connected with an output end of the second switch, the second frequency divider is connected with the second switch, and the second frequency divider is used for dividing the frequency of the first clock signal or the second clock signal and outputting the divided frequency.
Referring to fig. 2, an output terminal of the second frequency divider is connected to an output driving stage, and the output driving stage is configured to amplify and output the first clock signal or the second clock signal.
Referring to fig. 2, the first and second frequency dividers are programmable frequency dividers.
It should be noted that, the control unit is connected with the I2C bus SDA/SCL, and the frequency dividing ratio of the first frequency divider and the second frequency divider can be set through the I2C bus SDA/SCL; if the application of the real-time clock circuit is fixed and the frequency of the external clock CLK is constant, the preset frequency range of the clock detection circuit and the frequency division ratio of the frequency divider can be set to be constant through the ISC bus SDA/SCL and the control unit.
It should be further noted that, since the clock detection circuit needs to cooperate with the first divider and the second divider, the external clock CLK cannot be of any frequency, and the frequency of the output clock FOUT finally needs to be obtained by dividing the external clock CLK by the first divider and the second divider.
The implementation principle of the real-time clock circuit in the embodiment of the application is as follows: when the clock detection circuit detects that the input second clock signal is in a preset frequency range according to the first clock signal, the clock detection circuit outputs a detection result to the control unit and outputs the second clock signal to the first frequency divider, and the control unit adjusts the frequency division ratio of the first frequency divider according to the detection result and controls the two-to-one switch to switch and output the first clock signal and the second clock signal; the real-time clock circuit has two clock sources of the first clock signal and the second clock signal, so that the reliability of the real-time clock circuit is improved, and the application flexibility of the real-time clock circuit is improved.
The foregoing description of the preferred embodiments of the present application is not intended to limit the scope of the application, in which any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.
Claims (8)
1. The real-time clock circuit comprises an oscillating circuit for outputting a first clock signal, and is characterized by further comprising a second switch, a first frequency divider, a clock detection circuit and a control unit, wherein the clock detection circuit is connected with the oscillating circuit; the clock detection circuit is used for calculating the frequency of an input second clock signal according to the first clock signal, judging whether the frequency of the second clock signal is in a preset frequency range, if so, outputting a detection result to the control unit, and outputting the second clock signal to the frequency divider I;
the input end of the frequency divider I is connected with the clock detection circuit, and the output end of the frequency divider I is connected with the alternative switch;
the output end of the oscillating circuit and the output end of the frequency divider I are connected with the alternative switch;
the clock detection circuit, the first frequency divider and the second switch are all connected with the control unit, and the control unit is used for adjusting the frequency division ratio of the first frequency divider according to the detection result and controlling the second switch to switch and output the first clock signal and the second clock signal.
2. A real time clock circuit as recited in claim 1, wherein said clock detection circuit comprises a counter and a decoder;
the first input end of the counter is connected with the oscillating circuit, the second input end of the counter is used for inputting a second clock signal, and the counter is used for calculating and obtaining frequency codes corresponding to the frequency of the second clock signal according to the first clock signal and the second clock signal;
the first input end of the decoder is connected with the output end of the counter, the second input end of the decoder is connected with the control unit, and the decoder is used for outputting a detection result code corresponding to the detection result to the control unit according to the frequency code and the frequency offset code output by the control unit.
3. The real time clock circuit according to claim 1, further comprising a power management circuit, wherein the power management circuit is connected to an external power supply VDD and a battery VBAT, and the power management circuit is connected to the control unit and the clock detection circuit, respectively; the power management circuit is used for periodically detecting whether the external power supply VDD is powered or not, if the external power supply VDD is powered off, the first clock signal is switched to be a clock source, the clock detection circuit is closed, and if the external power supply VDD is powered on, the clock detection circuit is started.
4. The real-time clock circuit according to claim 3, wherein the power management circuit comprises a MOS tube and a power detection circuit for controlling on-off of the MOS tube, a drain electrode of the MOS tube is connected with an external power supply VDD, and a source electrode of the MOS tube is connected with a battery VBAT; the power supply detection circuit is connected with an enable end EN provided by the control unit, and comprises:
one end of the first resistor R1 is connected with the drain electrode of the MOS tube;
a second resistor R2, one end of which is connected to the other end of the first resistor R1, and the other end of which is grounded;
a comparator, one input pin is connected with the other end of the first resistor R1, and the other input pin is connected with a voltage reference source VREF; the method comprises the steps of,
and the input end of the switch control circuit is connected with the output end of the comparator, and the output end of the switch control circuit is connected with the grid electrode of the MOS tube.
5. The real time clock circuit of claim 1, further comprising a second divider, wherein an input of the second divider is connected to an output of the second switch, the second divider is connected to the second switch, and the second divider is configured to divide and output the first clock signal or the second clock signal.
6. The real time clock circuit of claim 5, wherein the output of the second divider is coupled to an output driver stage, and the output driver stage is configured to amplify and output the first clock signal or the second clock signal.
7. The real time clock circuit of claim 5, wherein said first divider and said second divider are programmable dividers.
8. The real time clock circuit of claim 4, wherein the MOS transistor comprises a P-channel MOS transistor.
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