CN117498840B - Parallel coarse-fine adjustment device in single-ended analog duty cycle regulator - Google Patents
Parallel coarse-fine adjustment device in single-ended analog duty cycle regulator Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
Abstract
The invention provides a parallel coarse-fine adjustment device in a single-ended analog duty ratio adjuster, which relates to the technical field of duty ratio adjustment and comprises a main circuit, a control circuit and a control circuit, wherein the main circuit is used for conducting when the duty ratio of an input clock signal does not need to be adjusted and comprises a first inverter and a second inverter which are connected in series; the multi-stage coarse tuning circuit is used for realizing the large-scale adjustment of the duty ratio of an input clock signal, and comprises a first-stage coarse tuning circuit and a second-stage coarse tuning circuit, wherein the input end of the first-stage coarse tuning circuit is connected with the input end of the first inverter in parallel. The invention can divide the adjustment of the duty ratio of the whole clock signal into two parts of coarse adjustment and fine adjustment which are connected in parallel, and the duty ratio of the clock signal is adjusted in a mode of coarse adjustment and fine adjustment, so that the invention realizes a larger range and higher precision, has good linearity, does not increase too much area and power consumption, and can adapt to the duty ratio adjustment of the clock signals with different frequencies and characteristics.
Description
Technical Field
The invention relates to the technical field of duty ratio adjustment, in particular to a parallel coarse-fine adjustment device in a single-ended analog duty ratio adjuster.
Background
Along with the faster and faster demand on the clock signal speed, the process, voltage and temperature changes can affect the duty ratio of the signal, so that errors are generated in the processing of the signal, and the computing capability of the chip is affected. There is an urgent need to improve the duty cycle of the clock signal in a high-speed application scenario.
However, in the existing duty ratio processing technology, the rising edge or the falling edge of the clock signal is adjusted by adjusting the size of the load capacitor on the clock path, and the duty ratio of the clock is adjusted by the load capacitor, so that the adjustment range and the accuracy of the duty ratio are limited, the load area is increased, the adaptability to different frequencies and clock signal characteristics is poor, and the method is not an ideal method for adjusting the duty ratio of the clock signal.
Disclosure of Invention
The present invention is directed to a parallel coarse-fine tuning device in a single-ended analog duty cycle adjuster, which solves the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
A parallel coarse-fine tuning device in a single-ended analog duty cycle adjuster, comprising:
a main circuit for conducting when the duty ratio of an input clock signal does not need to be adjusted, the main circuit comprising a first inverter and a second inverter connected in series;
The multi-stage coarse tuning circuit is used for realizing the large-range adjustment of the duty ratio of an input clock signal, and comprises a first-stage coarse tuning circuit and a second-stage coarse tuning circuit, wherein the input end of the first-stage coarse tuning circuit is connected with the input end of a first inverter in parallel, the input end of the second-stage coarse tuning circuit is connected with the output end of the first-stage coarse tuning circuit in cascade, the output end of the second-stage coarse tuning circuit is connected with the output end of the second inverter in parallel, the first-stage coarse tuning circuit comprises a P0-MOS tube and an N0-MOS tube which are connected in parallel, and the second-stage coarse tuning circuit comprises a P1-MOS tube and an N1-MOS tube which are connected in parallel;
The multistage fine adjustment circuit is used for fine adjustment of the duty ratio of an input clock signal, the multistage fine adjustment circuit comprises a first stage fine adjustment circuit and a second stage fine adjustment circuit, the input end of the first stage fine adjustment circuit is connected with the input end of the first inverter in parallel, the input end of the second stage fine adjustment circuit is connected with the output end of the first stage fine adjustment circuit in cascade, the output end of the second stage fine adjustment circuit is connected with the output end of the second inverter in parallel, the first stage fine adjustment circuit comprises a P2-MOS tube and an N2-MOS tube which are connected in parallel, and the second stage fine adjustment circuit comprises a P3-MOS tube and an N3-MOS tube which are connected in parallel.
Further, the method further comprises the following steps:
The duty ratio detector is electrically connected with the coarse adjustment mode completion detector and the fine adjustment mode completion detector and is used for transmitting rising edge signals from 0 to 1 or falling edge signals from 1 to 0 generated by an input clock signal to the coarse adjustment mode completion detector and the fine adjustment mode completion detector;
The coarse adjustment mode completion detector is used for detecting that the coarse adjustment mode is completed when the duty ratio detector detects that the input clock signal changes;
The fine adjustment mode completion detector is used for detecting that the fine adjustment mode is completed when the duty ratio detector detects that an input clock signal changes;
a counter of the coarse duty cycle corrector, wherein the counter of the coarse duty cycle corrector is electrically connected with the coarse mode completion detector and is used for generating a coarse 5bit code value;
A counter of the fine-tuning duty cycle corrector electrically connected to the fine-tuning mode completion detector for generating a fine-tuning 4bit code value;
Further, the first-stage coarse tuning circuit and the second-stage coarse tuning circuit are both built as inverters, and the first-stage fine tuning circuit and the second-stage fine tuning circuit are both built as inverters.
Further, the multi-stage coarse adjustment circuit can adjust the duty ratio of the input clock signal to a range of 40% -60%, the duty ratio of the actual output of the input clock signal to a range of 47.5% -52.5%, and the multi-stage fine adjustment circuit can adjust the duty ratio of the input clock signal to a range of 47% -53%, and the duty ratio of the actual output of the input clock signal to a range of 49% -51%.
Further, the P0-MOS tube, the P1-MOS tube, the N0-MOS tube and the N1-MOS tube all store 5-bit binary digits of <4:0>, and the P2-MOS tube, the P3-MOS tube, the N2-MOS tube and the N3-MOS tube all store 4-bit binary digits of <3:0 >.
Further, the duty cycle detector is a digital logic circuit built by a timing trigger circuit, a latch and a counter.
Further, the coarse mode completion detector and the fine mode completion detector are both integrated circuits of a digital logic circuit and a comparator circuit that detect duty cycles.
Further, the counter of the coarse duty cycle corrector and the counter of the fine duty cycle corrector are digital logic circuits built by a timing trigger circuit, a latch and the counter.
Compared with the prior art, the invention has the beneficial effects that:
According to the invention, the input end of the first-stage coarse tuning circuit is connected with the input end of the first inverter in parallel, the input end of the second-stage coarse tuning circuit is connected with the output end of the first-stage coarse tuning circuit in cascade, the output end of the second-stage coarse tuning circuit is connected with the output end of the second inverter in parallel, the input end of the first-stage fine tuning circuit is connected with the input end of the first inverter in parallel, the input end of the second-stage fine tuning circuit is connected with the output end of the first-stage fine tuning circuit in cascade, and the output end of the second-stage fine tuning circuit is connected with the output end of the second inverter in parallel. Therefore, the duty ratio of the whole clock signal can be adjusted in a mode of coarse adjustment and fine adjustment in parallel, the duty ratio of the clock signal is adjusted in a mode of coarse adjustment and fine adjustment, so that the larger range is realized, the higher precision is realized, the linearity is good, too much area and power consumption are not increased, and the duty ratio adjustment of the clock signal with different frequencies and characteristics can be adapted.
Drawings
FIG. 1 is a schematic diagram of the circuit connections of coarse and fine tuning units according to the present invention;
FIG. 2 is a control circuit diagram of duty cycle correction of the present invention;
FIG. 3 is a circuit diagram of a duty cycle corrector of the present invention;
FIG. 4 is a waveform diagram of a coarse duty cycle increase in accordance with the present invention;
FIG. 5 is a waveform diagram of a coarse duty cycle reduction of the present invention;
FIG. 6 is a waveform diagram of a fine-tuned duty cycle increase of the present invention;
fig. 7 is a waveform diagram of a fine-tuned duty cycle reduction of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples:
Referring to fig. 1 to 7, the present invention provides a technical solution:
A parallel coarse-fine tuning device in a single-ended analog duty cycle adjuster, as shown in fig. 1, comprising:
a main circuit for conducting when the duty ratio of an input clock signal does not need to be adjusted, the main circuit comprising a first inverter and a second inverter connected in series;
The multi-stage coarse tuning circuit is used for realizing the large-range adjustment of the duty ratio of an input clock signal, and comprises a first-stage coarse tuning circuit and a second-stage coarse tuning circuit, wherein the input end of the first-stage coarse tuning circuit is connected with the input end of a first inverter in parallel, the input end of the second-stage coarse tuning circuit is connected with the output end of the first-stage coarse tuning circuit in cascade, the output end of the second-stage coarse tuning circuit is connected with the output end of the second inverter in parallel, the first-stage coarse tuning circuit comprises a P0-MOS tube and an N0-MOS tube which are connected in parallel, and the second-stage coarse tuning circuit comprises a P1-MOS tube and an N1-MOS tube which are connected in parallel;
The multistage fine adjustment circuit is used for fine adjustment of the duty ratio of an input clock signal, the multistage fine adjustment circuit comprises a first stage fine adjustment circuit and a second stage fine adjustment circuit, the input end of the first stage fine adjustment circuit is connected with the input end of the first inverter in parallel, the input end of the second stage fine adjustment circuit is connected with the output end of the first stage fine adjustment circuit in cascade, the output end of the second stage fine adjustment circuit is connected with the output end of the second inverter in parallel, the first stage fine adjustment circuit comprises a P2-MOS tube and an N2-MOS tube which are connected in parallel, and the second stage fine adjustment circuit comprises a P3-MOS tube and an N3-MOS tube which are connected in parallel.
On the basis of the above embodiment, as shown in fig. 2, the method further includes:
The duty ratio detector is electrically connected with the coarse adjustment mode completion detector and the fine adjustment mode completion detector and is used for transmitting rising edge signals from 0 to 1 or falling edge signals from 1 to 0 generated by an input clock signal to the coarse adjustment mode completion detector and the fine adjustment mode completion detector;
The coarse adjustment mode completion detector is used for completing the coarse adjustment mode when the duty ratio detector detects the change of an input clock signal;
The fine adjustment mode completion detector is used for completing the fine adjustment mode when the duty ratio detector detects that an input clock signal changes;
a counter of the coarse duty cycle corrector, wherein the counter of the coarse duty cycle corrector is electrically connected with the coarse mode completion detector and is used for generating a coarse 5bit code value;
a counter of the fine-tuning duty cycle corrector, the counter of the fine-tuning duty cycle corrector being electrically connected to the fine-tuning mode completion detector for generating a coarse-tuning 4bit code value;
on the basis of the above embodiment, as shown in fig. 1, the first-stage coarse tuning circuit and the second-stage coarse tuning circuit are both built as inverters, and the first-stage fine tuning circuit and the second-stage fine tuning circuit are both built as inverters.
On the basis of the above embodiment, the multi-stage coarse adjustment circuit is capable of adjusting the duty ratio of the input clock signal to a range of 40% -60%, the duty ratio of the actual output of the input clock signal to a range of 47.5% -52.5%, and the multi-stage fine adjustment circuit is capable of adjusting the duty ratio of the input clock signal to a range of 47% -53%, and the duty ratio of the actual output of the input clock signal to a range of 49% -51%.
On the basis of the embodiment, the duty ratio detector is a digital logic circuit built by a timing trigger circuit, a latch and a counter, the duty ratio detector detects that the counter is reset during a low level period of a signal to be detected, the counter counts the signal during a high level period of the signal to be detected, the timing trigger circuit outputs a latch pulse when the signal to be detected falls, the count value of the counter is latched when the pulse rises, and the ratio of the duration of the high level to the whole period can be calculated by measuring the value in the counter, so that the duty ratio is obtained. The timing trigger circuit, the latch and the counter are all in the prior art, and can be written by referring to Yang Fengliang (design of pulse signal duty ratio measuring circuit and Proteus simulation).
On the basis of the above embodiment, the coarse mode completion detector and the fine mode completion detector may integrate a digital logic circuit for detecting a duty ratio with a comparator circuit, compare the calculated duty ratio with a set coarse or fine threshold, and trigger a coarse or fine mode completion state if the output of the counter satisfies the coarse or fine threshold. Because both the duty cycle detector and the comparator circuit are prior art, the coarse mode complete detector and the fine mode complete detector are prior art.
On the basis of the embodiment, the counter of the coarse duty cycle corrector and the counter of the fine duty cycle corrector are digital logic circuits built by a timing trigger circuit, a latch and a counter, and if the duty cycle is <50% initially, the duty cycle detector is 0, when the duty cycle is adjusted from less than 50% to more than 50%, the analog duty cycle detector generates a rising edge signal of 0 to 1, the signal is output to the analog DCC coarse tuning locking discriminator, the DCC locking discriminator is used for discriminating or discriminating that the input signal is the rising edge signal, the duty cycle at this time is in the increasing direction, and starts to work in the direction of the counter <4:0> = 00000= > 00001= >00011 of the duty cycle corrector until the output duty cycle detector detects the signal from 0 to 1, and then the counter of the duty cycle corrector stops to lock the duty cycle 5.
On the basis of the above embodiment, as shown in fig. 1, the P0-MOS, P1-MOS, N0-MOS and N1-MOS all store 5-bit binary digits of <4:0>, and the P2-MOS, P3-MOS, N2-MOS and N3-MOS all store 4-bit binary digits of <3:0 >.
Under the condition of forward bias, the current between the source electrode and the drain electrode of the P0-MOS tube, the P1-MOS tube, the P2-MOS tube and the P3-MOS tube can be blocked, namely in an off state. While in the negative bias case, current between the source and drain will flow, i.e., be in a conductive state. In contrast, the N0-MOS, the N1-MOS, the N2-MOS and the N3-MOS are opposite, and when the forward bias is carried out, the current between the source electrode and the drain electrode flows to be in a conducting state; while on negative bias, the current is blocked, off-state. Therefore, when the input of the first-stage coarse tuning circuit is high, the connection characteristic of the P0-MOS tube and the N0-MOS tube enables the output of the first-stage coarse tuning circuit to be low, the parallel connection of the P0-MOS tube and the N0-MOS tube is equivalent to the action of an inverter, namely the input level is opposite to the output level, and the parallel connection of the P1-MOS tube and the N1-MOS tube of the second-stage coarse tuning circuit is equivalent to the inverter, so that the low level output by the first-stage coarse tuning circuit can be converted into high level; similarly, when fine adjustment is performed, the P2-MOS tube and the N2-MOS tube of the first-stage fine adjustment circuit are connected in parallel to form an inverter, when the input is high level, the output is low level, and the P3-MOS tube and the N3-MOS tube of the second-stage fine adjustment circuit are connected in parallel to be equivalent to the inverter, so that the low level output by the first-stage fine adjustment circuit is converted into high level.
As shown in fig. 1 and 2, the analog control part, no matter the adjustment of less than 50% or more than 50%, has a DCC coarse tuning lock discriminator inside the analog circuit, if the duty ratio is <50% at the beginning, the duty ratio detector is 0 at this time, when the duty ratio is adjusted from less than 50% to more than 50%, the analog duty ratio detector generates a rising edge signal of 0 to 1, the signal is output to the analog DCC coarse tuning lock discriminator, the coarse tuning duty ratio starts to operate in the direction of increasing toward the counter <4:0> =00000= > 00001= >00011 of the coarse tuning duty ratio corrector until the output duty ratio >50%, that is, the duty ratio detector detects that the signal is from 0 to 1, and then the counter of the coarse tuning duty ratio corrector stops operating, thereby locking the coarse tuning 5bit code value, and displaying that the coarse tuning duty ratio is completed; also if the duty cycle is adjusted from greater than 50% to less than 50%, the simulated duty cycle detector will generate a1 to 0 falling edge signal that is output to the simulated DCC coarse lock discriminator, at which time the coarse duty cycle is reduced in a direction toward a decrease, toward the coarse duty cycle corrector counter <4:0> = 00000= > 00001= >00011, until the duty cycle detector detects a signal from 1 to 0, and then the coarse duty cycle corrector counter stops operating, thereby locking the coarse 5bit code value, indicating that the coarse duty cycle is complete.
The coarse adjustment of the duty ratio mainly realizes the large-scale adjustment of an input clock, the range of the duty ratio is 40% -60%, the duty ratio is divided into 5 grades, 5-bit binary digits of <4:0> are stored in a P0-MOS tube, an N0-MOS tube, a P1-MOS tube and an N1-MOS tube, 00000 is set as a default value, and any duty ratio is not adjusted. When the duty ratio of the input clock signal is smaller than <50%, the duty ratio corrector starts to adjust in a rough adjustment mode, and the proportion of the duty ratio of the input clock signal can be increased by 2.5% each time according to the requirement, namely when the 5-bit binary system is 00001, the proportion is increased by 2.5%; when the 5-bit binary is 00011, 5% increase; when the 5-bit binary is 00111, 7.5% increase; when the 5-bit binary is 01111, the increment is 10%; when the 5-bit binary is 11111, the increase is 12.5%. Similarly, if the duty ratio is more than 50%, the coarse adjustment of the duty ratio corrector starts to be adjusted, and the amplitude reduction is reduced by 2.5% each time, namely, when the 5-bit binary is 00001, the amplitude is reduced by 2.5%; when the 5-bit binary is 00011, the reduction is 5%; when the 5-bit binary is 00111, the reduction is 7.5%; when the 5-bit binary is 01111, the reduction is 10%, and when the 5-bit binary is 11111, the reduction is 12.5%.
As shown in fig. 1 and 2, the digital control part, whether there is an adjustment from less than 50% or more than 50%, has a DCC fine adjustment lock discriminator inside the digital circuit, if the duty ratio is <50% at the beginning, this time the duty ratio detector is 0, when the duty ratio is adjusted from less than 50% to more than 50%, the digital duty ratio detector will generate a rising edge signal of 0 to 1, this signal is output to the digital DCC fine adjustment lock discriminator, this time the fine adjustment duty ratio increases the duty ratio toward the direction of increase, toward the direction of the counter <3:0> = 0000= > 0001= >0011 of the fine adjustment duty ratio corrector, until the output duty ratio is >50%, that is, the duty ratio detector detects that the signal is from 0 to 1, then the counter of the fine adjustment duty ratio corrector stops working, thereby locking the value of the fine adjustment 4bit code, showing that the fine adjustment duty ratio is completed; also if the duty cycle is adjusted from greater than 50% to less than 50%, the digital duty cycle detector will generate a1 to 0 falling edge signal that is output to the digital DCC fine adjustment lock discriminator, at which point the fine-tuned duty cycle is in the decreasing direction, the counter of the fine-tuned duty cycle corrector <3:0> = 0000= > 0001= >0011 decreases the duty cycle until the output duty cycle <50%, i.e., the duty cycle detector detects that the signal is from 1 to 0, and then the counter of the fine-tuned duty cycle corrector stops working, locking the fine-tuned 4bit code value, indicating that the fine-tuned duty cycle is complete.
The duty ratio is finely adjusted, the input clock signal is finely adjusted, after the input clock signal passes through the rough adjustment duty ratio corrector, the duty ratio is finely adjusted, the duty ratio adjustment range is 47% -53%, then the 0000 is set as a default value through 4-gear fine adjustment control, any duty ratio is not adjusted, when the duty ratio of the input clock signal is smaller than <50%, the duty ratio corrector starts to adjust the duty ratio, and the duty ratio of the input clock signal is increased by 1% increment each time according to the requirement, namely, when 4-bit binary is 0001, 1% increment is added; when 4-bit binary is 0011, 2% increase; when the 4-bit binary is 0111, the increment is 3%; when the 4-bit binary is 1111, the increment is 4%; similarly, if the duty ratio is more than 50%, the duty ratio corrector starts to adjust the duty ratio by reducing the duty ratio by 1% each time, namely, when the 4-bit binary system is 0001, the duty ratio is reduced by 1%; when 4-bit binary is 0011, the reduction is 2%; when the 4-bit binary is 0111, the reduction is 3%; when the 4-bit binary is 1111, the reduction is 4%.
The working principle of the parallel coarse-fine adjustment device in the single-ended analog duty ratio adjuster is as follows:
first, the adjustment of the duty ratio of the circuit is divided into coarse adjustment and fine adjustment, and the adjustment of the duty ratio is that the coarse adjustment is performed before the fine adjustment.
As shown in FIG. 4, when the duty ratio of the input clock signal needs to be increased in a coarse adjustment, on one hand, the size of the N0-MOS tube is increased by increasing the size of the N0-MOS tube, so that the falling edge of the signal output by the first-stage coarse adjustment circuit from 1 to 0 is faster, namely the falling edge of the signal output by the first-stage coarse adjustment circuit is reduced, thereby increasing the width of the low-level signal, and the width of the high-level signal is increased after the increase of the width of the low-level signal passes through the second-stage coarse adjustment circuit, so that the purpose of increasing the duty ratio is achieved; on the other hand, the size of the P1-MOS tube can be increased, and the size of the P1-MOS tube is increased, so that the rising edge of the signal output by the second-stage coarse adjustment circuit can be directly reduced, the width of the high-level signal output by the second-stage coarse adjustment circuit is increased, and the duty ratio is increased.
Similarly, as shown in fig. 5, when the duty ratio of the input clock signal needs to be reduced, on one hand, the size of the P0-MOS transistor can be increased, and the size of the P0-MOS transistor is increased, so that the rising edge of the signal output by the first-stage coarse tuning circuit from 0to 1 is faster, that is, the rising edge of the signal output by the first-stage coarse tuning circuit is reduced, so that the width of the high-level signal is increased, and after passing through the second-stage coarse tuning circuit, the width of the low-level signal is increased, thereby achieving the purpose of reducing the duty ratio; on the other hand, the size of the N1-MOS tube can be increased, and the size of the N1-MOS tube is increased, so that the falling edge of the signal output by the second-stage coarse adjustment circuit can be directly reduced, the width of the low-level signal output by the second-stage coarse adjustment circuit is increased, and the duty ratio is reduced.
When the duty ratio of the input clock signal needs to be increased during fine adjustment, as shown in fig. 6, on one hand, the falling edge of the signal output by the first-stage fine adjustment circuit from 1 to 0 can be made faster by increasing the size of N2 and increasing the size of N2, that is, the falling edge of the signal output by the first-stage fine adjustment circuit is reduced, so that the width of the low-level signal is increased, and the width of the high-level signal is increased after the increase of the width of the low-level signal passes through the second-stage fine adjustment circuit, so that the purpose of increasing the duty ratio is achieved; on the other hand, the size of the P3-MOS tube can be increased, and the size of the P3-MOS tube is increased, so that the rising edge of the signal output by the second-stage fine-tuning circuit can be directly reduced, the width of the high-level signal output by the second-stage fine-tuning circuit is increased, and the duty ratio is increased.
Similarly, as shown in fig. 7, when the duty ratio of the input clock signal needs to be reduced, on one hand, the size of the P2-MOS transistor can be increased, and the size of the P2-MOS transistor is increased, so that the rising edge of the signal output by the first-stage fine adjustment circuit from 0 to 1 is faster, that is, the rising edge of the signal output by the first-stage fine adjustment circuit is reduced, thereby increasing the width of the high-level signal, and after the increase of the width of the high-level signal passes through the second-stage fine adjustment circuit, the width of the low-level signal is increased, thereby achieving the purpose of reducing the duty ratio; on the other hand, the size of the N3-MOS tube is increased, and the size of the N3-MOS tube is increased, so that the falling edge of the signal output by the second-stage fine-tuning circuit can be directly reduced, the width of the low-level signal output by the second-stage fine-tuning circuit is increased, and the duty ratio is reduced.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A parallel coarse-fine tuning device in a single-ended analog duty cycle adjuster, comprising:
a main circuit for conducting when the duty ratio of an input clock signal does not need to be adjusted, the main circuit comprising a first inverter and a second inverter connected in series;
The multi-stage coarse tuning circuit is used for realizing the large-range adjustment of the duty ratio of an input clock signal, and comprises a first-stage coarse tuning circuit and a second-stage coarse tuning circuit, wherein the input end of the first-stage coarse tuning circuit is connected with the input end of a first inverter in parallel, the input end of the second-stage coarse tuning circuit is connected with the output end of the first-stage coarse tuning circuit in cascade, the output end of the second-stage coarse tuning circuit is connected with the output end of the second inverter in parallel, the first-stage coarse tuning circuit comprises a P0-MOS tube and an N0-MOS tube which are connected in parallel, and the second-stage coarse tuning circuit comprises a P1-MOS tube and an N1-MOS tube which are connected in parallel;
The multistage fine adjustment circuit is used for fine adjustment of the duty ratio of an input clock signal, the multistage fine adjustment circuit comprises a first stage fine adjustment circuit and a second stage fine adjustment circuit, the input end of the first stage fine adjustment circuit is connected with the input end of the first inverter in parallel, the input end of the second stage fine adjustment circuit is connected with the output end of the first stage fine adjustment circuit in cascade, the output end of the second stage fine adjustment circuit is connected with the output end of the second inverter in parallel, the first stage fine adjustment circuit comprises a P2-MOS tube and an N2-MOS tube which are connected in parallel, and the second stage fine adjustment circuit comprises a P3-MOS tube and an N3-MOS tube which are connected in parallel.
2. A parallel coarse and fine tuning device in a single-ended analog duty cycle adjuster as recited in claim 1, further comprising:
The duty ratio detector is electrically connected with the coarse adjustment mode completion detector and the fine adjustment mode completion detector and is used for transmitting rising edge signals from 0 to 1 or falling edge signals from 1 to 0 generated by an input clock signal to the coarse adjustment mode completion detector and the fine adjustment mode completion detector;
The coarse adjustment mode completion detector is used for detecting that the coarse adjustment mode is completed when the duty ratio detector detects that the input clock signal changes;
The fine adjustment mode completion detector is used for detecting that the fine adjustment mode is completed when the duty ratio detector detects that an input clock signal changes;
a counter of the coarse duty cycle corrector, wherein the counter of the coarse duty cycle corrector is electrically connected with the coarse mode completion detector and is used for generating a coarse 5bit code value;
and the counter of the fine-tuning duty cycle corrector is electrically connected with the fine-tuning mode completion detector and is used for generating a fine-tuning 4bit code value.
3. A parallel coarse and fine tuning arrangement in a single-ended analog duty cycle adjuster according to claim 1, wherein the first and second coarse tuning circuits are each built as an inverter, and the first and second fine tuning circuits are each built as an inverter.
4. A parallel coarse and fine tuning device in a single-ended analog duty cycle adjuster according to claim 1, wherein the multi-stage coarse tuning circuit is capable of adjusting the duty cycle of the input clock signal to a range of 40% -60%, the duty cycle of the actual output of the input clock signal to a range of 47.5% -52.5%, and the multi-stage fine tuning circuit is capable of adjusting the duty cycle of the input clock signal to a range of 47% -53%, and the duty cycle of the actual output of the input clock signal to a range of 49% -51%.
5. The parallel coarse-fine tuning device in a single-ended analog duty cycle adjuster according to claim 1, wherein the P0-MOS tube, the P1-MOS tube, the N0-MOS tube, and the N1-MOS tube each store a 5-bit binary number of <4:0>, and the P2-MOS tube, the P3-MOS tube, the N2-MOS tube, and the N3-MOS tube each store a 4-bit binary number of <3:0 >.
6. A parallel coarse and fine tuning device in a single-ended analog duty cycle adjuster according to claim 2, wherein the duty cycle detector is a digital logic circuit built of a clocked flip-flop, a latch and a counter.
7. The apparatus of claim 6, wherein the coarse mode complete detector and the fine mode complete detector are integrated circuits of digital logic and comparator circuits for detecting duty cycles.
8. A parallel coarse and fine tuning device in a single-ended analog duty cycle adjuster according to claim 2, wherein the counter of the coarse and fine duty cycle rectifiers are digital logic circuits built from clocked flip-flop circuits, latches and counters.
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Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
| CN102412811A (en) * | 2012-01-06 | 2012-04-11 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
| CN105162435A (en) * | 2015-08-28 | 2015-12-16 | 西安启微迭仪半导体科技有限公司 | Clock duty cycle adjustment circuit with wide adjustment range |
| CN206686148U (en) * | 2017-03-02 | 2017-11-28 | 北京集创北方科技股份有限公司 | Dutycycle adjusting apparatus |
| CN107612529A (en) * | 2017-10-17 | 2018-01-19 | 中电科技集团重庆声光电有限公司 | A kind of clock duty cycle auto-adjusting circuit |
| CN108390672A (en) * | 2018-03-09 | 2018-08-10 | 电子科技大学 | A kind of method and apparatus for the digital oscillator frequency synthesis generating high precision clock |
| CN108832915A (en) * | 2018-09-13 | 2018-11-16 | 长江存储科技有限责任公司 | A kind of duty-ratio calibrating circuit |
| CN111030645A (en) * | 2019-11-29 | 2020-04-17 | 芯创智（北京）微电子有限公司 | Digital control wide-range clock duty ratio adjusting system |
| WO2020166645A1 (en) * | 2019-02-15 | 2020-08-20 | 株式会社ソシオネクスト | Digital phase synchronizing circuit, digitally-controlled oscillator, and digital-to-time converter |
| CN113841334A (en) * | 2019-04-08 | 2021-12-24 | 康杜实验室公司 | Measurement and correction of multiphase clock duty cycle and time offset |
| CN114598302A (en) * | 2022-03-16 | 2022-06-07 | 上海东软载波微电子有限公司 | Clock duty ratio calibrating device |
| CN115118252A (en) * | 2021-03-19 | 2022-09-27 | 爱普存储技术(杭州)有限公司 | Duty ratio correction device and duty ratio correction method |
| CN115361003A (en) * | 2022-08-15 | 2022-11-18 | 锐掣(杭州)科技有限公司 | Delay chain control circuit |
| CN115940631A (en) * | 2023-01-10 | 2023-04-07 | 中茵微电子(南京)有限公司 | Low ripple charge pump circuit |
| CN116388734A (en) * | 2023-03-28 | 2023-07-04 | 合芯科技有限公司 | Duty cycle adjusting circuit and system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7612592B2 (en) * | 2005-12-22 | 2009-11-03 | Agere Systems, Inc. | Programmable duty-cycle generator |
| US7944262B2 (en) * | 2008-05-21 | 2011-05-17 | Elpida Memory, Inc. | Duty correction circuit |
| KR20100135552A (en) * | 2009-06-17 | 2010-12-27 | 삼성전자주식회사 | Delay locked loop correcting duty of input clock and output clock |
| KR101331442B1 (en) * | 2012-06-29 | 2013-11-21 | 포항공과대학교 산학협력단 | Delay locked loop with a loop-embedded duty cycle corrector |
| US9954517B2 (en) * | 2012-11-06 | 2018-04-24 | Micron Technology, Inc. | Apparatuses and methods for duty cycle adjustment |
| JP2015012352A (en) * | 2013-06-27 | 2015-01-19 | マイクロン テクノロジー， インク． | Semiconductor device |
-
2023
- 2023-12-29 CN CN202311854344.4A patent/CN117498840B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
| CN102412811A (en) * | 2012-01-06 | 2012-04-11 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
| CN105162435A (en) * | 2015-08-28 | 2015-12-16 | 西安启微迭仪半导体科技有限公司 | Clock duty cycle adjustment circuit with wide adjustment range |
| CN206686148U (en) * | 2017-03-02 | 2017-11-28 | 北京集创北方科技股份有限公司 | Dutycycle adjusting apparatus |
| CN107612529A (en) * | 2017-10-17 | 2018-01-19 | 中电科技集团重庆声光电有限公司 | A kind of clock duty cycle auto-adjusting circuit |
| CN108390672A (en) * | 2018-03-09 | 2018-08-10 | 电子科技大学 | A kind of method and apparatus for the digital oscillator frequency synthesis generating high precision clock |
| CN108832915A (en) * | 2018-09-13 | 2018-11-16 | 长江存储科技有限责任公司 | A kind of duty-ratio calibrating circuit |
| WO2020166645A1 (en) * | 2019-02-15 | 2020-08-20 | 株式会社ソシオネクスト | Digital phase synchronizing circuit, digitally-controlled oscillator, and digital-to-time converter |
| CN113841334A (en) * | 2019-04-08 | 2021-12-24 | 康杜实验室公司 | Measurement and correction of multiphase clock duty cycle and time offset |
| CN111030645A (en) * | 2019-11-29 | 2020-04-17 | 芯创智（北京）微电子有限公司 | Digital control wide-range clock duty ratio adjusting system |
| CN115118252A (en) * | 2021-03-19 | 2022-09-27 | 爱普存储技术(杭州)有限公司 | Duty ratio correction device and duty ratio correction method |
| CN114598302A (en) * | 2022-03-16 | 2022-06-07 | 上海东软载波微电子有限公司 | Clock duty ratio calibrating device |
| CN115361003A (en) * | 2022-08-15 | 2022-11-18 | 锐掣(杭州)科技有限公司 | Delay chain control circuit |
| CN115940631A (en) * | 2023-01-10 | 2023-04-07 | 中茵微电子(南京)有限公司 | Low ripple charge pump circuit |
| CN116388734A (en) * | 2023-03-28 | 2023-07-04 | 合芯科技有限公司 | Duty cycle adjusting circuit and system |
Non-Patent Citations (1)
| Title |
|---|
| 张礼.《应用型基础物理实验教程》.南京东南大学出版社,2022,(第1版),140. * |
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