CN113054619A

CN113054619A - High-precision high-reliability undervoltage protection circuit for high-voltage gate driving chip

Info

Publication number: CN113054619A
Application number: CN202110347556.8A
Authority: CN
Inventors: 何宁业; 周云艳; 张燕飞; 许媛; 陈珍海; 宁仁霞
Original assignee: Huangshan University
Current assignee: Huangshan University
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-06-29

Abstract

The invention discloses a high-precision high-reliability undervoltage protection circuit for a high-voltage gate driving chip, which comprises: the circuit comprises a voltage detection circuit, a comparator circuit, a two-stage output shaping circuit and a power supply burr detection circuit. In order to overcome the serious influence of insufficient power supply voltage when a power supply module or a power grid is abnormal, the high-precision high-reliability under-voltage protection circuit provided by the invention adopts a two-stage comparator circuit with a reset function, and when a reset signal output by a power burr detection circuit is effective, the output signal of the comparator is cooperatively locked to further lock an under-voltage protection signal; on the other hand, the output shaping circuit adopts RC low-pass filtering and two-stage Schmitt trigger combined filtering to filter the influence of high-frequency noise and keep a certain hysteresis quantity, thereby generating a stable and reliable undervoltage protection output signal. The invention can be widely applied to various high-voltage gate driving chips.

Description

High-precision high-reliability undervoltage protection circuit for high-voltage gate driving chip

Technical Field

The invention relates to a high-precision high-reliability under-voltage protection circuit for a high-voltage gate driving chip, and belongs to the technical field of integrated circuits.

Background

Under the traction of emerging industries such as smart grids, mobile communication, new energy automobiles and the like, power electronic application systems require further improvement of efficiency, miniaturization and added functions of the systems, and particularly require trade-offs among size, quality, power and efficiency of system equipment, such as server power management, battery chargers and micro-inverters of solar farms. The new generation of power electronic complete machine system puts higher demands on the reliability, speed and intellectualization of an internal High Voltage Integrated Circuit (HVIC), thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system. The high-voltage integrated circuit is used as a bridge of a system signal processing part and an execution part, integrates a high-voltage power device with a control circuit, a peripheral interface circuit, a protection circuit and the like, and needs to realize high-voltage and low-voltage compatibility, high performance, high efficiency and high reliability on a limited chip area in a power integration technology.

Because the high-voltage circuit control object is usually a high-power semiconductor device, a system control signal needs to be quickly turned off when the whole system is abnormal, and various protection circuits such as over-temperature protection, under-voltage protection, over-voltage protection and the like need to be integrated in the high-voltage integrated circuit. The undervoltage protection circuit is a commonly used protection function circuit for a high-voltage integrated circuit, and when the power supply voltage is lower than a set threshold, the system is turned off, and the undervoltage protection circuit is required to output an undervoltage protection signal for the control unit to perform power supply logic judgment protection. The stable working power supply is an indispensable condition for ensuring the reliable operation of the high-voltage integrated circuit. When the power supply module or the power grid is abnormal, the corresponding circuit system also works abnormally, and particularly, when each functional module of a circuit board of an electronic product works at the minimum working power supply voltage value, although the circuit of the functional module cannot be damaged, the circuit system cannot stably run at the moment, so that the problems of abnormal logic control, data processing errors and the like of the system occur, and the problems can bring serious loss to the equipment running field. In addition, the high-voltage integrated circuit system works in a lower power supply voltage environment for a long time, and can cause adverse effects on the circuit, so that the efficiency is reduced, and the service life is greatly reduced.

Fig. 1 shows a high-voltage gate driving chip commonly used in power electronic application systems, which is a typical high-voltage half-bridge gate driving chip and application circuit. The typical half-bridge driving circuit is divided into a high-side channel driving circuit and a low-side channel driving circuit, the high-side driving circuit adopts a bootstrap boosting mode to realize signal transmission control, and two low-voltage inputs HI and LI enter the high-side channel and the low-side channel respectively. During the period that the low side LI inputs the high level, the LO outputs the high level, the switch ML is turned on, the switch node SW is pulled down to the ground, and at the moment, the HB point voltage charges the bootstrap capacitor through the bootstrap diode, so that the voltage difference between the two ends of the bootstrap capacitor is close to the chip power supply voltage VDD. During the period when the high side HI is input to high, HO outputs high, the high side MH is turned on, and the switch node voltage rises to VH, i.e., SW rises to VH. Since the voltage across the bootstrap capacitor is constant, the bootstrap voltage VHB is bootstrapped to SW + VDD. The high-side circuit always keeps VHB-SW ≈ VDD, SW swings between 0 and VH, which causes huge fluctuation of the high-side circuit power voltage (namely HB point voltage) and the substrate potential, and very serious common mode noise is generated. Therefore, various protection circuits used in the high-voltage gate driving chip need to realize high-reliability work under severe environmental factors such as voltage swing fluctuation, large substrate noise and the like, and provide high-precision chip state monitoring and protection functions.

Disclosure of Invention

Aiming at the system application requirements of a high-voltage grid driving chip, the invention provides a high-reliability undervoltage protection circuit which can realize high-precision monitoring and protection of the power supply voltage of the chip in the environment with voltage swing fluctuation and severe substrate noise.

According to the technical scheme provided by the invention, the high-precision high-reliability undervoltage protection circuit for the high-voltage gate driving chip comprises: the circuit comprises a voltage detection circuit, a comparator circuit, a two-stage output shaping circuit and a power supply burr detection circuit;

the voltage detection circuit generates a detection signal Vin according to the chip power supply voltage VDD and outputs the detection signal Vin to the comparator circuit; the comparator circuit compares a reference voltage signal Vref with a power supply voltage detection signal Vin to obtain a comparator output signal Vo1, and outputs the comparator output signal Vo1 to the two-stage output shaping circuit; the two-stage output shaping circuit shapes the comparator output signal Vo1 to obtain an under-voltage protection signal UVLock, the under-voltage protection signal UVLock is connected to the input end of the voltage detection circuit, the UVLock is a digital logic signal and is used for controlling the magnitude of the power supply voltage detection signal Vin, and the under-voltage protection signal UVLock is also used as a control signal to be output to other circuit modules of the high-voltage integrated circuit; the power supply burr detection circuit amplifies a power supply voltage burr signal through a two-stage input amplifier, and then converts the amplified signal into digital logic signals VC1 and VC2 through shaping of a Schmitt trigger, a third-stage inverter and a fourth-stage inverter, the signal VC1 is connected to the voltage detection circuit and the comparator circuit, the signal VC2 is connected to the comparator circuit and the two-stage output shaping circuit, the signal VC1 and the signal VC2 are opposite-phase signals and are used for controlling and assisting the voltage detection circuit, the comparator circuit and the two-stage output shaping circuit to generate a more reliable undervoltage protection signal UVLock; the voltage detection circuit is connected with a chip power supply voltage VDD, the comparator circuit and the two-stage output shaping circuit are both connected with an internal low-voltage power supply VCCL, and the power burr detection circuit is simultaneously connected with the chip power supply voltage VDD and the internal low-voltage power supply VCCL; the internal low-voltage power supply VCCL is generated by a chip power supply voltage VDD through a voltage reduction circuit;

when the power supply voltage of the chip is normal, a power supply burr detection circuit outputs a signal VC1 with a high level, a signal VC2 with a low level, the circuit works normally, an under-voltage protection signal UVLock is at a low level, and the UVLock low level controls the voltage detection circuit to generate a higher power supply voltage detection signal Vin;

when the power voltage of the chip is abnormal, the undervoltage protection signal UVLock is changed into a high-level logic signal, the high level of the UVLock controls the voltage detection circuit to generate a lower power voltage detection signal Vin, and the locking signal Vo1 is a high-level signal; at this time, the output signal VC1 of the glitch detection circuit is low, and VC2 is high, which further cooperate with the UVLock to be high.

Specifically, the power supply burr detection circuit comprises an input amplification circuit, a Schmitt trigger, a third-stage phase inverter and a fourth-stage phase inverter which are sequentially connected; the input amplification circuit consists of two stages of amplification circuits, the input end of the input amplification circuit is respectively connected to the output nodes of a second bias voltage signal Vb2, a third bias voltage signal Vb3 and a fourth bias voltage signal Vb4, the output end of the third-stage inverter outputs a signal VC1, and the signal VC1 enters the fourth-stage inverter to be inverted and then outputs a signal VC 2.

Specifically, the input amplification circuit includes: a PMOS tube M41, a PMOS tube M42, an NMOS tube M43, a PMOS tube M44, an NMOS tube M45, a PMOS tube M46, a resistor R41, a capacitor C41, a resistor R42 and a capacitor C42; the Schmitt trigger includes: the transistor is composed of a PMOS tube M47, a PMOS tube M48, an NMOS tube M49, an NMOS tube M410, a PMOS tube M411 and an NMOS tube M412; the third-stage phase inverter consists of a PMOS tube M413 and an NMOS tube M414; the fourth-stage inverter consists of a PMOS tube M415 and an NMOS tube M416;

the grid electrode of the PMOS tube M41 is connected to the output node of the second bias voltage signal Vb2, the source electrode of the PMOS tube M41 is connected with the power supply voltage VDD, the drain electrode of the PMOS tube M41 is connected with the source electrode of the PMOS tube M42, the grid electrode of the PMOS tube M42 is connected to the output node of the third bias voltage signal Vb3, and the drain electrode of the PMOS tube M42 is connected with the drain electrode and the grid electrode of the NMOS tube M43 and the grid electrode of the NMOS tube M45; the source electrode of the NMOS transistor M43, the source electrode of the NMOS transistor M45, the lower end of the resistor R42, the lower end of the capacitor C42, the source electrode of the NMOS transistor M410, the source electrode of the PMOS transistor M411, the source electrode of the NMOS transistor M414 and the source electrode of the NMOS transistor M416 are simultaneously connected to the ground voltage GND; the grid electrode of the PMOS tube M44 is connected to the output node of the fourth bias voltage signal Vb4, the source electrode of the PMOS tube M44 is connected with the lower end of the resistor R41, the lower end of the capacitor C41 and the grid electrode of the PMOS tube M46, and the drain electrode of the PMOS tube M44 is connected with the drain electrode of the NMOS tube M45; the source electrode of the PMOS tube M46, the upper end of the resistor R41, the upper end of the capacitor C41, the source electrode of the PMOS tube M47, the source electrode of the NMOS tube M412, the source electrode of the PMOS tube M413 and the source electrode of the PMOS tube M415 are simultaneously connected to an internal low-voltage power supply VCCL; the drain of the PMOS tube M46 is connected to the upper end of a resistor R42, the upper end of a capacitor C42, the gate of the PMOS tube M47, the gate of the PMOS tube M48, the gate of the NMOS tube M49 and the gate of the NMOS tube M410; the drain electrode of the PMOS tube M47 is connected with the source electrode of the PMOS tube M48 and the drain electrode of the PMOS tube M411; the drain electrode of the PMOS tube M48 is connected with the drain electrode of the NMOS tube M49, the grid electrode of the PMOS tube M411, the grid electrode of the NMOS tube M412, the grid electrode of the PMOS tube M413 and the grid electrode of the NMOS tube M414; the source electrode of the NMOS tube M49 is connected with the drain electrode of the NMOS tube M410 and the drain electrode of the NMOS tube M412; the drain electrode of the PMOS tube M413 is connected to the drain electrode of the NMOS tube M414, the grid electrode of the PMOS tube M415 and the grid electrode of the NMOS tube M416 and is used as an output node of a signal VC1 of the power supply glitch detection circuit; the drain electrode of the PMOS tube M415 is connected with the drain electrode of the NMOS tube M416 and is used as an output node of a signal VC2 of the power supply glitch detection circuit;

the first stage of the input amplifying circuit is a cascode amplifying circuit formed by a PMOS (P-channel metal oxide semiconductor) tube M44 and an NMOS (N-channel metal oxide semiconductor) tube M45, and the second stage of the input amplifying circuit is a common source amplifying circuit formed by a PMOS tube M46 and used for amplifying a fluctuation signal of a power supply voltage VDD; the resistor R41, the capacitor C41, the resistor R42 and the capacitor C42 in the circuit are mainly used for filtering high-frequency interference.

Specifically, the voltage detection circuit includes: a PMOS tube M11, an NMOS tube M12, a resistor R11, a resistor R12 and a resistor R13; the source of a PMOS tube M11 is connected to a power supply voltage VDD, the gate of the PMOS tube M11 is connected to a signal VC1 output by the power supply burr detection circuit, the drain of the PMOS tube M11 is connected to the upper end of a resistor R11, the source of an NMOS tube M12 is connected to the lower end of a resistor R13 and is simultaneously connected to a ground voltage GND, the gate of an NMOS tube M12 is connected to an undervoltage protection signal UVLock, the drain of an NMOS tube M12 is connected to the lower end of a resistor R12 and is simultaneously connected to the upper end of a resistor R13, and the lower end of the resistor R11 is connected to the upper end of the resistor R12 and serves as a detection signal Vin output node.

Specifically, the comparator circuit includes: a PMOS tube M21, an NMOS tube M22, a PMOS tube M23, a PMOS tube M24, an NMOS tube M25, a PMOS tube M26, a PMOS tube M27, a PMOS tube M28, an NMOS tube M29, an NMOS tube M210, an NMOS tube M211, an NMOS tube M212, a PMOS tube M213, an NMOS tube M214, a resistor R21 and a capacitor C21;

the connection relationship of the circuit is as follows: the grid electrode of the PMOS tube M21 is connected to the output node of the first bias voltage signal Vb1, the drain electrode of the PMOS tube M21 is connected with the drain electrode of the NMOS tube M22 and the grid electrode of the NMOS tube M25, and the source electrode of the PMOS tube M21, the source electrode of the PMOS tube M23, the source electrode of the PMOS tube M24, the source electrode of the PMOS tube M26 and the source electrode of the PMOS tube M213 are commonly connected to an internal low-voltage power supply VCCL; the grid electrode of the NMOS tube M22, the grid electrode of the NMOS tube M29 and the grid electrode of the NMOS tube M212 are simultaneously connected to a signal VC2 output by the power supply glitch detection circuit; the source electrode of the NMOS transistor M22, the source electrode of the NMOS transistor M25, the source electrode of the NMOS transistor M29, the source electrode of the NMOS transistor M210, the source electrode of the NMOS transistor M211, the source electrode of the NMOS transistor M212, the source electrode of the NMOS transistor M214, the lower end of the resistor R21 and the lower end of the capacitor C21 are connected to the ground voltage GND in common; the grid electrode of the PMOS pipe M23 is connected to a signal VC1 output by the power supply burr detection circuit; the drain electrode of the PMOS tube M23 is connected to the grid electrode and the drain electrode of the PMOS tube M24, the drain electrode of the NMOS tube M25, the grid electrode of the PMOS tube M26 and the grid electrode of the PMOS tube M213; the drain electrode of the PMOS tube M26 is connected with the source electrode of the PMOS tube M27 and the source electrode of the PMOS tube M28; the grid electrode of the PMOS tube M27 is connected with a reference voltage signal Vref; the drain electrode of the PMOS tube M27 is connected to the drain electrode of the NMOS tube M29, the drain electrode and the grid electrode of the NMOS tube M210 and the grid electrode of the NMOS tube M211; the grid electrode of the PMOS tube M28 is connected with the detection signal Vin output by the voltage detection circuit, the drain electrode of the PMOS tube M28 is connected with the drain electrode of the NMOS tube M211, the drain electrode of the NMOS tube M212 and the grid electrode of the NMOS tube M214, and the drain electrode of the PMOS tube M213 is connected with the drain electrode of the NMOS tube M214, the upper end of the resistor R21 and the upper end of the capacitor C21 and serves as an output node of an output signal Vo1 of the comparator circuit.

Specifically, the two-stage output shaping circuit includes: a PMOS tube M31, a PMOS tube M32, an NMOS tube M33, an NMOS tube M34, a PMOS tube M35, an NMOS tube M36, a PMOS tube M37, an NMOS tube M38, an NMOS tube M39, a PMOS tube M310, an NMOS tube M311, a PMOS tube M312, an NMOS tube M313, a PMOS tube M314, a PMOS tube M315, an NMOS tube M316, an NMOS tube M317, a PMOS tube M318, an NMOS tube M319, a PMOS tube M320, an NMOS tube M321, a PMOS tube M322, an NMOS tube M323, a resistor R31, a resistor R32 and a capacitor C31;

the grid of the PMOS transistor M31, the grid of the PMOS transistor M32, the grid of the NMOS transistor M33, and the grid of the NMOS transistor M34 are commonly connected to the signal Vo1 output by the comparator circuit, the source of the PMOS transistor M31, the source of the NMOS transistor M36, the source of the PMOS transistor M37, the source of the PMOS transistor M310, the source of the PMOS transistor M312, the source of the PMOS transistor M314, the source of the NMOS transistor M319, the source of the PMOS transistor M320, and the source of the PMOS transistor M322 are commonly connected to the internal low voltage power supply VCCL, the drain of the PMOS transistor M31 is connected to the source of the PMOS transistor M32 and the drain of the PMOS transistor M35, the drain of the PMOS transistor M32 is connected to the drain of the NMOS transistor M33, the grid of the PMOS transistor M35, the grid of the NMOS transistor M36, the grid of the PMOS transistor M37, and the grid; the source electrode of the NMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the drain electrode of the NMOS tube M36; the source of the NMOS transistor M34, the source of the PMOS transistor M35, the source of the NMOS transistor M38, the source of the NMOS transistor M39, the source of the NMOS transistor M311, the source of the NMOS transistor M313, the source of the NMOS transistor M317, the source of the PMOS transistor M318, the source of the NMOS transistor M321, the source of the NMOS transistor M323, and the lower end of the capacitor C31 are commonly connected to a ground voltage GND, the drain of the PMOS transistor M37 is connected to the drain of the NMOS transistor M38, the drain of the NMOS transistor M39, the gate of the PMOS transistor M310, the gate of the NMOS transistor M311, the gate of the NMOS transistor M39 is connected to a signal VC2 output by the power supply glitch detection circuit, the drain of the PMOS transistor M310 is connected to the drain of the NMOS transistor M311, the gate of the NMOS transistor M312 and the gate of the NMOS transistor M313, the drain of the PMOS transistor M312 is connected to the upper end of a resistor R31, the lower end of the resistor R31 is connected to the upper end of the resistor R32, the upper end of the capacitor C31, the gate of the PMOS transistor M314, the gate of the PMOS transistor M317, the gate, The drain electrode of the PMOS tube M318, the drain electrode of the PMOS tube M315 is connected with the drain electrode of the NMOS tube M316, the grid electrode of the PMOS tube M318, the grid electrode of the NMOS tube M319, the grid electrode of the PMOS tube M320 and the grid electrode of the NMOS tube M321, the source electrode of the NMOS tube M316 is connected with the drain electrode of the NMOS tube M317 and the drain electrode of the NMOS tube M319, and the drain electrode of the PMOS tube M320 is connected with the drain electrode of the NMOS tube M321, the grid electrode of the PMOS tube M322 and the grid electrode of the NMOS tube M323; the drain electrode of the PMOS tube M322 is connected with the drain electrode of the NMOS tube M323 and is used as an output node of an undervoltage protection signal UVLock of the two-stage output shaping circuit.

The invention has the advantages that: in order to overcome the serious influence of insufficient power supply voltage when a power supply module or a power grid is abnormal, the high-precision high-reliability under-voltage protection circuit provided by the invention adopts a two-stage comparator circuit with a reset function, and when a reset signal output by a power burr detection circuit is effective, the output signal of the comparator can be cooperatively locked to further lock an under-voltage protection signal; on the other hand, the output shaping circuit adopts RC low-pass filtering and two-stage Schmitt trigger combined filtering to filter the influence of high-frequency noise and keep a certain hysteresis quantity, thereby generating a stable and reliable undervoltage protection output signal.

Drawings

Fig. 1 is a circuit diagram of a typical half-bridge gate driving circuit and an application system.

Fig. 2 is a block diagram of the high-precision high-reliability under-voltage protection circuit of the present invention.

FIG. 3 is a diagram of an embodiment of a voltage detection circuit according to the invention.

Fig. 4 shows an embodiment of the comparator circuit of the present invention.

Fig. 5 is a diagram of an embodiment of a two-stage output shaping circuit according to the present invention.

Fig. 6 shows an embodiment of a power glitch detection circuit of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

As shown in fig. 2, the circuit configuration of the present invention includes a voltage detection circuit 1, a comparator circuit 2, a two-stage output shaping circuit 3, and a power supply glitch detection circuit 4. The voltage detection circuit 1 is used for obtaining a detection signal Vin of a power supply voltage VDD and outputting the detection signal Vin to the comparator circuit 2; the comparator circuit 2 compares the reference voltage signal Vref with the power supply voltage detection signal Vin to obtain a comparator output signal Vo1, and outputs the comparator output signal Vo1 to the two-stage output shaping circuit 3; the two-stage output shaping circuit 3 carries out shaping processing on the comparator output signal Vo1 to obtain an under-voltage protection signal UVLock, the UVLock is a digital logic signal, the UVLock is connected to the input end of the voltage detection circuit 1 again and used for controlling the magnitude of the power supply voltage detection signal Vin, and the UVLock is also used as a control signal to be output to other circuit modules of the high-voltage integrated circuit.

The power burr detection circuit 4 comprises an input amplification circuit, a Schmitt trigger, a third-stage phase inverter and a fourth-stage phase inverter which are sequentially connected; the input amplification circuit consists of two stages of amplification circuits, the input end of the input amplification circuit is respectively connected to the output nodes of a second bias voltage signal Vb2, a third bias voltage signal Vb3 and a fourth bias voltage signal Vb4, the output end of the third-stage inverter outputs a signal VC1, and the signal VC1 enters the fourth-stage inverter to be inverted and then outputs a signal VC 2. The power supply burr detection circuit 4 amplifies a power supply voltage burr signal through a two-stage input amplifier, and then converts the amplified signal into digital logic signals VC1 and VC2 through shaping of a Schmitt trigger, a third-stage inverter and a fourth-stage inverter, wherein the signal VC1 is connected to the voltage detection circuit 1 and the comparator circuit 2, and the signal VC2 is connected to the comparator circuit 2 and the two-stage output shaping circuit 3. The signal VC1 and the signal VC2 are inverted signals, and are used to control and assist the voltage detection circuit 1, the comparator circuit 2 and the two-stage output shaping circuit 3 to generate a more reliable under-voltage protection signal UVLock.

The voltage detection circuit 1 adopts a chip power supply voltage VDD, the comparator circuit 2 and the two-stage output shaping circuit 3 both adopt an internal low-voltage power supply VCCL, and the power burr detection circuit 4 adopts the chip power supply voltage VDD and the internal low-voltage power supply VCCL at the same time. The internal low-voltage power supply VCCL is generated from the chip power supply voltage VDD through a voltage-reducing circuit, and is generally a voltage not higher than the chip power supply voltage VDD.

When the power supply voltage of the chip is normal, the output signal VC1 of the power supply burr detection circuit 4 is at a high level, VC2 is at a low level, the under-voltage protection signal UVLock is at a low level, and the UVLock low level controls the voltage detection circuit 1 to generate a higher power supply voltage detection signal Vin; the comparator output signal Vo1 obtained by the comparator circuit 2 according to the reference voltage Vref and the power supply voltage detection signal Vin should be a high level signal in a normal case; the two-stage output shaping circuit 3 processes the comparator output signal Vo1 to obtain an undervoltage protection signal UVLock which is a low-level logic signal.

When the power voltage of the chip is abnormal, the power voltage detection signal Vin detected by the voltage detection circuit 1 will change, the comparator output signal Vo1 obtained by the comparator circuit 2 according to the reference voltage Vref and the power voltage detection signal Vin becomes a low-level signal, the undervoltage protection signal UVLock obtained by the two-stage output shaping circuit 3 is changed into a high-level logic signal, the high-level UVLock controls the voltage detection circuit 1 to generate a lower power voltage detection signal Vin, and the voltage Vin will lock the comparator output signal Vo1 of the comparator circuit 2 into a high-level signal. At this time, the output signal VC1 of the glitch detection circuit 4 is low, and VC2 is high, which further cooperate with the UVLock to be high.

When the power supply module or the power grid is abnormal, the power supply voltage may be insufficient, and the normal operation of the high-voltage integrated circuit is seriously influenced. In order to overcome the serious influence caused by the power supply undervoltage, on one hand, a two-stage comparator circuit 2 with a reset function is adopted, and when reset signals VC1 and VC2 output by a power supply burr detection circuit 4 are effective, the output signal Vo1 of the comparator is cooperatively locked, and an undervoltage protection signal UVLock is further locked; on the other hand, the output shaping circuit adopts RC low-pass filtering and two-stage Schmitt trigger combined filtering to filter the influence of high-frequency noise, and a certain hysteresis quantity is kept, so that a stable and reliable undervoltage protection signal UVLock is generated.

Fig. 3 is an implementation of the voltage detection circuit 1 of the present invention, which is composed of a PMOS transistor M11, an NMOS transistor M12, a resistor R11, a resistor R12, and a resistor R13; the source of the PMOS transistor M11 is connected to the power voltage VDD, the gate of the PMOS transistor M11 is connected to the signal VC1 output by the power glitch detection circuit 4, the drain of the PMOS transistor M11 is connected to the upper end of the resistor R11, the source of the NMOS transistor M12 is connected to the lower end of the resistor R13 and simultaneously connected to the ground voltage GND, the gate of the NMOS transistor M12 is connected to the undervoltage protection signal UVLock, the drain of the NMOS transistor M12 is connected to the lower end of the resistor R12 and simultaneously connected to the upper end of the resistor R13, and the lower end of the resistor R11 is connected to the upper end of the resistor R12 and serves as the detection signal Vin output node of the voltage detection circuit.

In the voltage detection circuit 1 of fig. 3, the power voltage VDD is detected by voltage dividing resistors R11, R12 and R13 in real time, the voltage value Vin obtained by voltage dividing is input to the comparator circuit 2, the resistance value of R13 is controlled by M12, and the on and off of M12 are controlled by the undervoltage protection signal UVLock signal. When the UVLock signal is at a low level, the gate of M12 is low, M12 is in an off state, R13 is a large resistor, and the voltage value Vin obtained by voltage division is a higher output voltage Vin _ h; when the UVLock signal is at a low level, the gate of M12 is high, M12 is in a conducting state, R13 is shorted by M13 to be a small resistor, and the voltage value Vin obtained by voltage division is a lower output voltage Vin _ l. M11 is controlled by a control signal VC1 of the output of the power glitch detection circuit 4. When VC1 is at high level, M11 is conducted, the voltage detection circuit 1 works normally, and the detection voltage Vin is output; when VC1 is low, M11 turns off and turns off the entire voltage detection circuit 1.

Fig. 4 is an implementation manner of the comparator circuit 2 of the present invention, and the circuit is composed of a PMOS transistor M21, an NMOS transistor M22, a PMOS transistor M23, a PMOS transistor M24, an NMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27, a PMOS transistor M28, an NMOS transistor M29, an NMOS transistor M210, an NMOS transistor M211, an NMOS transistor M212, a PMOS transistor M213, an NMOS transistor M214, a resistor R21, and a capacitor C21. The grid electrode of the PMOS tube M21 is connected to the output node of the first bias voltage signal Vb1, the drain electrode of the PMOS tube M21 is connected with the drain electrode of the NMOS tube M22 and the grid electrode of the NMOS tube M25, and the source electrode of the PMOS tube M21, the source electrode of the PMOS tube M23, the source electrode of the PMOS tube M24, the source electrode of the PMOS tube M26 and the source electrode of the PMOS tube M213 are commonly connected to an internal low-voltage power supply VCCL; the grid electrode of the NMOS tube M22, the grid electrode of the NMOS tube M29 and the grid electrode of the NMOS tube M212 are simultaneously connected to a signal VC2 output by the power supply glitch detection circuit 4; the source electrode of the NMOS transistor M22, the source electrode of the NMOS transistor M25, the source electrode of the NMOS transistor M29, the source electrode of the NMOS transistor M210, the source electrode of the NMOS transistor M211, the source electrode of the NMOS transistor M212, the source electrode of the NMOS transistor M214, the lower end of the resistor R21 and the lower end of the capacitor C21 are connected to the ground voltage GND in common; the grid electrode of the PMOS pipe M23 is connected to a signal VC1 output by the power supply burr detection circuit 4; the drain electrode of the PMOS tube M23 is connected to the grid electrode and the drain electrode of the PMOS tube M24, the drain electrode of the NMOS tube M25, the grid electrode of the PMOS tube M26 and the grid electrode of the PMOS tube M213; the drain electrode of the PMOS tube M26 is connected with the source electrode of the PMOS tube M27 and the source electrode of the PMOS tube M28; the grid electrode of the PMOS tube M27 is connected with a reference voltage signal Vref; the drain electrode of the PMOS tube M27 is connected to the drain electrode of the NMOS tube M29, the drain electrode and the grid electrode of the NMOS tube M210 and the grid electrode of the NMOS tube M211; the gate of the PMOS transistor M28 is connected to the detection signal Vin output by the voltage detection circuit 1, the drain of the PMOS transistor M28 is connected to the drain of the NMOS transistor M211, the drain of the NMOS transistor M212, and the gate of the NMOS transistor M214, and the drain of the PMOS transistor M213 is connected to the drain of the NMOS transistor M214, the upper end of the resistor R21, and the upper end of the capacitor C21, and serves as the output node of the output signal Vo1 of the comparator circuit 2.

The comparator circuit 2 shown in fig. 4 is composed of a first-stage comparator with a reset function and a second-stage common-source amplifier. The PMOS tube M26, the PMOS tube M27, the PMOS tube M28, the NMOS tube M29, the NMOS tube M210, the NMOS tube M211 and the NMOS tube M212 form a first-stage comparator with a reset function, and the PMOS tube M213 and the NMOS tube M214 form a second-stage common-source amplifier.

When the output signal VC1 of the power glitch detection circuit 4 is high and VC2 is low, the comparator circuit 2 operates normally: if the input voltage Vin is greater than the reference voltage Vref, the output of the first-stage comparator circuit 2 is at a low level, and the output Vo1 is at a high level; if the input voltage Vin is smaller than the reference voltage Vref, i.e. under-voltage state, the output of the first stage comparator circuit 2 is at high level, and the output Vo1 is at low level. When the output signal VC1 of the power glitch detection circuit 4 is low and VC2 is high, the single-ended output signal of the first-stage comparator circuit 2 is pulled low to low, and the second-stage amplifier output Vo1 is locked to high.

Fig. 5 is an implementation manner of the two-stage output shaping circuit 3 of the present invention, and the circuit is composed of a PMOS transistor M31, a PMOS transistor M32, an NMOS transistor M33, an NMOS transistor M34, a PMOS transistor M35, an NMOS transistor M36, a PMOS transistor M37, an NMOS transistor M38, an NMOS transistor M39, a PMOS transistor M310, an NMOS transistor M311, a PMOS transistor M312, an NMOS transistor M313, a PMOS transistor M314, a PMOS transistor M315, an NMOS transistor M316, an NMOS transistor M317, a PMOS transistor M318, an NMOS transistor M319, a PMOS transistor M320, an NMOS transistor M321, a PMOS transistor M322, an NMOS transistor M323, a resistor R31, a resistor R32, and a capacitor C31. The grid of the PMOS transistor M31, the grid of the PMOS transistor M32, the grid of the NMOS transistor M33, and the grid of the NMOS transistor M34 are commonly connected to the signal Vo1 output by the comparator circuit 2, the source of the PMOS transistor M31, the source of the NMOS transistor M36, the source of the PMOS transistor M37, the source of the PMOS transistor M310, the source of the PMOS transistor M312, the source of the PMOS transistor M314, the source of the NMOS transistor M319, the source of the PMOS transistor M320, and the source of the PMOS transistor M322 are commonly connected to the internal low voltage power supply VCCL, the drain of the PMOS transistor M31 is connected to the source of the PMOS transistor M32 and the drain of the PMOS transistor M35, and the drain of the PMOS transistor M32 is connected to the drain of the NMOS transistor M33, the grid of the PMOS transistor M35, the grid of the NMOS transistor M36, the grid of the PMOS transistor M37, and the; the source electrode of the NMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the drain electrode of the NMOS tube M36; the source of the NMOS transistor M34, the source of the PMOS transistor M35, the source of the NMOS transistor M38, the source of the NMOS transistor M39, the source of the NMOS transistor M311, the source of the NMOS transistor M313, the source of the NMOS transistor M317, the source of the PMOS transistor M318, the source of the NMOS transistor M321, the source of the NMOS transistor M323, and the lower end of the capacitor C31 are commonly connected to a ground voltage GND, the drain of the PMOS transistor M37 is connected to the drain of the NMOS transistor M38, the drain of the NMOS transistor M39, the gate of the PMOS transistor M310, the gate of the NMOS transistor M311, the gate of the NMOS transistor M39 is connected to the signal VC2 output by the power supply glitch detection circuit 4, the drain of the PMOS transistor M310 is connected to the drain of the NMOS transistor M311, the gate of the NMOS transistor M312 and the gate of the NMOS transistor M313, the drain of the PMOS transistor M312 is connected to the upper end of the resistor R31, the lower end of the resistor R32, the upper end of the capacitor C31, the gate of the PMOS transistor M314, the gate of the PMOS transistor M317, the gate of the PMOS transistor M315, the drain of the NMOS transistor, The drain electrode of the PMOS tube M318, the drain electrode of the PMOS tube M315 is connected with the drain electrode of the NMOS tube M316, the grid electrode of the PMOS tube M318, the grid electrode of the NMOS tube M319, the grid electrode of the PMOS tube M320 and the grid electrode of the NMOS tube M321, the source electrode of the NMOS tube M316 is connected with the drain electrode of the NMOS tube M317 and the drain electrode of the NMOS tube M319, and the drain electrode of the PMOS tube M320 is connected with the drain electrode of the NMOS tube M321, the grid electrode of the PMOS tube M322 and the grid electrode of the NMOS tube M323; the drain of the PMOS transistor M322 is connected to the drain of the NMOS transistor M323, and serves as an output node of the undervoltage protection signal UVLock of the two-stage output shaping circuit 3.

The PMOS transistor M31, the PMOS transistor M32, the NMOS transistor M33, the NMOS transistor M34, the PMOS transistor M35 and the NMOS transistor M36 form a first-stage Schmitt trigger; the PMOS tube M37 and the NMOS tube M38 form a first-stage inverter; the PMOS tube M310, the NMOS tube M311, the PMOS tube M312, the NMOS tube M313, the resistor R31, the resistor R32 and the capacitor C31 form a buffer with an RC filtering function; the PMOS tube M314, the PMOS tube M315, the NMOS tube M316, the NMOS tube M317, the PMOS tube M318 and the NMOS tube M319 form a second-stage Schmitt trigger; the PMOS transistor M320, the NMOS transistor M321, the PMOS transistor M322 and the NMOS transistor M323 form an output buffer.

The input of the first stage schmitt trigger in fig. 5 is connected to the comparison output voltage Vo1 node of the comparator circuit 2; the output end of the first-stage Schmitt trigger is connected to the input end of the first-stage inverter; the output end of the first-stage phase inverter is connected to the input end of the buffer with the RC filtering function; the output end of the buffer with the RC filtering function is connected to the input end of the second-stage Schmitt trigger; the output end of the second-stage Schmitt trigger is connected with the input end of the output buffer; the output end of the output buffer is the undervoltage protection signal UVLock.

The two-stage output shaping circuit 3 shown in fig. 5 provides a standard digital logic signal on one hand, and converts the comparison output voltage Vo1 into a standard digital logic signal, i.e. an undervoltage protection signal UVLock; on the other hand, the common-mode noise and the high-frequency interference influence caused by voltage fluctuation are filtered. The output shaping circuit adopts RC low-pass filtering and two-stage Schmidt trigger combined filtering, so that a certain hysteresis quantity is kept to effectively prevent high-frequency interference and avoid the adverse effect of frequent system starting and stopping on the system. In addition, the two-stage output shaping circuit 3 is controlled by adding a power supply burr detection circuit 4 output signal VC2, and when VC2 is at a low level, the two-stage output shaping circuit 3 works normally; when VC2 is high, the output of NMOS transistor M39 is pulled low, which results in the two-stage output shaping circuit 3 outputting the under-voltage protection signal UVLock locked to high level.

FIG. 6 is an implementation of the power glitch detection circuit 4 of the present invention, where the power glitch detection circuit 4 includes an input amplifier circuit, a Schmitt trigger, a third-stage inverter, and a fourth-stage inverter, which are connected in sequence; the input amplification circuit consists of two stages of amplification circuits, the input end of the input amplification circuit is respectively connected to the output nodes of a second bias voltage signal Vb2, a third bias voltage signal Vb3 and a fourth bias voltage signal Vb4, the output end of the third-stage inverter outputs a signal VC1, and the signal VC1 enters the fourth-stage inverter to be inverted and then outputs a signal VC 2.

In fig. 6, the input amplifying circuit is composed of a PMOS transistor M41, a PMOS transistor M42, an NMOS transistor M43, a PMOS transistor M44, an NMOS transistor M45, a PMOS transistor M46, a resistor R41, a capacitor C41, a resistor R42, and a capacitor C42; the Schmitt trigger consists of a PMOS tube M47, a PMOS tube M48, an NMOS tube M49, an NMOS tube M410, a PMOS tube M411 and an NMOS tube M412; the third-stage phase inverter consists of a PMOS tube M413 and an NMOS tube M414; the fourth-stage inverter consists of a PMOS transistor M415 and an NMOS transistor M416.

The input end of the input amplifying circuit is connected to the output nodes of the second bias voltage signal Vb2, the third bias voltage signal Vb3 and the fourth bias voltage signal Vb4, the output of the third-stage inverter is connected to the input end of the fourth-stage inverter and is simultaneously used as an output signal VC1 of the power supply burr detection circuit 4, and the output of the fourth-stage inverter is used as an output signal VC2 of the power supply burr detection circuit 4.

The specific circuit connection relationship is as follows: the grid electrode of the PMOS tube M41 is connected to the output node of the second bias voltage signal Vb2, the source electrode of the PMOS tube M41 is connected with the power supply voltage VDD, the drain electrode of the PMOS tube M41 is connected with the source electrode of the PMOS tube M42, the grid electrode of the PMOS tube M42 is connected to the output node of the third bias voltage signal Vb3, and the drain electrode of the PMOS tube M42 is connected with the drain electrode and the grid electrode of the NMOS tube M43 and the grid electrode of the NMOS tube M45; the source electrode of the NMOS transistor M43, the source electrode of the NMOS transistor M45, the lower end of the resistor R42, the lower end of the capacitor C42, the source electrode of the NMOS transistor M410, the source electrode of the PMOS transistor M411, the source electrode of the NMOS transistor M414 and the source electrode of the NMOS transistor M416 are simultaneously connected to the ground voltage GND; the grid electrode of the PMOS tube M44 is connected to the output node of the fourth bias voltage signal Vb4, the source electrode of the PMOS tube M44 is connected with the lower end of the resistor R41, the lower end of the capacitor C41 and the grid electrode of the PMOS tube M46, and the drain electrode of the PMOS tube M44 is connected with the drain electrode of the NMOS tube M45; the source electrode of the PMOS tube M46, the upper end of the resistor R41, the upper end of the capacitor C41, the source electrode of the PMOS tube M47, the source electrode of the NMOS tube M412, the source electrode of the PMOS tube M413 and the source electrode of the PMOS tube M415 are simultaneously connected to an internal low-voltage power supply VCCL; the drain of the PMOS tube M46 is connected to the upper end of a resistor R42, the upper end of a capacitor C42, the gate of the PMOS tube M47, the gate of the PMOS tube M48, the gate of the NMOS tube M49 and the gate of the NMOS tube M410; the drain electrode of the PMOS tube M47 is connected with the source electrode of the PMOS tube M48 and the drain electrode of the PMOS tube M411; the drain electrode of the PMOS tube M48 is connected with the drain electrode of the NMOS tube M49, the grid electrode of the PMOS tube M411, the grid electrode of the NMOS tube M412, the grid electrode of the PMOS tube M413 and the grid electrode of the NMOS tube M414; the source electrode of the NMOS tube M49 is connected with the drain electrode of the NMOS tube M410 and the drain electrode of the NMOS tube M412; the drain of the PMOS transistor M413 is connected to the drain of the NMOS transistor M414, the gate of the PMOS transistor M415, and the gate of the NMOS transistor M416, and serves as an output node of a signal VC1 of the power glitch detection circuit 4; the drain of the PMOS transistor M415 is connected to the drain of the NMOS transistor M416 and serves as an output node of a signal VC2 of the power glitch detection circuit 4.

The input amplifier circuit in the power glitch detection circuit 4 shown in fig. 6 is composed of two stages of amplifier circuits, the first stage is a cascode amplifier circuit composed of a PMOS transistor M44 and an NMOS transistor M45, and the second stage is a common source amplifier circuit composed of a PMOS transistor M46, and is used for amplifying a fluctuation signal of the power voltage VDD. The resistor R41, the capacitor C41, the resistor R42 and the capacitor C42 in the circuit are mainly used for filtering high-frequency interference. When the power voltage VDD has a glitch or generates a fast fluctuation, the signal is amplified by the two-stage input amplifier, and then is shaped and converted into digital logic signals VC1 and VC2 by the schmitt trigger, the third-stage inverter and the fourth-stage inverter, so as to control and assist the voltage detection circuit 1, the comparator circuit 2 and the two-stage output shaping circuit 3 to generate more reliable under-voltage protection signals.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A high-accuracy high-reliability undervoltage protection circuit for high-voltage gate driver chip, characterized by includes: the circuit comprises a voltage detection circuit (1), a comparator circuit (2), a two-stage output shaping circuit (3) and a power supply burr detection circuit (4); the voltage detection circuit (1) generates a detection signal Vin according to a chip power supply voltage VDD and outputs the detection signal Vin to the comparator circuit (2); the comparator circuit (2) compares a reference voltage signal Vref with a power supply voltage detection signal Vin to obtain a comparator output signal Vo1, and outputs the comparator output signal Vo1 to the two-stage output shaping circuit (3); the two-stage output shaping circuit (3) shapes the comparator output signal Vo1 to obtain an under-voltage protection signal UVLock, the under-voltage protection signal UVLock is connected to the input end of the voltage detection circuit (1), the UVLock is a digital logic signal and is used for controlling the magnitude of the power supply voltage detection signal Vin, and the under-voltage protection signal UVLock is also used as a control signal to be output to other circuit modules of the high-voltage integrated circuit; the power supply burr detection circuit (4) amplifies a power supply voltage burr signal through a two-stage input amplifier, and then converts the power supply voltage burr signal into digital logic signals VC1 and VC2 through shaping of a Schmitt trigger, a third-stage inverter and a fourth-stage inverter, the signal VC1 is connected to the voltage detection circuit (1) and the comparator circuit (2), the signal VC2 is connected to the comparator circuit (2) and the two-stage output shaping circuit (3), the signal VC1 and the signal VC2 are opposite-phase signals and are used for controlling and assisting the voltage detection circuit (1), the comparator circuit (2) and the two-stage output shaping circuit (3) to generate a more reliable undervoltage protection signal UVLock; the voltage detection circuit (1) is connected with a chip power supply voltage VDD, the comparator circuit (2) and the two-stage output shaping circuit (3) are both connected with an internal low-voltage power supply VCCL, and the power burr detection circuit (4) is simultaneously connected with the chip power supply voltage VDD and the internal low-voltage power supply VCCL; the internal low-voltage power supply VCCL is generated by a chip power supply voltage VDD through a voltage reduction circuit;

when the power supply voltage of the chip is normal, a power burr detection circuit (4) outputs a signal VC1 at a high level, a signal VC2 at a low level, the circuit works normally, an under-voltage protection signal UVLock is at a low level, and the UVLock low level controls a voltage detection circuit (1) to generate a higher power supply voltage detection signal Vin;

when the power voltage of the chip is abnormal, the undervoltage protection signal UVLock is changed into a high-level logic signal, the high level of the UVLock controls the voltage detection circuit (1) to generate a lower power voltage detection signal Vin, and the locking signal Vo1 is a high-level signal; at this time, the output signal VC1 of the power glitch detection circuit (4) is low, and VC2 is high, which further cooperate with the UVLock to be high.

2. The high-precision high-reliability undervoltage protection circuit for the high-voltage gate driving chip as claimed in claim 1, wherein the power glitch detection circuit (4) comprises an input amplification circuit, a Schmitt trigger, a third-stage inverter and a fourth-stage inverter which are connected in sequence; the input amplification circuit consists of two stages of amplification circuits, the input end of the input amplification circuit is respectively connected to the output nodes of a second bias voltage signal Vb2, a third bias voltage signal Vb3 and a fourth bias voltage signal Vb4, the output end of the third-stage inverter outputs a signal VC1, and the signal VC1 enters the fourth-stage inverter to be inverted and then outputs a signal VC 2.

3. The high-precision high-reliability undervoltage protection circuit for the high-voltage gate driving chip as claimed in claim 2, wherein the input amplifying circuit comprises: a PMOS tube M41, a PMOS tube M42, an NMOS tube M43, a PMOS tube M44, an NMOS tube M45, a PMOS tube M46, a resistor R41, a capacitor C41, a resistor R42 and a capacitor C42; the Schmitt trigger includes: the transistor is composed of a PMOS tube M47, a PMOS tube M48, an NMOS tube M49, an NMOS tube M410, a PMOS tube M411 and an NMOS tube M412; the third-stage phase inverter consists of a PMOS tube M413 and an NMOS tube M414; the fourth-stage inverter consists of a PMOS tube M415 and an NMOS tube M416;

the grid electrode of the PMOS tube M41 is connected to the output node of the second bias voltage signal Vb2, the source electrode of the PMOS tube M41 is connected with the power supply voltage VDD, the drain electrode of the PMOS tube M41 is connected with the source electrode of the PMOS tube M42, the grid electrode of the PMOS tube M42 is connected to the output node of the third bias voltage signal Vb3, and the drain electrode of the PMOS tube M42 is connected with the drain electrode and the grid electrode of the NMOS tube M43 and the grid electrode of the NMOS tube M45; the source electrode of the NMOS transistor M43, the source electrode of the NMOS transistor M45, the lower end of the resistor R42, the lower end of the capacitor C42, the source electrode of the NMOS transistor M410, the source electrode of the PMOS transistor M411, the source electrode of the NMOS transistor M414 and the source electrode of the NMOS transistor M416 are simultaneously connected to the ground voltage GND; the grid electrode of the PMOS tube M44 is connected to the output node of the fourth bias voltage signal Vb4, the source electrode of the PMOS tube M44 is connected with the lower end of the resistor R41, the lower end of the capacitor C41 and the grid electrode of the PMOS tube M46, and the drain electrode of the PMOS tube M44 is connected with the drain electrode of the NMOS tube M45; the source electrode of the PMOS tube M46, the upper end of the resistor R41, the upper end of the capacitor C41, the source electrode of the PMOS tube M47, the source electrode of the NMOS tube M412, the source electrode of the PMOS tube M413 and the source electrode of the PMOS tube M415 are simultaneously connected to an internal low-voltage power supply VCCL; the drain of the PMOS tube M46 is connected to the upper end of a resistor R42, the upper end of a capacitor C42, the gate of the PMOS tube M47, the gate of the PMOS tube M48, the gate of the NMOS tube M49 and the gate of the NMOS tube M410; the drain electrode of the PMOS tube M47 is connected with the source electrode of the PMOS tube M48 and the drain electrode of the PMOS tube M411; the drain electrode of the PMOS tube M48 is connected with the drain electrode of the NMOS tube M49, the grid electrode of the PMOS tube M411, the grid electrode of the NMOS tube M412, the grid electrode of the PMOS tube M413 and the grid electrode of the NMOS tube M414; the source electrode of the NMOS tube M49 is connected with the drain electrode of the NMOS tube M410 and the drain electrode of the NMOS tube M412; the drain electrode of the PMOS pipe M413 is connected to the drain electrode of the NMOS pipe M414, the grid electrode of the PMOS pipe M415 and the grid electrode of the NMOS pipe M416 and is used as an output node of a signal VC1 of the power supply glitch detection circuit (4); the drain electrode of the PMOS tube M415 is connected with the drain electrode of the NMOS tube M416 and is used as an output node of a signal VC2 of the power supply glitch detection circuit (4);

4. The high-precision high-reliability undervoltage protection circuit for the high-voltage gate driving chip as claimed in claim 1, wherein the voltage detection circuit (1) comprises: a PMOS tube M11, an NMOS tube M12, a resistor R11, a resistor R12 and a resistor R13; the source of a PMOS tube M11 is connected to a power supply voltage VDD, the gate of the PMOS tube M11 is connected with a signal VC1 output by a power supply burr detection circuit (4), the drain of the PMOS tube M11 is connected with the upper end of a resistor R11, the source of an NMOS tube M12 is connected with the lower end of a resistor R13 and simultaneously connected to a ground voltage GND, the gate of an NMOS tube M12 is connected to an undervoltage protection signal UVLock, the drain of the NMOS tube M12 is connected with the lower end of a resistor R12 and simultaneously connected with the upper end of a resistor R13, and the lower end of the resistor R11 is connected with the upper end of the resistor R12 and serves as a detection signal Vin output node of a voltage detection circuit (.

5. The high-precision high-reliability undervoltage protection circuit for the high-voltage gate driving chip as claimed in claim 1, wherein the comparator circuit (2) comprises: a PMOS tube M21, an NMOS tube M22, a PMOS tube M23, a PMOS tube M24, an NMOS tube M25, a PMOS tube M26, a PMOS tube M27, a PMOS tube M28, an NMOS tube M29, an NMOS tube M210, an NMOS tube M211, an NMOS tube M212, a PMOS tube M213, an NMOS tube M214, a resistor R21 and a capacitor C21;

the connection relationship of the circuit is as follows: the grid electrode of the PMOS tube M21 is connected to the output node of the first bias voltage signal Vb1, the drain electrode of the PMOS tube M21 is connected with the drain electrode of the NMOS tube M22 and the grid electrode of the NMOS tube M25, and the source electrode of the PMOS tube M21, the source electrode of the PMOS tube M23, the source electrode of the PMOS tube M24, the source electrode of the PMOS tube M26 and the source electrode of the PMOS tube M213 are commonly connected to an internal low-voltage power supply VCCL; the grid electrode of the NMOS tube M22, the grid electrode of the NMOS tube M29 and the grid electrode of the NMOS tube M212 are simultaneously connected to a signal VC2 output by the power supply glitch detection circuit (4); the source electrode of the NMOS transistor M22, the source electrode of the NMOS transistor M25, the source electrode of the NMOS transistor M29, the source electrode of the NMOS transistor M210, the source electrode of the NMOS transistor M211, the source electrode of the NMOS transistor M212, the source electrode of the NMOS transistor M214, the lower end of the resistor R21 and the lower end of the capacitor C21 are connected to the ground voltage GND in common; the grid electrode of the PMOS pipe M23 is connected to a signal VC1 output by the power supply burr detection circuit (4); the drain electrode of the PMOS tube M23 is connected to the grid electrode and the drain electrode of the PMOS tube M24, the drain electrode of the NMOS tube M25, the grid electrode of the PMOS tube M26 and the grid electrode of the PMOS tube M213; the drain electrode of the PMOS tube M26 is connected with the source electrode of the PMOS tube M27 and the source electrode of the PMOS tube M28; the grid electrode of the PMOS tube M27 is connected with a reference voltage signal Vref; the drain electrode of the PMOS tube M27 is connected to the drain electrode of the NMOS tube M29, the drain electrode and the grid electrode of the NMOS tube M210 and the grid electrode of the NMOS tube M211; the grid electrode of the PMOS tube M28 is connected with the detection signal Vin output by the voltage detection circuit (1), the drain electrode of the PMOS tube M28 is connected with the drain electrode of the NMOS tube M211, the drain electrode of the NMOS tube M212 and the grid electrode of the NMOS tube M214, and the drain electrode of the PMOS tube M213 is connected with the drain electrode of the NMOS tube M214, the upper end of the resistor R21 and the upper end of the capacitor C21 and is used as the output node of the output signal Vo1 of the comparator circuit (2).

6. The high-precision high-reliability undervoltage protection circuit for the high-voltage gate driving chip as recited in claim 1, wherein the two-stage output shaping circuit (3) comprises: a PMOS tube M31, a PMOS tube M32, an NMOS tube M33, an NMOS tube M34, a PMOS tube M35, an NMOS tube M36, a PMOS tube M37, an NMOS tube M38, an NMOS tube M39, a PMOS tube M310, an NMOS tube M311, a PMOS tube M312, an NMOS tube M313, a PMOS tube M314, a PMOS tube M315, an NMOS tube M316, an NMOS tube M317, a PMOS tube M318, an NMOS tube M319, a PMOS tube M320, an NMOS tube M321, a PMOS tube M322, an NMOS tube M323, a resistor R31, a resistor R32 and a capacitor C31;

the grid of the PMOS transistor M31, the grid of the PMOS transistor M32, the grid of the NMOS transistor M33, and the grid of the NMOS transistor M34 are commonly connected to the signal Vo1 output by the comparator circuit (2), the source of the PMOS transistor M31, the source of the NMOS transistor M36, the source of the PMOS transistor M37, the source of the PMOS transistor M310, the source of the PMOS transistor M312, the source of the PMOS transistor M314, the source of the NMOS transistor M319, the source of the PMOS transistor M320, and the source of the PMOS transistor M322 are commonly connected to the internal low voltage power supply VCCL, the drain of the PMOS transistor M31 is connected to the source of the PMOS transistor M32 and the drain of the PMOS transistor M35, the drain of the PMOS transistor M32 is connected to the drain of the NMOS transistor M33, the grid of the PMOS transistor M35, the grid of the NMOS transistor M36, the grid of the PMOS transistor M37, and the grid of; the source electrode of the NMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the drain electrode of the NMOS tube M36; the source of the NMOS transistor M34, the source of the PMOS transistor M35, the source of the NMOS transistor M38, the source of the NMOS transistor M39, the source of the NMOS transistor M311, the source of the NMOS transistor M313, the source of the NMOS transistor M317, the source of the PMOS transistor M318, the source of the NMOS transistor M321, the source of the NMOS transistor M323, and the lower end of the capacitor C31 are commonly connected to a ground voltage GND, the drain of the PMOS transistor M37 is connected to the drain of the NMOS transistor M38, the drain of the NMOS transistor M39, the gate of the PMOS transistor M310, the gate of the NMOS transistor M311, the gate of the NMOS transistor M39 is connected to a signal VC 62 output by the power glitch detection circuit (4), the drain of the PMOS transistor M310 is connected to the drain of the NMOS transistor M311, the gate of the NMOS transistor M312 and the gate of the NMOS transistor M313, the drain of the PMOS transistor M312 is connected to the upper end of a resistor R732, the lower end of the resistor R32, the upper end of the drain of the capacitor C31, the gate of the PMOS transistor M314, the gate of the PMOS transistor M317, the gate of the PMOS transistor M315, the drain of the PMOS transistor M316, the drain electrode of the PMOS tube M318, the drain electrode of the PMOS tube M315 is connected with the drain electrode of the NMOS tube M316, the grid electrode of the PMOS tube M318, the grid electrode of the NMOS tube M319, the grid electrode of the PMOS tube M320 and the grid electrode of the NMOS tube M321, the source electrode of the NMOS tube M316 is connected with the drain electrode of the NMOS tube M317 and the drain electrode of the NMOS tube M319, and the drain electrode of the PMOS tube M320 is connected with the drain electrode of the NMOS tube M321, the grid electrode of the PMOS tube M322 and the grid electrode of the NMOS tube M323; the drain electrode of the PMOS tube M322 is connected with the drain electrode of the NMOS tube M323 and is used as an output node of an undervoltage protection signal UVLock of the two-stage output shaping circuit (3).