CN114142851A - Sampling type phase frequency detector circuit - Google Patents
Sampling type phase frequency detector circuit Download PDFInfo
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- CN114142851A CN114142851A CN202111331972.5A CN202111331972A CN114142851A CN 114142851 A CN114142851 A CN 114142851A CN 202111331972 A CN202111331972 A CN 202111331972A CN 114142851 A CN114142851 A CN 114142851A
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- 238000005070 sampling Methods 0.000 title claims abstract description 61
- 238000001514 detection method Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000035559 beat frequency Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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Abstract
The invention discloses a sampling type phase frequency detector circuit, which comprises a frequency detector, a sampling type phase detector, a comparator, a logic selection circuit and a signal exchanger. The invention realizes the sampling type phase frequency detector with the phase frequency detection function by improving the sampling type phase detector. The sampling type phase frequency and phase detection phase locked loop adopting the structure has a larger frequency capture range and better robustness. Meanwhile, when the sampling type phase frequency detector circuit is applied to the sampling type phase locked loop, the sampling type phase locked loop does not need an additional frequency locking loop to realize the frequency locking of the phase locked loop, and meanwhile, the loop disturbance caused by the switching between the frequency locking loop and the phase locked loop in the locking process of the phase locked loop and the increase of the loop locking time are avoided. Of course the invention can also be used in a sub-sampling type phase locked loop.
Description
Technical Field
The invention relates to the field of radio frequency integrated circuits, in particular to a sampling type phase frequency detector circuit.
Background
The conventional phase detector cannot provide a frequency discrimination function, and when the frequency deviation of an input signal is large, the phase detector cannot provide useful information, but outputs a beat frequency signal with the frequency of the input frequency difference. Therefore, the frequency synthesizer such as the phase-locked loop cannot provide a large enough frequency capture range in the application of the phase-locked loop and the like, and when the automatic frequency calibration circuit of the phase-locked loop works abnormally or the frequency subband of the oscillator is set to be large, the frequency synthesizer such as the phase-locked loop and the like cannot realize locking.
Disclosure of Invention
Aiming at the defects in the prior art, the sampling type phase frequency detector with the phase frequency detection function is obtained by improving the sampling type phase detector. The sampling type frequency and phase discriminator with the functions of frequency discrimination and phase discrimination is realized.
The purpose of the invention is realized by the following technical scheme:
a sampling type phase frequency detector circuit comprises a frequency detector, a sampling type phase detector, a comparator, a logic selection circuit and a signal exchanger;
the frequency discriminator comprises four ports, namely a reference clock input end Refp _ in, a feedback clock input end fb _ in, two output ends freq _ state1 and freq _ state0 of a frequency discrimination result; when the reference clock frequency is higher than the feedback clock, freq _ state1 is 1, freq _ state0 is 1; when the reference clock frequency is lower than the feedback clock, freq _ state1 is 0, freq _ state0 is 1; when the difference between the reference clock frequency and the feedback clock frequency is less than a certain threshold, freq _ state0 is 0;
the sampling type phase discriminator comprises a normal phase reference signal input end p _ in, an inverse phase reference signal input end n _ in, a feedback signal input end clk, a normal phase output end vsamp and an inverse phase output end vsamn;
the comparator comprises a positive phase input end in +, an inverse phase input end in-and an output end comp, wherein when a signal of the positive phase input end in + is higher than the inverse phase input end in-, the output end comp is at a high level, otherwise, the output end comp is at a low level;
the logic selection circuit comprises three input ends freq _ state1_ in, freq _ state0_ in, comp _ in and an output end sel;
the signal exchanger comprises a positive phase input end vsamp _ in, a negative phase input end vsamn _ in, a control end sel _ in, a positive phase output end outn and a negative phase output end outp;
a reference signal Refp is simultaneously input to a Refp _ in end of the frequency detector and a p _ in end of the sampling type phase detector, and a reference signal Refn is input to an n _ in end of the sampling type phase detector; a feedback clock fb is simultaneously input to the fb _ in end of the frequency detector and the clk end of the sampling type phase detector; freq _ state1 and freq _ state0 of the frequency discriminator are respectively connected with a logic selection circuit freq _ state1_ in and freq _ state0_ in; the vsamp of the sampling type phase discriminator is simultaneously connected with the in + of the comparator and the vsamp _ in of the signal exchanger, and the vsamp of the sampling type phase discriminator is simultaneously connected with the in-of the comparator and the vsamp _ in of the signal exchanger; the comp of the comparator is connected with the comp _ in of the logic selection circuit; the output end sel of the logic selection circuit is connected with the control end sel _ in of the signal exchanger.
Further, the frequency discriminator is a pulse counting frequency discriminator, a time-to-digital converter or a balanced slope frequency discriminator.
Further, one arrangement of the truth table of the logic selection circuit is as follows:
| freq_state1_in | freq_state0_in | comp | sel |
| 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 |
the invention has the following beneficial effects:
the sampling type phase frequency detector can realize the functions of frequency detection and phase detection at the same time. When the sampling type phase frequency detector circuit is applied to the sampling type phase locked loop, the sampling type phase frequency detector phase locked loop has a larger frequency capture range and better robustness. Meanwhile, the sampling phase-locked loop does not need an additional frequency locking loop to realize the frequency locking of the phase-locked loop, and meanwhile, the loop disturbance caused by the switching between the frequency locking loop and the phase-locked loop in the locking process of the phase-locked loop and the increase of the loop locking time are avoided. Of course the invention can also be used in a sub-sampling type phase locked loop.
Drawings
Fig. 1 is a schematic diagram of a sampling-type phase frequency detector circuit according to the present invention;
fig. 2 is a schematic diagram of a phase discrimination curve of a conventional sampling-type phase discriminator;
fig. 3 is a schematic diagram of a phase detection curve of one embodiment of the sampling type phase frequency detector of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the present invention will become more apparent, it being understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
As shown in fig. 1, a sampling-type phase frequency detector circuit according to an embodiment of the present invention includes a frequency detector, a sampling-type phase detector, a comparator, a logic selection circuit, and a signal converter.
The frequency discriminator comprises four ports, namely a reference clock input end Refp _ in, a feedback clock input end fb _ in, two output ends freq _ state1 and freq _ state0 of a frequency discrimination result; when the reference clock frequency is higher than the feedback clock, freq _ state1 is 1, freq _ state0 is 1; when the reference clock frequency is lower than the feedback clock, freq _ state1 is 0, freq _ state0 is 1; when the difference between the reference clock frequency and the feedback clock frequency is less than a certain threshold, freq _ state0 is 0. The frequency discriminator is preferably a pulse count discriminator, a time-to-digital converter or a balanced slope discriminator. The discrimination of the frequency between the input signals is realized through the frequency discriminator.
The sampling type phase discriminator comprises a normal phase reference signal input end p _ in, an inverted phase reference signal input end n _ in, a feedback signal input end clk, a normal phase output end vsamp and an inverted phase output end vsamn.
The comparator comprises a positive phase input end in +, an inverse phase input end in-and an output end comp, wherein when a signal of the positive phase input end in + is higher than the inverse phase input end in-, the output end comp is at a high level, otherwise, the output end comp is at a low level;
the logic selection circuit comprises three input ends freq _ state1_ in, freq _ state0_ in, comp _ in and an output end sel; in one embodiment, the truth table for the logic select circuit is shown in table 1.
| freq_state1_in | freq_state0_in | comp | sel |
| 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 |
The signal exchanger comprises a positive phase input end vsamp _ in, a negative phase input end vsamn _ in, a control end sel _ in, a positive phase output end outn and a negative phase output end outp. The main function of the signal exchanger is to reverse the input signal and then feed the signal to the output. When sel _ in is at high level, the polarity of signals is reversed, the signal exchanger transmits the signal at the vsamp _ in end to the outn end, and the signal at the vsamn end is transmitted to the outp end; when sel is at low level, the polarity of the signal is kept unchanged, the signal at the vsamp _ in terminal is transmitted to the outp terminal, and the signal at the vsamn _ in terminal is transmitted to the outn terminal.
A reference signal Refp is simultaneously input to a Refp _ in end of the frequency detector and a p _ in end of the sampling type phase detector, and a reference signal Refn is input to an n _ in end of the sampling type phase detector; a feedback clock fb is simultaneously input to the fb _ in end of the frequency detector and the clk end of the sampling type phase detector; freq _ state1 and freq _ state0 of the frequency discriminator are respectively connected with a logic selection circuit freq _ state1_ in and freq _ state0_ in; the vsamp of the sampling type phase discriminator is simultaneously connected with the in + of the comparator and the vsamp _ in of the signal exchanger, and the vsamp of the sampling type phase discriminator is simultaneously connected with the in-of the comparator and the vsamp _ in of the signal exchanger; the comp of the comparator is connected with the comp _ in of the logic selection circuit; the output end sel of the logic selection circuit is connected with the control end sel _ in of the signal exchanger.
Assuming that input signals at p _ in and n _ in ends of the sampling type phase detector are sine waves, a phase detection curve of the conventional sampling type phase detector is shown in fig. 2, where vsam represents vsamp-vsamn, and phase represents an input phase difference of the sampling type phase detector. As the phase difference between the output signals of the sampling type phase discriminator becomes larger, the output signals of the sampling type phase discriminator show periodic changes. This results in that the sampling type phase detector can only ensure that the polarity of the output signal is correct within a limited input phase difference range, i.e. the polarity of the phase detection result of the sampling type phase detector is correct within the interval of-pi to + pi.
At this time, a phase discrimination curve obtained by using the sampling type phase frequency detector circuit of the present invention is shown in fig. 3, where vsam represents vsamp-vsamn, and phase represents an input phase difference of the sampling type phase detector, and the sampling type phase frequency detector can ensure that a polarity of an output phase discrimination result is correct under any input phase difference. Assuming that the frequency of the feedback clock is reduced along with the increase of the control voltage, assuming that the frequency of the input reference signal is higher than the frequency of the feedback clock, in order to realize the frequency discrimination effect, the output of the sampling type phase frequency discriminator needs to be ensured to be always smaller than zero, so that the frequency of the feedback clock can be ensured to be increased all the time; if the frequency of the input reference signal is lower than the frequency of the feedback clock, the output of the sampling type phase frequency detector is always greater than zero to achieve the frequency discrimination effect, so that the frequency of the feedback clock is always reduced.
The invention utilizes the state signal output by the frequency discriminator and the output result of the comparator to control the polarity of the output result of the sampling type phase discriminator, thus ensuring that when the output signal has larger frequency difference, the sampling type phase discriminator circuit can always ensure the correct phase discrimination polarity result (indicating the frequency of the input signal) until the frequency difference of the input signal is basically consistent, the sampling type phase discriminator can be caught by the phase discriminator, at this time, the loop of the frequency discriminator does not work, and the sampling type phase discriminator can provide the correct phase discrimination result.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made and equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.
Claims (3)
1. A sampling type phase frequency detector circuit is characterized by comprising a frequency detector, a sampling type phase detector, a comparator, a logic selection circuit and a signal exchanger;
the frequency discriminator comprises four ports, namely a reference clock input end Refp _ in, a feedback clock input end fb _ in, two output ends freq _ state1 and freq _ state0 of a frequency discrimination result; when the reference clock frequency is higher than the feedback clock, freq _ state1 is 1, freq _ state0 is 1; when the reference clock frequency is lower than the feedback clock, freq _ state1 is 0, freq _ state0 is 1; when the difference between the reference clock frequency and the feedback clock frequency is less than a certain threshold, freq _ state0 is 0;
the sampling type phase discriminator comprises a normal phase reference signal input end p _ in, an inverse phase reference signal input end n _ in, a feedback signal input end clk, a normal phase output end vsamp and an inverse phase output end vsamn;
the comparator comprises a positive phase input end in +, an inverse phase input end in-and an output end comp, wherein when a signal of the positive phase input end in + is higher than the inverse phase input end in-, the output end comp is at a high level, otherwise, the output end comp is at a low level;
the logic selection circuit comprises three input ends freq _ state1_ in, freq _ state0_ in, comp _ in and an output end sel;
the signal exchanger comprises a positive phase input end vsamp _ in, a negative phase input end vsamn _ in, a control end sel _ in, a positive phase output end outn and a negative phase output end outp;
a reference signal Refp is simultaneously input to a Refp _ in end of the frequency detector and a p _ in end of the sampling type phase detector, and a reference signal Refn is input to an n _ in end of the sampling type phase detector; a feedback clock fb is simultaneously input to the fb _ in end of the frequency detector and the clk end of the sampling type phase detector; freq _ state1 and freq _ state0 of the frequency discriminator are respectively connected with a logic selection circuit freq _ state1_ in and freq _ state0_ in; the vsamp of the sampling type phase discriminator is simultaneously connected with the in + of the comparator and the vsamp _ in of the signal exchanger, and the vsamp of the sampling type phase discriminator is simultaneously connected with the in-of the comparator and the vsamp _ in of the signal exchanger; the comp of the comparator is connected with the comp _ in of the logic selection circuit; the output end sel of the logic selection circuit is connected with the control end sel _ in of the signal exchanger.
2. A sampling type phase frequency detector circuit according to claim 1, wherein said frequency detector is a pulse count frequency detector, a time to digital converter or a balanced slope frequency detector.
3. A sampled phase frequency detector circuit as claimed in claim 1, wherein one of the truth tables of the logic selection circuit is arranged as follows:
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|---|---|---|---|
| CN202111331972.5A CN114142851A (en) | 2021-11-11 | 2021-11-11 | Sampling type phase frequency detector circuit |
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| CN202111331972.5A CN114142851A (en) | 2021-11-11 | 2021-11-11 | Sampling type phase frequency detector circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023179261A1 (en) * | 2022-03-23 | 2023-09-28 | 华为技术有限公司 | Phase-frequency detector, phase-locked loop, and electronic device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023179261A1 (en) * | 2022-03-23 | 2023-09-28 | 华为技术有限公司 | Phase-frequency detector, phase-locked loop, and electronic device |
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