WO2023179261A1

WO2023179261A1 - Phase-frequency detector, phase-locked loop, and electronic device

Info

Publication number: WO2023179261A1
Application number: PCT/CN2023/076786
Authority: WO
Inventors: 张津海
Original assignee: 华为技术有限公司
Priority date: 2022-03-23
Filing date: 2023-02-17
Publication date: 2023-09-28
Also published as: CN116846386A

Abstract

The present application provides a phase-frequency detector, a phase-locked loop, and an electronic device, and relates to the technical field of integrated circuits. The phase-frequency detector is at least one order of magnitude faster and more precise compared to the time at which traditional solutions are depleted when detecting phase and frequency. The phase-frequency detector comprises: a two-phase synchronous logic circuit, a time-to-digital converter, a counter, and a phase-frequency detection logic circuit. The two-phase synchronous logic circuit receives a local clock signal and a reference clock signal; the counter determines a first number of complete periods of the local clock signal during n periods of the reference clock signal; the time-to-digital converter determines a coefficient and a second number of unit steps in an incomplete period of the local clock signal during n periods of the reference clock signal; and the phase-frequency detection logic circuit determines, according to the first number, the second number and the coefficient, a first phase difference between the reference clock signal and the local clock signal during n periods of the reference clock signal.

Description

Frequency detectors, phase locked loops and electronic equipment

This application requires the priority of the Chinese patent application submitted to the State Intellectual Property Office on March 23, 2022, with the application number 202210290537.0 and the application name "Frequency Phase Detector, Phase Locked Loop and Electronic Equipment", and all its contents have been approved This reference is incorporated into this application.

Technical field

The present application relates to the field of integrated circuit technology, and in particular to a frequency and phase detector, a phase-locked loop and electronic equipment.

Background technique

Currently, in most systems such as central processing unit (CPU) and graphics processing unit (GPU), dynamic voltage and frequency scaling (DVFS) technology is introduced. Among them, dynamic voltage and frequency scaling (DVFS) technology is introduced. Voltage regulation and frequency regulation technology can dynamically adjust the system voltage and the frequency of the local clock signal when the system is running according to the needs of different applications running the system, thereby reducing system energy consumption.

In order to adjust the frequency of the local clock signal when the system is running, it is first necessary to lock the frequency of the local clock signal when the system is running. Locking the frequency of the local clock signal when the system is running usually requires the use of a phase frequency detector (PFD) for frequency identification, that is, determining the frequency difference between the target clock signal and the local clock signal, so that the system determines the frequency based on the frequency difference. How to adjust the frequency of the local clock signal so that the frequency of the local clock signal is locked to the frequency of the target clock signal. However, the frequency identification accuracy of the existing frequency and phase detector is 1, which means that the existing frequency and phase detector can determine that the frequency difference between the target clock signal and the local clock signal is at least 1, so that the frequency and phase detector When the device performs frequency and phase identification processing, it takes a long time.

Contents of the invention

Embodiments of the present application provide a frequency and phase detector, a phase-locked loop and electronic equipment. When the frequency and phase detector performs frequency and phase detection processing, it consumes at least one order of magnitude faster time and is more accurate than the traditional solution. high.

In order to achieve the above objectives, the embodiments of this application adopt the following technical solutions:

In the first aspect, embodiments of the present application provide a frequency and phase detector, including: a two-phase synchronous logic circuit, a counter, a time-to-digital converter, and a frequency and phase detector; a two-phase synchronous logic circuit for receiving local The clock signal and the reference clock signal, the period length of the reference clock signal is greater than the period length of the local clock signal; after the rising edge of the reference clock signal, the first clock signal is generated according to the first rising edge of the local clock signal, where the first The rising edge of the clock signal is not earlier than the first rising edge of the local clock signal; after the rising edge of the reference clock signal, the second clock signal is generated according to the second rising edge of the local clock signal, where the second clock signal The rising edge is not earlier than the second rising edge of the local clock signal; after the rising edge of the reference clock signal, the third clock signal is generated according to the third rising edge of the local clock signal, where the rising edge of the third clock signal is not Earlier than the third rising edge of the local clock signal; counter, used to determine the first number of complete cycles of the local clock signal within n cycles of the reference clock signal, where n is a positive integer greater than or equal to 2; time-to-digital converter , used to determine the coefficient based on the second clock signal and the third clock signal, the coefficient is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal; also used to determine the coefficient based on the reference clock signal and the first clock signal , determine the second number of unit steps in the incomplete cycles of the local clock signal within n cycles of the reference clock signal quantity; a frequency and phase detection logic circuit, configured to determine the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal based on the first quantity, the second quantity, and the coefficient. In the above frequency and phase detector, the two-phase synchronization logic circuit receives the reference clock signal and the local clock signal, and generates the first clock signal according to the first rising edge of the local clock signal after the rising edge of the reference clock signal; After the rising edge of the reference clock signal, the second clock signal is generated based on the second rising edge of the local clock signal. After the rising edge of the reference clock signal, the third clock signal is generated based on the third rising edge of the local clock signal. Furthermore, the counter can determine the first number of complete cycles of the local clock signal within n cycles of the reference clock signal, and the time-to-digital converter can determine the unit steps of the incomplete cycles of the local clock signal within n cycles of the reference clock signal. The second longer number, and the time-to-digital converter can also determine a coefficient. This coefficient is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal. Then, when the frequency identification and phase identification logic circuit receives After reaching the first number, the second number, and the coefficient, the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal Fref can be determined based on the first number, the second number, and the coefficient. For such a frequency and phase detector, due to the existence of the time-to-digital converter, the accuracy of the frequency and phase identification is improved to the ratio of the unit step of the time-to-digital converter to the length of one cycle of the local clock signal, and the time-to-digital conversion The unit step size of the detector is usually on the order of picoseconds (ps). Therefore, when the current frequency and phase detector performs frequency and phase identification processing, it consumes at least one order of magnitude faster time and has higher accuracy than the traditional solution.

Optionally, the frequency and phase identification logic circuit is specifically used to determine the third number of complete cycles of the local clock signal corresponding to the second number according to the second number and the coefficient; add the first number to the third number to obtain Within n cycles of the reference clock signal, the fourth number of complete cycles of the local clock signal; based on the reference clock signal and the fourth number, determine the first number of complete cycles of the reference clock signal and the local clock signal within n cycles of the reference clock signal. phase difference.

Optionally, the frequency and phase identification logic circuit is also used to determine the second phase difference based on the fourth number within n cycles and the fourth number within the next n cycles; determine the local clock based on the second phase difference. The frequency of the signal. In this optional solution, according to the relationship between phase and frequency, the frequency and phase detector obtains the fourth number based on two adjacent n cycles, which can obtain the frequency of the local clock signal, so that the frequency and phase detector simultaneously It has frequency identification and phase identification functions.

Optionally, the two-phase synchronous logic circuit generates a fourth clock signal based on the fourth rising edge of the local clock signal after the rising edge of the reference clock signal, wherein the rising edge of the fourth clock signal is no earlier than the local clock signal. The fourth rising edge of the two-phase synchronous logic circuit is also used for the control signal generated by the frequency and phase detection logic circuit received at the control end of the two-phase synchronous logic circuit. When the control signal is at the first level, the reference clock The signal is transmitted to the data input terminal of the time-to-digital converter, the first clock signal is transmitted to the clock input terminal of the time-to-digital converter, and the third clock signal is transmitted to the sampling input terminal of the time-to-digital converter; when the control signal is the second level, the second clock signal is transmitted to the data input terminal of the time-to-digital converter, the third clock signal is transmitted to the clock input terminal of the time-to-digital converter, and the fourth clock signal is transmitted to the sampling input terminal of the time-to-digital converter. .

Optionally, this application provides specific connection methods for two-phase synchronous logic circuits. Two-phase synchronous logic circuit, including: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a delay, and an OR gate; two-phase synchronous logic The first input end of the circuit is connected to the clock input end of the first D flip-flop, the set end of the first D flip-flop, the set end of the second D flip-flop, the set end of the third D flip-flop, and the fourth D flip-flop. The set end of the D flip-flop, the set end of the fifth D flip-flop and the input end of the delay; two-phase synchronous logic circuit The second input terminal is connected to the first input terminal of the OR gate; the output terminal of the delay device is connected to the first output terminal of the two-phase synchronous logic circuit; the data input terminal of the first D flip-flop is connected to the third level terminal, The inverse output terminal of the first D flip-flop is connected to the second input terminal of the OR gate, wherein the third level terminal provides the third level; the output terminal of the OR gate is connected to the clock input terminal of the second D flip-flop, the third The clock input terminal of the D flip-flop, the clock input terminal of the fourth D flip-flop and the clock input terminal of the fifth D flip-flop; the data input terminal of the second D flip-flop is connected to the third level terminal, and the data input terminal of the second D flip-flop is connected to the third level terminal. The positive output terminal is connected to the data input terminal of the third D flip-flop and the second output terminal of the two-phase synchronous logic circuit; the positive output terminal of the third D flip-flop is connected to the data input terminal of the fourth D flip-flop and the two The first output terminal of the two-phase synchronous logic circuit; the forward output terminal of the fourth D flip-flop is connected to the data input terminal of the fifth D flip-flop, the second output terminal of the two-phase synchronous logic circuit, and the third output terminal of the two-phase synchronous logic circuit. Three output terminals; the positive output terminal of the fifth D flip-flop is connected to the third input terminal of the OR gate and the third output terminal of the two-phase synchronous logic circuit; the two-phase synchronous logic circuit is used to obtain the output terminal from the two-phase synchronous logic circuit. The first input terminal receives the reference clock signal and receives the local clock signal from the second input terminal of the two-phase synchronous logic circuit; the first D flip-flop is used to receive the reference clock signal at the setting terminal of the first D flip-flop and the clock input terminal. Under the control of the clock signal, an enable signal is generated according to the third level received by the data input terminal of the first D flip-flop; the OR gate is used to compare the received enable signal, the local clock signal and the positive signal of the fifth D flip-flop. The fourth clock signal output to the output terminal is OR logically processed to generate a control clock signal; the second D flip-flop is used for the reference clock signal received at the set end of the second D flip-flop, and the second D flip-flop. Under the control of the control clock signal received by the clock input terminal, the first clock signal is generated according to the third level received by the data input terminal of the second D flip-flop; the third D flip-flop is used to set the third D flip-flop. Under the control of the reference clock signal received by the bit terminal and the control clock signal received by the clock input terminal of the third D flip-flop, a second clock signal is generated according to the first clock signal received by the data input terminal of the third D flip-flop; A four-D flip-flop, used for controlling the reference clock signal received by the setting terminal of the fourth D flip-flop and the control clock signal received by the clock input terminal of the fourth D flip-flop, according to the data of the fourth D flip-flop. The second clock signal received at the input terminal generates a third clock signal; the fifth D flip-flop is used for the reference clock signal received at the set terminal of the fifth D flip-flop, and the clock input terminal of the fifth D flip-flop receives Under the control of the control clock signal, a fourth clock signal is generated according to the third clock signal received by the data input terminal of the fifth D flip-flop; the delayer is used to delay the reference clock signal and generate a delayed reference clock signal ; The time-to-digital converter is specifically used to determine the second number of unit steps in the incomplete cycles of the local clock signal within n cycles of the reference clock signal based on the delayed reference clock signal and the first clock signal.

Optionally, the two-phase synchronous logic circuit also includes a first selector, a second selector and a third selector; the control end of the two-phase synchronous logic circuit is connected to the control end of the first selector and the second selector. The control end and the control end of the third selector; the first input end of the first selector is connected to the output end of the delayer, and the second input end of the first selector is connected to the positive output end of the third D flip-flop. , the output terminal of the second selector is connected to the first output terminal of the two-phase synchronous logic circuit; the first input terminal of the second selector is connected to the positive output terminal of the second D flip-flop, and the second terminal of the second selector The input terminal is connected to the positive output terminal of the fourth D flip-flop, the output terminal of the second selector is connected to the second output terminal of the two-phase synchronous logic circuit; the first input terminal of the third selector is connected to the fourth D flip-flop. The forward output end of the third selector is connected to the forward output end of the fifth D flip-flop, and the output end of the third selector is connected to the third output end of the two-phase synchronous logic circuit; the two The one-phase synchronous logic circuit receives the control signal generated by the frequency and phase detection logic circuit from the control end of the two-phase synchronous logic circuit; the first selector passes the delayed reference signal through the two-phase synchronous logic circuit when the control signal is at the first level. The first output of the time digital the data input terminal of the converter; when the control signal is at the second level, the second clock signal is transmitted to the data input terminal of the time-to-digital converter through the first output terminal of the two-phase synchronous logic circuit; the second selector, when the control signal When the control signal is at the second level, the first clock signal is transmitted to the clock input terminal of the time-to-digital converter through the second output terminal of the two-phase synchronous logic circuit; when the control signal is at the second level, the third clock signal is transmitted through the two-phase synchronous logic circuit The second output end of the circuit is transmitted to the clock input end of the time-to-digital converter; the third selector transmits the third clock signal to the time digital through the third output end of the two-phase synchronous logic circuit when the control signal is the first level. The sampling input terminal of the converter; when the control signal is at the second level, the fourth clock signal is transmitted to the sampling input terminal of the time-to-digital converter through the third output terminal of the two-phase synchronous logic circuit.

Optionally, the counter is also used to sample the first number according to the third clock signal when the control signal generated by the frequency and phase detection logic circuit is at the first level, and store the first number in the counter.

Optionally, the time-to-digital converter is also used to sample the second quantity according to the third clock signal when the control signal generated by the frequency and phase detection logic circuit is at the first level, and store the second quantity in the time-to-digital conversion in the vessel.

Optionally, the time-to-digital converter is also configured to sample the coefficients according to the fourth clock signal when the control signal is the second level, and store the coefficients in the time-to-digital converter.

Optionally, the frequency and phase detection logic circuit is also used to receive a reference clock signal and generate a control signal according to the reference clock signal. The control signal is the second level in the first cycle of the reference clock signal; the control signal is at the second level in the first cycle of the reference clock signal. The first level is from the 2nd cycle to the nth cycle of the signal.

In a second aspect, a phase-locked loop is provided. The phase-locked loop includes a filter, an oscillation circuit and a frequency and phase detector as described in any one of the above-mentioned first aspects; the frequency and phase detector is connected to the oscillator through the filter. circuit, the oscillation circuit is also connected to the frequency and phase detector; the frequency and phase detector receives the reference clock signal, the local clock signal generated by the oscillation circuit, and the target clock signal, and determines based on the reference clock signal, the local clock signal, and the target clock signal. The third phase difference between the target clock signal and the local clock signal within n cycles of the reference clock signal generates a voltage control signal based on the third phase difference; the filter receives the voltage control signal and generates the control voltage of the oscillation circuit based on the voltage control signal ; The oscillation circuit receives the control voltage and adjusts the frequency of the local clock signal generated by the oscillation circuit under the control of the control voltage.

In a third aspect, an electronic device is provided. The electronic device includes a printed circuit board, and further includes: a phase-locked loop as described in the second aspect provided on the printed circuit board, or a phase-locked loop as described in the second aspect provided on the printed circuit board. The frequency and phase detector described in the first aspect.

The fourth aspect provides a frequency and phase identification method, which includes: receiving a local clock signal and a reference clock signal; the period length of the reference clock signal is greater than the period length of the local clock signal; after the rising edge of the reference clock signal, according to the local The first rising edge of the clock signal generates the first clock signal, wherein the rising edge of the first clock signal is not earlier than the first rising edge of the local clock signal; after the rising edge of the reference clock signal, according to the The second rising edge generates a second clock signal, wherein the rising edge of the second clock signal is no earlier than the second rising edge of the local clock signal; after the rising edge of the reference clock signal, according to the third rising edge of the local clock signal The rising edge generates a third clock signal, wherein the rising edge of the third clock signal is no earlier than the third rising edge of the local clock signal; determining the first number of complete cycles of the local clock signal within n cycles of the reference clock signal , n is a positive integer greater than or equal to 2; the coefficient is determined based on the second clock signal and the third clock signal, and the coefficient is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal; also based on the reference clock signal and the first clock signal, determine the incomplete cycles of the local clock signal within n cycles of the reference clock signal A second number of unit steps in the period; according to the first number, the second number, and the coefficient, determine the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal.

Optionally, determining the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal according to the first number, the second number, and the coefficient includes: according to the second number and the coefficient, Determine the third number of complete cycles of the local clock signal corresponding to the second number; add the first number to the third number to obtain the fourth number of complete cycles of the local clock signal within n cycles of the reference clock signal; according to The reference clock signal and the fourth quantity determine the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal.

Optionally, determine the second phase difference based on the fourth number within n cycles and the fourth number within the next n cycles; determine the frequency of the local clock signal based on the second phase difference.

Optionally, after receiving the local clock signal and the reference clock signal, the method further includes: after the rising edge of the reference clock signal, generating a fourth clock signal according to the fourth rising edge of the local clock signal, wherein the rising edge of the fourth clock signal edge no earlier than the fourth rising edge of the local clock signal.

Optionally, after receiving the local clock signal and the reference clock signal, the method includes: generating an enable signal according to the third level under the control of the reference clock signal; and performing the processing on the received enable signal, the local clock signal and the fourth clock signal. or logical processing to generate a control clock signal; under the control of the reference clock signal and the control clock signal, generate the first clock signal according to the third level; under the control of the reference clock signal and the control clock signal, according to the first clock signal The signal generates a second clock signal; under the control of the reference clock signal and the control clock signal, a third clock signal is generated according to the second clock signal; under the control of the reference clock signal and the control clock signal, a third clock signal is generated The fourth clock signal; perform delay processing on the reference clock signal to generate a delayed reference clock signal; then, according to the reference clock signal and the first clock signal, determine within n cycles of the reference clock signal, among the incomplete cycles of the local clock signal The second number of unit steps specifically includes: determining the second number of unit steps in the incomplete cycles of the local clock signal within n cycles of the reference clock signal based on the delayed reference clock signal and the first clock signal.

Optionally, the method further includes: when the control signal is at the first level, sampling the first number according to the third clock signal, and storing the first number.

Optionally, the method further includes: when the control signal is at the first level, sampling the second quantity according to the third clock signal, and storing the second quantity.

Optionally, the method further includes: when the control signal is at the second level, sampling the coefficient according to the fourth clock signal and storing the coefficient.

Optionally, the method further includes: receiving a reference clock signal, and generating a control signal according to the reference clock signal. The control signal is at the second level during the first cycle of the reference clock signal; the control signal is at the second level during the second cycle of the reference clock signal. It is the first level in the nth cycle.

In a fifth aspect, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are run on an electronic device, the electronic device causes the electronic device to perform the frequency and phase identification method as described in any one of the fourth aspects.

In a sixth aspect, a computer program product is provided. When the computer program product is run on an electronic device, it causes the electronic device to execute the frequency and phase identification method described in any one of the fourth aspects.

Among them, the technical effects brought about by any one of the possible implementation methods of the second to sixth aspects can be referred to the technical effects brought by any different implementation methods of the above-mentioned first aspect, and will not be described again here.

Description of the drawings

Figure 1 is a schematic structural diagram of a D flip-flop according to Embodiment 1 of the present application;

Figure 2 is a schematic structural diagram of a phase-locked loop according to Embodiment 1 of the present application;

Figure 3 is a timing diagram of an automatic frequency control loop provided by Embodiment 1 of the present application;

Figure 4 is a schematic structural diagram of a frequency and phase detector provided in Embodiment 2 of the present application;

Figure 5 is a timing diagram of the frequency and phase detector provided in Embodiment 2 of the present application;

Figure 6 is a timing diagram of a control signal provided by Embodiment 2 of the present application;

Figure 7 is a schematic structural diagram of a two-phase synchronous logic circuit provided in Embodiment 3 of the present application;

Figure 8 is a timing diagram of a two-phase synchronous logic circuit provided in Embodiment 3 of the present application;

Figure 9 is another structural schematic diagram of a two-phase synchronous logic circuit provided in Embodiment 3 of the present application;

Figure 10 is a schematic structural diagram of a phase-locked loop provided in Embodiment 4 of the present application;

Figure 11 is a schematic structural diagram of an oscillator provided in Embodiment 4 of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In this application, "at least one (layer)" refers to one (layer) or multiple (layers), and "multiple (layers)" refers to two (layers) or more than two (layers). "And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can It can be single or multiple. In addition, in the embodiments of the present application, words such as “first” and “second” do not limit the number and order.

In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the schematically placed directions of the components in the drawings. It should be understood that these directional terms are relative concepts and they are used relative to each other. The descriptions and clarifications may change accordingly according to the changes in the orientation of the components in the drawings.

It should be noted that in this application, words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "such as" is not intended to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

The technical terms used in the embodiments of this application are explained below:

A D flip-flop is an information storage device with a memory function and two stable states. Referring to Figure 1, an embodiment of the present application provides a schematic structural diagram of a D flip-flop. The D flip-flop has three input terminals and two output terminals. The three input terminals are the data input terminal D terminal, the clock input terminal clk terminal, and the set terminal rstn terminal. The two output terminals are the forward output terminal Q terminal and the Reverse output terminal, and the level output by the forward output terminal Q terminal is the same as the reverse output terminal The level of the terminal output is always opposite. In the D flip-flop, when the set terminal rstn terminal inputs a low level (also called LOW), no matter what level the clock input terminal clk terminal and the data input terminal D terminal input, The positive output terminal Q terminal of the D flip-flop outputs a low level. When the setting terminal rstn terminal inputs a high level (also called HIGH), and a rising edge occurs at the clock input terminal clk terminal (that is, the level input at the clock input terminal clk terminal changes from low level to high level) level), the level output by the positive output terminal Q terminal of the D flip-flop is the same as the input level input by the data input terminal D terminal; when the set terminal rstn terminal inputs a high level (also called HIGH), and When the clock input terminal clk inputs a low level, the level output by the forward output terminal Q of the D flip-flop remains consistent with the level output by the forward output terminal Q at the previous moment.

For example, the basic process of dynamic voltage and frequency modulation technology includes: collecting signals related to system load, calculating the system load in the current time period; predicting the performance required by the system in the next time period based on the system load in the current time period; predicting The obtained performance is converted into the frequency of the local clock signal required when the system is running; the system voltage when the system is running is calculated based on the required frequency of the local clock signal, and the power management module in the system is notified to provide the system voltage to the system.

In order to adjust the frequency of the local clock signal when the system is running, it is first necessary to lock the frequency of the local clock signal when the system is running. The existing phase locked loop (PLL) or frequency locked loop (FLL) can achieve the purpose of locking the frequency of the local clock signal when the system is running.

Taking the digital architecture phase-locked loop as an example, with reference to Figure 2, the embodiment of the present application provides a schematic structural diagram of the phase-locked loop 20. The phase-locked loop 20 includes a frequency detector 201, a loop filter (loop filter). , LF) 202, voltage control oscillator (VCO) 203, the first input end of the frequency and phase detector 201 receives the reference clock signal Fref, and the output end of the frequency and phase detector 201 passes through the loop filter 202 Connected to the voltage controlled oscillator 203 , the voltage controlled oscillator 203 is connected to the second input end of the frequency and phase detector 201 . Among them, the voltage controlled oscillator 203 is used to generate the local clock signal Fckv, and transmit the local clock signal Fckv to the second input end of the frequency and phase detector 201. The frequency and phase detector 201 compares the local clock signal Fckv and the reference clock signal Fref. The phase difference of The signal Ud is filtered to generate the control voltage Uc of the voltage-controlled oscillator 203, and the control voltage Uc is transmitted to the voltage-controlled oscillator 203, so that the voltage-controlled oscillator 203 adjusts the frequency and phase of the local clock signal Fckv to realize the local clock signal. The frequency and phase of Fckv are locked to the frequency and phase of the reference clock signal Fref.

It should be noted that when the frequency and phase detector 201 is used to compare the frequencies of the local clock signal Fckv and the reference clock signal Fref, the phase-locked loop of the digital architecture may also be called a frequency-locked loop of the digital architecture.

For example, in a phase-locked loop of a digital architecture, there is usually a target clock signal, in which both the target clock signal and the reference clock signal are determined, and the target clock signal and the reference clock signal have a fixed ratio relationship. In order to achieve fast phase locking, the phase-locked loop is usually frequency-locked first and then phase-locked, that is, first aligning the frequency of the local clock signal with the target clock signal, and then aligning the phase of the local clock signal with the target clock signal. alignment. Among them, in order to realize the frequency locking of the digital structure phase-locked loop, most of them will be attached to the digital structure phase-locked loop. Add an automatic frequency control (AFC) loop. The automatic frequency control loop requires frequency identification, that is, to determine the frequency difference between the target clock signal and the local clock signal. The automatic frequency control loop often uses a reference The clock signal Fref constructs a counting time window, and within this counting time window, the target clock signal is counted to generate the target quantity. The local clock signal is also counted within this counting time window to generate the local quantity, and then the target quantity and the local quantity are calculated. The difference between them is the equivalent frequency difference between the target clock signal and the local clock signal.

Among them, in order to increase the counting time, the automatic frequency control loop often divides the reference clock signal Fref by N. Since the frequency of the local clock signal is usually in the GHz level, it is often difficult to achieve the GHz level in digital architecture. Therefore, it is also necessary to divide the local clock signal to the 100MHz level to meet the frequency requirements in the current digital structure. Referring to Figure 3, a timing diagram of an automatic frequency control loop provided by an embodiment of the present application is shown. Figure 3 includes the timing of the reference clock signal Fref, the timing of N-dividing the reference clock signal Fref, and the target clock signal Fckv1 The timing of the target clock signal Fckv1 is divided by M. For example, referring to Figure 3, the automatic frequency control loop in the digital phase-locked loop determines the equivalent frequency difference between the target clock signal Fckv1 and the local clock signal Fckv according to the following formula 1:

In Formula 1, the period of the reference clock signal Fref is Tref. Since the constructed counting time window divides the reference clock signal Fref by N, the counting time window can be expressed as N*Tref. The period of the target clock signal Fckv1 is Tckv1, and the target clock signal Fckv1 is divided by M, so one period after the target clock signal Fckv1 is divided is M*Tckv1; the period of the local clock signal Fckv is Tckv, and the counter The signal Fckv is divided by M, so one cycle after the local clock signal Fckv is divided is M*Tckv. Among them, the first term in formula 1 Indicates the target number obtained by counting the target clock signal Fckv1 within a counting time window of the reference clock signal Fref, the second term in Formula 1 Indicates the local number obtained by counting the local clock signal Fckv within a counting time window of the reference clock signal Fref. Then the first term minus the second term can determine the target clock within a counting period of the reference clock signal Fref. The equivalent frequency difference between the signal Fckv1 and the local clock signal Fckv.

Among them, when counting the target clock signal Fckv1 within the counting time window, it is asynchronous sampling. Asynchronous sampling has a metastable problem, the minimum sampling error is 1, and the frequency identification accuracy of the above-mentioned automatic frequency control loop is 1, that is, It means that the existing automatic frequency control loop can determine that the equivalent frequency difference between the target clock signal and the local clock signal is at least 1. Then it can be determined that the absolute value of the above formula 1 is at least 2, and the following formula 2 is obtained.

According to Formula 2, it can be seen that the counting time window of the above-mentioned automatic frequency control loop structure is:

Therefore, assuming that the period of the target clock signal Fckv1 is 250 picoseconds (ps) (indicating that the frequency of the local clock signal Fckv1 is 4GHz), if the local clock signal Fckv with a period of 251ps can be identified, divide the local clock signal Fckv by 8. Under the condition, the required counting time window N*Tref ≥ 1us, that is to say, it takes 1us for the automatic frequency control loop to perform one frequency identification, then use the current digital phase-locked loop to achieve the frequency and phase of the local clock signal Fckv to the target It takes at least about 10us to lock the frequency and phase of the clock signal Fckv1.

If it is a phase-locked loop with an analog architecture, the phase-locked loop 201 is non-linear, and the bandwidth of the analog phase-locked loop is usually on the order of 100 kilohertz (kHz), so that the locking time of the analog phase-locked loop 20 is usually Around 50 microseconds (us).

Therefore, the embodiment of the present application provides a frequency and phase detector 400. Referring to Figure 4, the frequency and phase detector 400 can be applied to the phase-locked loop 20 shown in Figure 2. The frequency and phase detector 400 can be used in the phase-locked loop 20 shown in Figure 2. The phase detector 400 is used to generate the voltage control signal Uvco in Figure 2, and when the frequency and phase detector 400 performs frequency and phase identification processing, it consumes at least one order of magnitude faster time and has higher accuracy than the traditional solution. The frequency and phase detector 400 includes: a two-phase synchronous logic circuit 401, a counter 402, a time-to-digital converter 403, and a frequency and phase detector logic circuit 404.

Referring to FIG. 5 , a timing diagram of the frequency and phase detector 400 provided by the embodiment of the present application is shown. The two-phase synchronization logic circuit 401 receives the local clock signal Fckv and the reference clock signal Fref. The period length of the reference clock signal Fref is is greater than the period length of the local clock signal Fckv. After the rising edge of the reference clock signal Fref, the first clock signal Fckv_a is generated according to the first rising edge of the local clock signal Fckv, wherein the rising edge of the first clock signal Fckv_a is not earlier than the first rising edge of the local clock signal Fckv As shown in Figure 5, after the rising edge of the reference clock signal Fref arrives, the first rising edge of the local clock signal Fckv is aligned with the first rising edge of the first clock signal Fckv_a. After the rising edge of the reference clock signal Fref, the second clock signal Fckv_b is generated according to the second rising edge of the local clock signal Fckv, wherein the rising edge of the second clock signal Fckv_b is not earlier than the second rising edge of the local clock signal Fckv edge, as shown in Figure 5, after the rising edge of the reference clock signal Fref arrives, the second rising edge of the local clock signal Fckv is aligned with the first rising edge of the second clock signal Fckv_b; after the rising edge of the reference clock signal Fref After the edge, the third clock signal Fckv_c is generated according to the third rising edge of the local clock signal Fckv, where the rising edge of the third clock signal Fckv_c is not earlier than the third rising edge of the local clock signal Fckv, as shown in Figure 5 , after the rising edge of the reference clock signal Fref arrives, the third rising edge of the local clock signal Fckv is aligned with the first rising edge of the third clock signal Fckv_c.

Exemplarily, the two-phase synchronous logic circuit 401 will also generate the fourth clock signal Fckv_d according to the fourth rising edge of the local clock signal Fckv after the rising edge of the reference clock signal Fref, where the rising edge of the fourth clock signal Fckv_d The edge is not earlier than the fourth rising edge of the local clock signal Fckv. As shown in Figure 5, after the rising edge of the reference clock signal Fref arrives, the fourth rising edge of the local clock signal Fckv is consistent with the fourth rising edge of the fourth clock signal Fckv_d. A rising edge aligns.

The counter 402 is used to determine the first number of complete cycles of the local clock signal Fckv within n cycles of the reference clock signal Fref, where n is a positive integer greater than or equal to 2. Specifically, the counter 402 determines how many integer periods of the local clock signal Fckv are included in n periods of the reference clock signal Fref based on the reference clock signal Fref and the local clock signal Fckv. The integer period of the local clock signal Fckv is the local clock signal. complete cycle.

The time-to-digital converter 403 is used to determine a coefficient based on the second clock signal and the third clock signal. The coefficient is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal; it is also used to determine a coefficient based on the reference clock signal. and the first clock signal, determining a second number of unit steps in incomplete cycles of the local clock signal within n cycles of the reference clock signal. Specifically, the time-to-digital converter 403 quantizes the second clock signal Fckv_b according to the third clock signal Fckv_c in the first cycle of n cycles of the reference clock signal Fref, thereby determining the third clock signal Fckv_c and The phase difference between the second clock signal Fckv_b, and since the rising edge of the second clock signal Fckv_b is aligned with the second rising edge of the local clock signal Fckv after the arrival of the rising edge of the reference clock signal Fref, the third clock signal Fckv_c The rising edge is aligned with the third rising edge of the local clock signal Fckv after the arrival of the rising edge of the reference clock signal Fref. Therefore, the second clock signal The phase difference between Fckv_b and the third clock signal Fckv_c can exactly reflect the length of one cycle of the local clock signal Fckv. Moreover, when the time-to-digital converter 403 determines the length of one cycle of the local clock signal Fckv, its measurement unit is a unit step of the current time-to-digital converter 403, that is, the time-to-digital converter 403 determines the length of the local clock signal Fckv. The length of one cycle of is equal to the unit step size of x is the coefficient determined by the time-to-digital converter. Then, the time-to-digital converter 403 can quantize the reference clock signal Fref according to the first clock signal Fckv_a within n cycles of the reference clock signal Fref, thereby determining the phase between the reference clock signal Fref and the first clock signal Fckv_a. difference, and since the rising edge of the first clock signal is aligned with the first rising edge of the local clock signal Fckv after the rising edge of the reference clock signal Fref arrives, the phase between the reference clock signal Fref and the first clock signal Fckv_a The difference can exactly reflect the number of incomplete cycles of the local clock signal Fckv within n cycles of the reference clock signal Fref. Moreover, the measurement unit of the number of incomplete cycles of the local clock signal Fckv determined by the time-to-digital converter 403 is a unit step of the current time-to-digital converter 403 , that is, the local clock signal Fckv determined by the time-to-digital converter 403 The number of incomplete cycles is equal to y unit steps of the time-to-digital converter 403, where y represents the number of incomplete cycles of the local clock signal within n cycles of the reference clock signal Fref determined by the time-to-digital converter 403. The second number of unit steps.

The frequency and phase detection logic circuit 404 is used to determine the first phase difference between the reference clock signal Fref and the local clock signal Fckv within n cycles of the reference clock signal Fref based on the first quantity, the second quantity, and the coefficient. Specifically, the frequency and phase identification logic circuit 404 determines the third number of complete cycles of the local clock signal corresponding to the second number based on the second number and the coefficient. As mentioned above, the time-to-digital converter 403 determines that within n cycles of the reference clock signal Fref, the number of incomplete cycles of the local clock signal Fckv is equal to y unit steps of the time-to-digital converter, and y represents the incomplete cycles of the local clock signal. The second number of unit steps in a complete cycle. Moreover, the time-to-digital converter 403 also determines that the length of one cycle of the local clock signal Fckv is equal to x unit steps of the time-to-digital converter. 1/x is the coefficient, that is, the unit step of the time-to-digital converter 403 is equal to the unit step of the local clock. The ratio of the length of one cycle of the signal Fckv. It is equal to then that after the frequency and phase detection logic circuit 404 first obtains x and then y, it will calculate the value of y*(1/x), that is, the value of y÷x, and the local clock corresponding to the second number can be determined. The third number of complete cycles of the signal. At the same time, the frequency and phase detection logic circuit 404 can also obtain the first number of complete cycles of the local clock signal Fckv within n cycles of the reference clock signal Fref determined by the counter 402. Then, the frequency and phase detection logic circuit 404 will The first quantity is added to the third quantity to obtain the fourth quantity of complete cycles of the local clock signal within n cycles of the reference clock signal Fref. Then, the frequency and phase detection logic circuit 404 determines the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal based on the reference clock signal and the fourth quantity. For example, the measurement unit of the reference clock signal Fref is one complete cycle of the local clock signal Fckv, and the frequency and phase detection logic circuit 404 can also obtain n cycles of the reference clock signal Fref according to the reference clock signal Fref. The number of complete cycles of the local clock signal Fckv corresponding to the clock signal Fref, then the number of complete cycles of the local clock signal Fckv corresponding to the reference clock signal Fref minus the fourth number, can be determined in n cycles of the reference clock signal Within, the first phase difference between the reference clock signal and the local clock signal.

In the above frequency and phase detector, the two-phase synchronization logic circuit receives the reference clock signal and the local clock signal, and generates the first clock signal according to the first rising edge of the local clock signal after the rising edge of the reference clock signal; After the rising edge of the reference clock signal, the second clock signal is generated according to the second rising edge of the local clock signal. After the rising edge of the reference clock signal, the third clock signal is generated according to the third rising edge of the local clock signal. Furthermore, the counter can determine the first number of complete cycles of the local clock signal within n cycles of the reference clock signal, and the time-to-digital converter can determine the unit steps of the incomplete cycles of the local clock signal within n cycles of the reference clock signal. The second longer number, and the time-to-digital converter can also determine a coefficient. This coefficient is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal. Then, when the frequency identification and phase identification logic circuit receives After reaching the first number, the second number, and the coefficient, the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal Fref can be determined based on the first number, the second number, and the coefficient. For such a frequency and phase detector, due to the existence of the time-to-digital converter, the accuracy of the frequency and phase identification is improved to the ratio of the unit step of the time-to-digital converter to the length of one cycle of the local clock signal, and the time-to-digital conversion The unit step size of the detector is usually on the order of picoseconds (ps). Therefore, when the current frequency and phase detector performs frequency and phase identification processing, it consumes at least one order of magnitude faster time and has higher accuracy than the traditional solution.

Exemplarily, the frequency and phase detection logic circuit 404, after acquiring the fourth number of the local clock signal Fckv within n cycles of the reference clock signal Fref, will also acquire the fourth number of the local clock signal Fckv within n cycles of the next reference clock signal Fref. The fourth number of the local clock signal Fckv, then the difference between the fourth numbers in two adjacent n cycles is obtained, and then the difference is divided by 2 to obtain the frequency of the local clock signal Fckv, then The frequency difference between the local clock signal Fckv and the reference clock signal Fref can be obtained by subtracting the frequency of the local clock signal Fckv from the frequency of the reference clock signal Fref. That is to say, by applying the phase frequency detector 400 provided by the embodiment of the present application in a phase-locked loop, there is no need to set up an additional automatic frequency control loop, and the purpose of frequency identification can be achieved.

It should be noted that when the above-mentioned frequency and phase detector is used to determine the phase difference and/or frequency difference between the target clock signal and the local clock signal, since the target clock signal is determined and the reference clock signal is also determined, the target clock signal There is a fixed ratio relationship with the reference clock signal. Then, after the phase frequency detector determines the phase difference or frequency difference between the reference clock signal and the local clock signal, based on the fixed ratio relationship between the target clock signal and the reference clock signal, Determine the phase difference and/or frequency difference between the target clock signal and the local clock signal.

Exemplarily, referring to Figure 4, the frequency and phase detection logic circuit 404 is also used to receive the reference clock signal Fref, generate the control signal Fctl according to the reference clock signal Fref, and transmit the control signal Fctl to the two-phase synchronous logic circuit 401. Control terminal; Referring to Figure 6, for example, when the frequency and phase detector determines the first phase difference between the reference clock signal Fref and the local clock signal Fckv within 2 cycles of the reference clock signal Fref, the control signal Fctl It is the second level during the first period of the two periods of the reference clock signal Fref, and the control signal Fctl is the first level during the second period of the two periods of the reference clock signal Fref. When the frequency and phase detector determines the first phase difference between the reference clock signal Fref and the local clock signal Fckv within n cycles of the reference clock signal Fref, the control signal Fctl is at the first of n cycles of the reference clock signal Fref. The control signal Fctl is at the second level within n cycles, and the control signal Fctl is at the first level within the second to nth cycles of the n cycles of the reference clock signal Fref. Specifically, the first level may be low level and the second level may be high level, or the first level may be high level and the second level may be low level. The embodiment of the present application does not limit the control signal Fctl.

For the sake of clarity, the following takes the frequency and phase detector to determine the first phase difference between the reference clock signal Fref and the local clock signal Fckv within 2 cycles of the reference clock signal Fref as an example to describe the frequency and phase detection provided by the embodiment of the present application. The two-phase synchronous logic circuit 401 generates the first clock signal Fckv_a, the second clock signal Fckv_b, the third clock signal Fckv_c, and the fourth clock signal Fckv_d.

Among them, since the control signal Fctl generated by the frequency and phase detection logic circuit 404 is the second level in the first cycle of the two cycles of the reference clock signal Fref, It is the first level within 2 cycles.

Then, the two-phase synchronous logic circuit 401 transmits the second clock signal Fckv_b to the time-to-digital converter 403 in the first cycle of the two cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the second level. The data input terminal tdc_in terminal, the third clock signal Fckv_c is transmitted to the clock input terminal tdc_clk terminal of the time-to-digital converter 403, and the fourth clock signal Fckv_d is transmitted to the data input terminal tdc_smp terminal of the time-to-digital converter 403, so that the time The digitizer 403 quantizes the second clock signal Fckv_b according to the third clock signal Fckv_c to determine the coefficient, then samples the coefficient according to the third clock signal Fckv_c, stores the coefficient in the time-to-digital converter 403, and then stores the coefficient The coefficients are transmitted to the frequency and phase detection logic circuit 404.

Then, the two-phase synchronous logic circuit 401 transmits the reference clock signal Fref to the time-to-digital converter 403 in the second cycle of the two cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the first level. The data input terminal tdc_in transmits the first clock signal Fckv_a to the clock input terminal tdc_clk of the time-to-digital converter 403, and transmits the third clock signal Fckv_c to the data input terminal tdc_smp of the time-to-digital converter 403; so that the time digital The converter 403 quantizes the reference clock signal Fref according to the first clock signal Fckv_a, determines the second number of unit steps in the incomplete cycle of the local clock signal within 2 cycles of the reference clock signal, and then quantizes the unit step size according to the third clock signal Fckv_c samples the second quantity, stores the second quantity in the time-to-digital converter 403 , and then transmits the stored second quantity to the frequency and phase detection logic circuit 404 .

The counter 402, in the first cycle of the two cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the second level, samples the first number according to the fourth clock signal Fckv_d, and stores the first number in In the counter 402, the stored first number is then transmitted to the frequency and phase detection logic circuit 404. However, the frequency and phase detection logic circuit 404 does not use the signal received in the first cycle of the two cycles of the reference clock signal Fref. The first quantity arrived. In the second cycle of the two cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the first level, the first number is sampled according to the third clock signal Fckv_c, and the first number is stored in the counter 402 , and then transmit the stored first quantity to the frequency and phase detection logic circuit 404. The frequency and phase detection logic circuit 404 will use the first quantity received in the second cycle of the two cycles of the reference clock signal Fref. Then, since the third clock signal Fckv_c must have a rising edge only after the arrival of a rising edge of the reference clock signal Fref, sampling the first quantity through the third clock signal Fckv_c also makes the frequency and phase detector There is no sampling error in 400.

For example, the counter 402 may not receive the reference clock signal Fref, because the counter will receive the third cycle in the second cycle of the two cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the first level. Clock signal Fckv_c. The third clock signal Fckv_c changes periodically according to the reference clock signal Fref. Therefore, when the counter 402 does not receive the reference clock signal Fref, the first quantity is sampled according to the third clock signal Fckv_c. The first quantity That is, it represents the first number of complete cycles of the local clock signal Fckv within 2 cycles of the reference clock signal Fref.

Therefore, the frequency and phase detection logic circuit 404 receives coefficients within the first cycle of the two cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the second level, within the two cycles of the reference clock signal Fref. In the second cycle of , that is, when the control signal Fctl is at the second level, the first quantity and the second quantity are received, so that the frequency and phase detection logic circuit 404 determines based on the first quantity, the second quantity, and the coefficient. in reference clock Within n cycles of the signal Fref, the first phase difference between the reference clock signal Fref and the local clock signal Fckv.

Illustratively, with reference to FIG. 7 , the embodiment of the present application provides a schematic structural diagram of a two-phase synchronous logic circuit. The two-phase synchronous logic circuit 401 includes: D flip-flop 4010, D flip-flop 4011, D flip-flop 4012. D flip-flop 4013, D flip-flop 4014, delay 4015 and OR gate 4016.

The first input terminal of the two-phase synchronous logic circuit 401 is connected to the clock input terminal clk terminal of the D flip-flop 4010, the set terminal rstn terminal of the D flip-flop 4010, the set terminal rstn terminal of the D flip-flop 4011, and the D flip-flop 4011. The set end rstn end of the D flip-flop 4012, the set end rstn end of the D flip-flop 4013, the set end rstn end of the D flip-flop 4014 and the input end of the delayer 4015. The second input terminal of the two-phase synchronous logic circuit 401 is connected to the first input terminal of the OR gate 4016 . The output terminal of the delay device 4015 is connected to the first output terminal of the two-phase synchronous logic circuit 401 . The data input terminal D of the D flip-flop 4010 is connected to the third level terminal V3, which provides the third level, and the third level is high level; the reverse output terminal of the D flip-flop 4010 terminal is connected to the second input terminal of the OR gate 4016. The output terminal of the OR gate 4016 is connected to the clock input terminal clk terminal of the D flip-flop 4011, the clock input terminal clk terminal of the D flip-flop 4012, the clock input terminal clk terminal of the D flip-flop 4013 and the clock input terminal clk of the D flip-flop 4014. end. The data input terminal D of the D flip-flop 4011 is connected to the third level terminal V3. The forward output terminal Q of the D flip-flop 4011 is connected to the data input terminal D of the D flip-flop 4012 and the third level terminal of the two-phase synchronous logic circuit 401. Two output terminals. The positive output terminal Q terminal of the D selector 4012 is connected to the data input terminal D terminal of the D flip-flop 4013 and the first output terminal of the two-phase synchronous logic circuit 401 . The forward output terminal Q terminal of the D flip-flop 4013 is connected to the data input terminal D terminal of the D flip-flop 4014, the second output terminal of the two-phase synchronous logic circuit 401, and the third output terminal of the two-phase synchronous logic circuit 401. The positive output Q terminal of the D flip-flop 4014 is connected to the third input terminal of the OR gate 4016 and the third output terminal of the two-phase synchronous logic circuit 401 .

The two-phase synchronous logic circuit 401 is configured to receive the reference clock signal Fref from the first input terminal of the two-phase synchronous logic circuit 401 and receive the local clock signal Fckv from the second input terminal of the two-phase synchronous logic circuit 401 .

Referring to FIG. 8 , an embodiment of the present application provides a timing diagram of a two-phase synchronous logic circuit 401 .

The D flip-flop 4010 is used for controlling the reference clock signal Fref received by the setting terminal rstn terminal of the D flip-flop 4010 and the clock input terminal clk terminal, and according to the third voltage received by the data input terminal D terminal of the D flip-flop 4010. The level generates the enable signal Fenb. Among them, since the data input terminal D terminal of the D flip-flop 4010 is connected to the level V3, the level V3 is high level, and the clock input terminal clk terminal and the set terminal rstn terminal of the D flip-flop 4010 receive the reference clock signal Fref, then , when the reference clock signal Fref is low level, the forward output terminal Q terminal of the D flip-flop 4010 outputs a low level, and the reverse output terminal The terminal outputs a high level; when a rising edge of the reference clock signal Fref occurs, the forward output terminal Q terminal of the D flip-flop outputs the high level received from the data input terminal D terminal, and the reverse output terminal terminal output level. Then, the enable signal Fenb generated by the D flip-flop 4010 can be considered as the inverse signal of the reference clock signal Fref, and the enable signal Fenb is delayed by a certain period of time compared to the reference clock signal Fref. This delay is caused by the D flip-flop 4010 of.

The OR gate 4016 is used to perform OR logic processing based on the received enable signal Fenb, the local clock signal Fckv, and the fourth clock signal Fckv_d output from the forward output terminal Q of the D flip-flop 4014 to generate the control clock signal Fck1. Referring to FIG. 8 , when the fourth clock signal Fckv_d is low level, the OR gate 4016 generates the control clock signal Fck1 according to the reception enable signal Fenb and the local reference signal Fckv. Among them, when the reference clock signal Fref is high level, the enable signal Fenb is low level. At this time, the control clock signal Fck1 is synchronized with the local reference signal Fckv, and the control clock signal Fck1 is delayed by a certain amount compared with the local reference signal Fckv. time, This delay is caused by the OR gate 4016 and is a logical delay. During the period when the fourth clock signal Fckv_d is at the high level, the control clock signal Fck1 always remains at the high level.

D flip-flop 4011 is used to control the reference clock signal Fref received at the set end rstn end of the D flip-flop 4011 and the control clock signal Fck1 received at the clock input end clk end of the D flip-flop 4011, according to the D flip-flop 4011 The third level received by the data input terminal D of 4011 generates the first clock signal Fckv_1. Among them, since the data input terminal D of the D flip-flop 4011 is connected to the third level terminal V3, the third level terminal V3 provides a high level, and the clock input terminal clk of the D flip-flop 4011 receives the control clock signal Fck1, the D flip-flop 4011 The set end rstn end of 4011 receives the reference clock signal Fref. Then, when the reference clock signal Fref is low level, the forward output end Q end of the D flip-flop 4011 outputs a low level, and the reverse output end The terminal outputs a high level; when the reference clock signal Fref is a high level and the control clock signal Fck1 has a rising edge, the forward output terminal Q terminal of the D flip-flop outputs the high level received from the data input terminal D terminal. Referring to Figure 8, after the rising edge of the reference clock signal Fref, when the first rising edge of the local clock signal Fckv arrives, the first rising edge of the control clock signal Fck1 appears. Under the trigger of this rising edge, D The first clock signal Fckv_a output by the positive output terminal Q of the flip-flop 4011 delays the first rising edge, and after the rising edge appears, it remains high until the reference clock signal Fref becomes low. is caused by D flip-flop 1011.

The D flip-flop 4012 is used to control the reference clock signal Fref received at the set end rstn end of the D flip-flop 4012 and the control clock signal Fck1 received at the clock input end clk end of the D flip-flop 4012, according to the D flip-flop 4012 The first clock signal Fckv_a received by the data input terminal D of 4012 generates a second clock signal Fckv_b. Among them, since the data input terminal D terminal of the D flip-flop 4012 is connected to the forward output terminal Q terminal of the D flip-flop 4011 and receives the first clock signal Fckv_a, and the clock input terminal clk terminal of the D flip-flop 4012 receives the control clock signal Fck1, The setting terminal rstn of the D flip-flop 4012 receives the reference clock signal Fref. Then, when the reference clock signal Fref is low level, the forward output terminal Q of the D flip-flop 4012 outputs a low level, and the reverse output terminal The terminal outputs a high level; when the reference clock signal Fref is a high level and the control clock signal Fck1 has a rising edge, the forward output terminal Q terminal of the D flip-flop receives the first clock signal Fckv_a from the data input terminal D terminal. . Referring to Figure 8, after the rising edge of the reference clock signal Fref, when the first rising edge of the local clock signal Fckv arrives, the first rising edge of the control clock signal Fck1 appears. Under the trigger of this rising edge, D The first rising edge of the first clock signal Fckv_a output by the positive output terminal Q of the flip-flop 4011 is delayed, and the delay is less than one period of the local clock signal Fckv. Therefore, the first rising edge of the control clock signal Fck1 appears. edge, since the first clock signal Fckv_a is low level, then the second clock signal Fckv_b is also low level. After the rising edge of the reference clock signal Fref, when the second rising edge of the local clock signal Fckv arrives, the control clock signal Fck1 has a second rising edge. At this time, the first clock signal Fckv_a is high level, then the second rising edge The clock signal Fckv_b also has a rising edge, and after the rising edge appears, it remains at a high level until the reference clock signal Fref changes to a low level.

D flip-flop 4013 is used to control the reference clock signal Fref received at the set end rstn end of the D flip-flop 4013 and the control clock signal Fck1 received at the clock input end clk end of the D flip-flop 4013, according to the D flip-flop 4013 The second clock signal Fckv_b received by the data input terminal D of 4013 generates a third clock signal Fckv_c. Among them, since the data input terminal D terminal of the D flip-flop 4013 is connected to the forward output terminal Q terminal of the D flip-flop 4012 and receives the second clock signal Fckv_b, and the clock input terminal clk terminal of the D flip-flop 4013 receives the control clock signal Fck1, The setting terminal rstn of the D flip-flop 4013 receives the reference clock signal Fref. Then, in the reference clock signal Fref When it is low level, the forward output terminal Q of the D flip-flop 4013 outputs a low level, and the reverse output terminal The terminal outputs a high level; when the reference clock signal Fref is a high level and the control clock signal Fck1 has a rising edge, the forward output terminal Q terminal of the D flip-flop receives the second clock signal Fckv_b from the data input terminal D terminal. . Referring to Figure 8, after the rising edge of the reference clock signal Fref, when the first rising edge of the local clock signal Fckv arrives, the control clock signal Fck1 delays a rising edge, then the forward output of the D flip-flop 4011 The first rising edge of the first clock signal Fckv_a output from terminal Q is delayed, and the delay is less than one period of the local clock signal Fckv. At this time, the second clock signal Fckv_b is low level, then the third clock signal Fckv_c It is also low level. After the rising edge of the reference clock signal Fref, when the local clock signal Fckv has a second rising edge, the control clock signal Fck1 also has a second rising edge. The first clock signal Fckv_a is high level, and the second clock signal Fckv_b A rising edge occurs, and the third clock signal Fckv_c is still low level. After the rising edge of the reference clock signal Fref, when the third rising edge of the local clock signal Fckv appears, the control clock signal Fck1 also appears the third rising edge. The first clock signal Fckv_a is high level. At this time, the second clock When the signal Fckv_b is high level, a rising edge appears on the third clock signal Fckv_c, and after the rising edge appears, it remains high level until the reference clock signal Fref becomes low level.

The D flip-flop 4014 is used to control the reference clock signal Fref received at the set end rstn end of the D flip-flop 4014 and the control clock signal Fck1 received at the clock input end clk end of the D flip-flop 4014, according to the D flip-flop 4014. The third clock signal Fckv_c received by the data input terminal D of 4014 generates a fourth clock signal Fckv_d. Among them, since the data input terminal D terminal of the D flip-flop 4014 is connected to the forward output terminal Q terminal of the D flip-flop 4013 and receives the third clock signal Fckv_c, and the clock input terminal clk terminal of the D flip-flop 4014 receives the control clock signal Fck1, The setting terminal rstn of the D flip-flop 4014 receives the reference clock signal Fref. Then, when the reference clock signal Fref is low level, the forward output terminal Q terminal of the D flip-flop 4014 outputs a low level, and the reverse output terminal The terminal outputs a high level; when the reference clock signal Fref is a high level and the control clock signal Fck1 has a rising edge, the forward output terminal Q terminal of the D flip-flop receives the third clock signal Fckv_c from the data input terminal D terminal. . Referring to Figure 8, after the rising edge of the reference clock signal Fref, when a rising edge of the local clock signal Fckv arrives, when the first rising edge of the local clock signal Fckv appears, the control clock signal Fck1 delays to appear a rising edge. edge, then the first clock signal Fckv_a output by the forward output terminal Q of the D flip-flop 4011 is delayed to appear the first rising edge, and the delay is less than one period of the local clock signal Fckv, at this time the second clock signal Fckv_b is low level, the third clock signal Fckv_c is also low level, and the fourth clock signal Fckv_d is also low level. After the rising edge of the reference clock signal Fref, when the local clock signal Fckv has a second rising edge, the control clock signal Fck1 also has a second rising edge. The first clock signal Fckv_a is high level, and the second clock signal Fckv_b When a rising edge occurs, the third clock signal Fckv_c is still low level, and the fourth clock signal Fckv_d is also low level. After the rising edge of the reference clock signal Fref, when the third rising edge of the local clock signal Fckv appears, the control clock signal Fck1 also appears the third rising edge, the first clock signal Fckv_a is high level, and the second clock signal Fckv_b is high level, the third clock signal Fckv_c has a rising edge, and the fourth clock signal Fckv_d is also low level. After the rising edge of the reference clock signal Fref, when the fourth rising edge of the local clock signal Fckv appears, the control clock signal Fck1 also appears the fourth rising edge, the first clock signal Fckv_a is high level, and the second clock signal Fckv_b is high level, the third clock signal Fckv_c is high level, then the fourth clock signal Fckv_d appears a rising edge, and after the rising edge appears, it remains high level until the reference clock signal Fref changes to low level.

7, the forward output Q terminal of the D flip-flop 4014 is also connected to the third input terminal of the OR gate 4016 to receive the fourth clock signal Fckv_d. Then, when the fourth clock signal Fckv_d appears high level , the control clock signal Fck1 clock output by the OR gate 4016 remains high and no rising edge appears. Therefore, the levels output by the positive output terminals of the D flip-flop 4011, D flip-flop 4012, D flip-flop 4013 and D flip-flop 4014 are only controlled by the reference clock signal Fref.

Among them, the delayer 4015 performs delay processing on the reference clock signal Fref to generate a delayed reference clock signal Fref-dly. It can be seen from Figure 8 that the rising edge of the delayed reference clock signal Fref-dly appears after the rising edge of the reference clock signal Fref, and the high-level duration of the delayed reference clock signal Fref-dly is equal to the high-level duration of the reference clock signal Fref. The duration is the same.

Then, the time-to-digital converter 403 is used to determine the local time according to the delayed reference clock signal Fref-dly and the first clock signal Fckv_a in the second to nth cycles within n cycles of the reference clock signal Fref. The second number of unit steps in the incomplete cycle of the clock signal Fckv. Among them, the reference clock signal Fref is delayed to generate the delayed reference clock signal Fref_dly. The primary purpose of the delay 4015 is to compensate the delay of the D flip-flop 4010 and the OR gate 4016, so that the delayed reference clock signal Fref_dly is compared with The delay time of the reference clock signal Fref is the same as the delay time of the first rising edge of the local clock signal Fckv after the first clock signal Fckv_a is compared with the rising edge of the reference clock signal. The secondary purpose of the delay 4015 is to obtain a measurable second number of unit steps in the incomplete cycle of the local clock signal Fckv.

Referring to Figure 9, the two-phase synchronous logic circuit 401 also includes a selector 4017, a selector 4018 and a selector 4019; the control end of the two-phase synchronous logic circuit 401 is connected to the control end of the selector 4017 and the control end of the selector 4018. terminal and the control terminal of the selector 4019; the first input terminal of the selector 4017 is connected to the output terminal of the delay device 4015, and the second input terminal of the selector 4017 is connected to the positive output terminal of the D flip-flop 4012. The selector 4017 The output terminal is connected to the first output terminal of the two-phase synchronous logic circuit 401; the first input terminal of the selector 4018 is connected to the forward output terminal of the D flip-flop 4011, and the second input terminal of the selector 4018 is connected to the D flip-flop 4011. The positive output terminal of 4013 and the output terminal of selector 4018 are connected to the second output terminal of the two-phase synchronous logic circuit 401; the first input terminal of selector 4019 is connected to the positive output terminal of D flip-flop 4013 and the selector 4019 The second input terminal is connected to the positive output terminal of the D flip-flop 4014, and the output terminal of the selector 4019 is connected to the third output terminal of the two-phase synchronous logic circuit 401; the two-phase synchronous logic circuit 401 receives the frequency discrimination from the control terminal The control signal Fctl generated by the phase detection logic circuit 404.

Referring to FIG. 8 , the two-phase synchronous logic circuit 401 will, in the first cycle of n cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the second level (that is, high level). The second clock signal Fckv_b is transmitted to the first output terminal of the two-phase synchronous logic circuit 401; the third clock signal Fckv_c is transmitted to the second output terminal of the two-phase synchronous logic circuit 401; the fourth clock signal Fckv_d is transmitted to the two-phase synchronous logic circuit 401. The third output terminal of the logic circuit 401. Referring to Figure 4, the data input terminal tdc_in of the time-to-digital converter 403 is connected to the first output terminal of the two-phase synchronous logic circuit 401, and the clock input terminal tdc_clk of the time-to-digital converter 403 is connected to the two-phase synchronous logic. The second output terminal of the circuit 401 and the sampling input terminal tdc_smp terminal of the time-to-digital converter 403 are connected to the third output terminal of the two-phase synchronous logic circuit 401. Then, in the first cycle within n cycles of the reference clock signal Fref , that is, when the control signal Fctl is at the second level (that is, high level), the time-to-digital converter 403 receives the second clock signal Fckv_b from the data input terminal tdc_in, and receives the third clock signal from the clock input terminal tdc_clk. Fckv_c, the self-sampling input terminal tdc_smp terminal receives the Four clock signals Fckv_d, then the time-to-digital converter 403 determines a coefficient based on the second clock signal Fckv_b and the third clock signal Fckv_c. The coefficient is the ratio of the unit step size of the time-to-digital converter 403 to the length of one cycle of the local clock signal. More specifically, the time-to-digital converter 403 quantizes the second clock signal Fckv_b according to the third clock signal Fckv_c to determine the coefficient, and then samples the coefficient according to the third clock signal Fckv_c, and stores the coefficient in the time-to-digital converter 403 , and then transmit the stored coefficients to the frequency and phase detection logic circuit 404.

The two-phase synchronous logic circuit 401 will delay the delay from the 2nd cycle to the nth cycle within n cycles of the reference clock signal Fref, that is, when the control signal Fctl is at the first level (ie, low level). The reference clock signal Fref_dly is transmitted to the first output end of the two-phase synchronous logic circuit 401; the selector 4018 transmits the first clock signal Fckv_a to the two-phase when the control signal Fctl is the first level (that is, low level). The second output terminal of the synchronous logic circuit 401; the selector 4019 transmits the third clock signal Fckv_c to the third output terminal of the two-phase synchronous logic circuit 401 when the control signal Fctl is a first level (that is, a low level). . Referring to Figure 4, the data input terminal tdc_in of the time-to-digital converter 403 is connected to the first output terminal of the two-phase synchronous logic circuit 401, and the clock input terminal tdc_clk of the time-to-digital converter 403 is connected to the two-phase synchronous logic. The second output terminal of the circuit 401 , the sampling input terminal tdc_smp terminal of the time-to-digital converter 403 is connected to the third output terminal of the two-phase synchronous logic circuit 401 . Then, in the second to nth cycles within n cycles of the reference clock signal Fref, that is, when the control signal Fctl is the first level (ie, low level), the time-to-digital converter 403 The input terminal tdc_in receives the delayed reference clock signal Fref_dly, receives the first clock signal Fckv_a from the clock input terminal tdc_clk, and receives the third clock signal Fckv_c from the sampling input terminal tdc_smp. The time-to-digital converter 403 responds to the delayed reference clock signal Fref_dly. The second number of unit steps in the incomplete cycles of the local clock signal within n cycles of the reference clock signal is determined with the first clock signal Fckv_a. More specifically, the time-to-digital converter 403 quantizes the delayed reference clock signal Fref_dly according to the first clock signal Fckv_a, and determines the second unit step of the incomplete cycle of the local clock signal within n cycles of the reference clock signal. quantity, and then samples the second quantity according to the third clock signal Fckv_c, stores the second quantity in the time-to-digital converter 403, and then transmits the stored second quantity to the frequency and phase detection logic circuit 404.

For example, the two-phase synchronous logic circuit in the frequency and phase detector 400 is the two-phase synchronous logic circuit 401 shown in Figure 9, and the counter 402 in the frequency and phase detector 400 is a counter implemented by the analog design method, then The frequency and phase detector 400 does not need to frequency divide the local clock signal Fckv, so the frequency and phase detector 400 determines the frequency difference between the target clock signal Fckv1 and the local clock signal Fckv according to the following formula 4:

Among them, the frequency identification accuracy of the frequency and phase detector 400 is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal, and overcomes the metastable problem of asynchronous sampling. Therefore, the above formula 4 The minimum value is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal, resulting in Equation 5 below.

Among them, in the above equation 5, Ltdc represents the unit step of the time-to-digital converter.

According to Formula 5, it can be seen that a counting time window of the above-mentioned frequency and phase detector 400 is:

Therefore, assuming that the period of the target clock signal Fckv1 is 250 picoseconds (ps) (meaning that the frequency of the local clock signal Fckv1 is 4GHz) and the unit step of the time-to-digital converter is 10ps, if the local clock signal Fckv with the period of 251ps can be identified , the required counting time window N*Tref≥2.5 nanoseconds (ns), the frequency and phase detector requires 2.5ns for 4001 times of frequency identification, then the frequency and phase detector provided by the embodiment of the present application is performing frequency and phase identification processing At this time, the time consumed is increased by 400 times compared with the traditional solution.

Refer to Figure 10. The embodiment of the present application provides a schematic structural diagram of a phase-locked loop 50. The phase-locked loop 50 includes a filter 501, an oscillation circuit 502 and a frequency and phase detector 400; wherein the frequency and phase detector 400 is connected through the filter 501 To the oscillation circuit 502, the oscillation circuit 502 is also connected to the frequency and phase detector 400; the frequency and phase detector 400 receives the reference clock signal Fref, the local clock signal Fckv generated by the oscillation circuit 502, and the target clock signal Fckv1. According to the reference clock signal Fref and the local clock signal Fckv determine the phase difference between the reference clock signal Fref and the local clock signal Fckv within n cycles of the reference clock signal Fref. Moreover, the current frequency and phase detector also receives the target clock signal. The target clock signal is determined, and the target clock signal Fckv1 has a fixed ratio relationship with the reference clock signal Fref. Then according to n cycles of the reference clock signal Fref, The phase difference between the reference clock signal Fref and the local clock signal Fckv, and the target clock signal Fckv1 and the reference clock signal Fref must have a fixed ratio relationship. It can be known that within n cycles of the reference clock signal Fref, the target clock signal Fckv1 and the local clock The phase difference of the signal Fckv. According to the phase difference between the target clock signal Fckv1 and the local clock signal Fckv, a voltage control signal can be generated and transmitted to the filter 501 .

For example, the frequency and phase detector 400 may not receive the target clock signal Fckv1, but instead receive the target clock signal Fckv1 and the reference clock signal Fref, which must have a fixed ratio relationship.

The filter 501 receives the voltage control signal and generates the control voltage of the oscillation circuit 502 according to the voltage control signal; the oscillation circuit 502 receives the control voltage and adjusts the frequency of the local clock signal Fckv generated by the oscillation circuit 502 under the control of the control voltage.

The oscillator circuit 502 may include a voltage-controlled oscillator or a current-controlled oscillator. As shown in FIG. 11 , the current-controlled oscillator includes an oscillator 5021 and four transistors. For example, as shown in FIG. 11 The transistor is a hole-type metal-oxide-semiconductor field effect transistor (MOSFET, PMOS transistor for short), in which the first end of the PMOS transistor P1 is connected to the level V4 end through the resistor R1. The level V4 terminal provides a high level. The second terminal of the PMOS tube P1 is connected to the first terminal of the PMOS tube P2. The second terminal of the PMOS tube P2 is connected to the control terminal of the oscillator 5021. The control terminal of the PMOS tube P1 receives the voltage. When the level signal U1 is low level, the first end and the second end of the PMOS tube P1 are turned on. When the level signal U1 is high level, the first end and the second end of the PMOS tube P1 are turned on. terminal is not conductive, the control terminal of the PMOS tube P2 receives the level signal U2. When the level signal U2 is low level, the first terminal and the second terminal of the PMOS tube P2 are conductive. When the level signal U2 is high, When the level is high, the first end and the second end of the PMOS tube P2 are not conductive; the first end of the PMOS tube P3 is connected to the level V4 end through a resistor. The level V4 end provides a high level, and the second end of the PMOS tube P3 The terminal is connected to the first terminal of the PMOS tube P4, the second terminal of the PMOS tube P4 is connected to the control terminal of the oscillator 5021, and the control terminal of the PMOS tube P3 receives the level signal U3. When the level signal U3 is low level, The first end and the second end of the PMOS transistor P3 are conductive. When the level signal U3 is high level, the first end and the second end of the PMOS transistor P3 are not conductive, and the control end of the PMOS transistor P4 receives the level signal. U4, when the level signal U4 is low level, the first end and the second end of the PMOS tube P4 are turned on. When the level signal U5 is high level, the first end and the second end of the PMOS tube P4 are not connected. conduction.

In the oscillator circuit shown in Figure 11, the level signal U1 and the level signal U3 are always low level to control the opening of the PMOS tube P1 and the PMOS tube P3. The control voltage transmitted by the filter 501 can control the level signal U2 The sum level signal U4 is high level or low level, thereby controlling the opening or closing of the PMOS transistor P2 and the PMOS transistor P4. Within a certain period of time, the number of times that the PMOS transistor P2 and the PMOS transistor P4 are turned on and off will cause the oscillator 5021 to receive different control currents, so that the phase and/or frequency of the local clock signal Fckv generated by the oscillator 5021 changes.

Illustratively, embodiments of the present application provide an electronic device, which includes a printed circuit board (PCB), a phase-locked loop disposed on the PCB, or a frequency identification device disposed on the PCB. Phase detector, the phase-locked loop may be the above-mentioned phase-locked loop 50, and the frequency-frequency phase detector may be the above-mentioned frequency-phase detector 400. The electronic devices include, for example, mobile phones, tablet computers, personal digital assistants (personal digital assistants, PDAs), vehicle-mounted computers, etc. The embodiments of the present application do not place any special restrictions on the specific form of the electronic device.

Illustratively, the embodiment of the present application provides a frequency and phase identification method, including:

Receive local clock signal and reference clock signal.

Wherein, the period length of the reference clock signal is greater than the period length of the local clock signal; and after the rising edge of the reference clock signal, the first clock signal is generated according to the first rising edge of the local clock signal, wherein the rising edge of the first clock signal The rising edge of the second clock signal is not earlier than the first rising edge of the local clock signal; after the rising edge of the reference clock signal, the second clock signal is generated according to the second rising edge of the local clock signal, where the rising edge of the second clock signal is not earlier than the rising edge of the local clock signal. on the second rising edge of the local clock signal; after the rising edge of the reference clock signal, generate a third clock signal based on the third rising edge of the local clock signal, wherein the rising edge of the third clock signal is not earlier than the local clock The third rising edge of the signal.

In some cases, the fourth clock signal is also generated according to the fourth rising edge of the local clock signal after the rising edge of the reference clock signal, wherein the rising edge of the fourth clock signal is not earlier than the fourth rising edge of the local clock signal. a rising edge.

Specifically, the above-mentioned first clock signal, second clock signal, third clock signal and fourth clock signal can be generated according to the following steps: under the control of the reference clock signal, generate an enable signal according to the third level; The received enable signal, local clock signal and fourth clock signal are OR logically processed to generate a control clock signal; under the control of the reference clock signal and the control clock signal, a first clock signal is generated according to the third level; in the reference Under the control of the clock signal and the control clock signal, a second clock signal is generated according to the first clock signal; under the control of the reference clock signal and the control clock signal, a third clock signal is generated according to the second clock signal; under the control of the reference clock signal , and under the control of the control clock signal, generate a fourth clock signal according to the third clock signal; perform delay processing on the reference clock signal to generate a delayed reference clock signal; then determine the reference clock according to the reference clock signal and the first clock signal Within n cycles of the signal, the second number of unit steps in the incomplete cycle of the local clock signal specifically includes: determining, based on the delayed reference clock signal and the first clock signal, within n cycles of the reference clock signal, the local The second number of unit steps in an incomplete cycle of a clock signal.

Determine the first number of complete cycles of the local clock signal within n cycles of the reference clock signal, where n is a positive integer greater than or equal to 2. For example, when the control signal is at the first level, the first number is sampled according to the third clock signal, and the first number is stored.

A coefficient is determined based on the second clock signal and the third clock signal, and the coefficient is a ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal. For example, when the control signal is at the second level, the root The coefficients are sampled according to the fourth clock signal and stored.

A second number of unit steps in incomplete cycles of the local clock signal within n cycles of the reference clock signal is also determined based on the reference clock signal and the first clock signal. For example, when the control signal is at the first level, the second quantity is sampled according to the third clock signal, and the second quantity is stored.

According to the first quantity, the second quantity, and the coefficient, a first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal is determined.

Exemplarily, based on the first quantity, the second quantity, and the coefficient, determining the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal specifically includes: according to the second quantity and the coefficient, Determine the third number of complete cycles of the local clock signal corresponding to the second number; add the first number to the third number to obtain the fourth number of complete cycles of the local clock signal within n cycles of the reference clock signal; according to The reference clock signal and the fourth quantity determine the first phase difference between the reference clock signal and the local clock signal within n cycles of the reference clock signal.

In other embodiments, the second phase difference is also determined based on the fourth number within n cycles and the fourth number within the next n cycles; the frequency of the local clock signal is determined based on the second phase difference. Then, based on the difference between the frequency of the reference clock signal and the frequency of the local clock signal, the frequency difference between the reference clock signal and the local clock signal can be obtained.

Wherein, the above control signal is generated according to the following steps: receiving a reference clock signal, generating a control signal according to the reference clock signal, the control signal is the second level in the first period of the reference clock signal; the control signal is in the second period of the reference clock signal. It is the first level within the period from the nth period to the nth period.

Embodiments of the present application also provide a computer-readable storage medium that stores computer program code. When the electronic device executes the computer program code, the electronic device executes the integrated circuit testing method in the above embodiment. Based on this understanding, the technical solutions of the embodiments of the present application are essentially or contribute to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium , including several instructions to cause a device (which can be a microcontroller, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code.

Embodiments of the present application also provide a computer program product. When the computer program product is run on an electronic device, it causes the electronic device to perform the above related steps to implement the integrated circuit testing method in the above embodiment.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be The combination can either be integrated into another device, or some features can be omitted, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated. The components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be separated. Distributed to many different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a readable storage medium. The above contents are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, and should are covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Although the invention has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are intended to be illustrative only of the invention as defined by the appended claims and are to be construed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the invention. In this way, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

A frequency and phase detector, characterized in that it includes: a two-phase synchronous logic circuit, a counter, a time-to-digital converter, and a frequency and phase detector logic circuit;

The two-phase synchronous logic circuit is used to receive a local clock signal and a reference clock signal. The period length of the reference clock signal is greater than the period length of the local clock signal; after the rising edge of the reference clock signal, according to the The first rising edge of the local clock signal generates the first clock signal, wherein the rising edge of the first clock signal is no earlier than the first rising edge of the local clock signal; after the rising edge of the reference clock signal After the edge of the local clock signal, a second clock signal is generated according to the second rising edge of the local clock signal, wherein the rising edge of the second clock signal is not earlier than the second rising edge of the local clock signal; in the After the rising edge of the reference clock signal, a third clock signal is generated according to the third rising edge of the local clock signal, wherein the rising edge of the third clock signal is no earlier than the third rising edge of the local clock signal. along;

The counter is used to determine the first number of complete cycles of the local clock signal within n cycles of the reference clock signal, where n is a positive integer greater than or equal to 2;

The time-to-digital converter is used to determine a coefficient based on the second clock signal and the third clock signal, where the coefficient is the unit step of the time-to-digital converter and one cycle of the local clock signal. The ratio of the length; also used to determine the unit step size in the incomplete cycle of the local clock signal within the n cycles of the reference clock signal based on the reference clock signal and the first clock signal. second quantity;

The frequency and phase identification logic circuit is used to determine, according to the first quantity, the second quantity, and the coefficient, within the n periods of the reference clock signal, the difference between the reference clock signal and The first phase difference of the local clock signal.
The frequency and phase detector according to claim 1, characterized in that the frequency and phase detection logic circuit is specifically used to determine the second number corresponding to the second number according to the second number and the coefficient. the third number of complete cycles of the local clock signal;

Adding the first number to the third number yields a fourth number of complete cycles of the local clock signal within the n cycles of the reference clock signal;

According to the reference clock signal and the fourth quantity, a first phase difference between the reference clock signal and the local clock signal within the n periods of the reference clock signal is determined.
The frequency and phase detector according to claim 2, characterized in that the frequency and phase detection logic circuit is also used to determine the fourth number in the n cycles and the next n The fourth number within the period determines a second phase difference; the frequency of the local clock signal is determined based on the second phase difference.
The frequency and phase detector according to any one of claims 1-3, characterized in that:

The two-phase synchronous logic circuit generates a fourth clock signal according to the fourth rising edge of the local clock signal after the rising edge of the reference clock signal, wherein the rising edge of the fourth clock signal is not earlier than the rising edge of the reference clock signal. On the fourth rising edge of the local clock signal;

The two-phase synchronous logic circuit is also used to control the control signal generated by the frequency identification and phase identification logic circuit received at the control end of the two-phase synchronous logic circuit. When the control signal is at the first level, the The reference clock signal is transmitted to the data input terminal of the time-to-digital converter, the first clock signal is transmitted to the clock input terminal of the time-to-digital converter, and the third clock signal is transmitted to the time digital converter. The sampling input terminal of the converter; when the control signal is at the second level, transmit the second clock signal to the time-to-digital converter The data input terminal transmits the third clock signal to the clock input terminal of the time-to-digital converter, and transmits the fourth clock signal to the sampling input terminal of the time-to-digital converter.
The frequency and phase detector according to claim 1, wherein the two-phase synchronous logic circuit includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop. , fifth D flip-flop, delayer, and OR gate;

The first input end of the two-phase synchronous logic circuit is connected to the clock input end of the first D flip-flop, the set end of the first D flip-flop, the set end of the second D flip-flop, The setting terminal of the third D flip-flop, the setting terminal of the fourth D flip-flop, the setting terminal of the fifth D flip-flop and the input terminal of the delayer;

The second input terminal of the two-phase synchronous logic circuit is connected to the first input terminal of the OR gate;

The output terminal of the delayer is connected to the first output terminal of the two-phase synchronous logic circuit;

The data input terminal of the first D flip-flop is connected to a third level terminal, and the reverse output terminal of the first D flip-flop is connected to the second input terminal of the OR gate, wherein the third level terminal provides third level;

The output terminal of the OR gate is connected to the clock input terminal of the second D flip-flop, the clock input terminal of the third D flip-flop, the clock input terminal of the fourth D flip-flop and the fifth D flip-flop. The clock input of the flip-flop;

The data input terminal of the second D flip-flop is connected to the third level terminal, and the positive output terminal of the second D flip-flop is connected to the data input terminal of the third D flip-flop and the two-phase a second output terminal of the synchronous logic circuit;

The forward output terminal of the third D flip-flop is connected to the data input terminal of the fourth D flip-flop and the first output terminal of the two-phase synchronous logic circuit;

The positive output terminal of the fourth D flip-flop is connected to the data input terminal of the fifth D flip-flop, the second output terminal of the two-phase synchronous logic circuit, and the third output of the two-phase synchronous logic circuit. end;

The positive output terminal of the fifth D flip-flop is connected to the third input terminal of the OR gate and the third output terminal of the two-phase synchronous logic circuit;

The two-phase synchronous logic circuit is configured to receive the reference clock signal from the first input terminal of the two-phase synchronous logic circuit and receive the local clock signal from the second input terminal of the two-phase synchronous logic circuit;

The first D flip-flop is configured to receive a signal at the data input end of the first D flip-flop under the control of the reference clock signal received by the setting end of the first D flip-flop and the clock input end. The third level generates an enable signal;

The OR gate is used to perform logical OR processing on the received enable signal, the local clock signal and the fourth clock signal output by the forward output terminal of the fifth D flip-flop to generate a control clock signal;

The second D flip-flop is used to adjust the reference clock signal received at the set end of the second D flip-flop and the control clock signal received at the clock input end of the second D flip-flop. Under control, generate the first clock signal according to the third level received by the data input terminal of the second D flip-flop;

The third D flip-flop is used to adjust the reference clock signal received at the set end of the third D flip-flop and the control clock signal received at the clock input end of the third D flip-flop. Under control, generate the second clock signal according to the first clock signal received by the data input terminal of the third D flip-flop;

The fourth D flip-flop is used to adjust the reference clock signal received at the set end of the fourth D flip-flop and the control clock signal received at the clock input end of the fourth D flip-flop. Under control, generate the third clock signal according to the second clock signal received by the data input terminal of the fourth D flip-flop;

The fifth D flip-flop is used to adjust the reference clock signal received at the set end of the fifth D flip-flop and the control clock signal received at the clock input end of the fifth D flip-flop. Under control, generate the fourth clock signal according to the third clock signal received by the data input terminal of the fifth D flip-flop;

The delayer is used to delay the reference clock signal and generate a delayed reference clock signal;

The time-to-digital converter is specifically configured to determine, based on the delayed reference clock signal and the first clock signal, the unit in the incomplete cycle of the local clock signal within n cycles of the reference clock signal. The second number of steps.
The frequency and phase detector according to claim 5, characterized in that:

The two-phase synchronous logic circuit also includes a first selector, a second selector and a third selector;

The control terminal of the two-phase synchronous logic circuit is connected to the control terminal of the first selector, the control terminal of the second selector and the control terminal of the third selector;

The first input terminal of the first selector is connected to the output terminal of the delay device, the second input terminal of the first selector is connected to the positive output terminal of the third D flip-flop, and the The output terminal of the second selector is connected to the first output terminal of the two-phase synchronous logic circuit;

The first input terminal of the second selector is connected to the positive output terminal of the second D flip-flop, and the second input terminal of the second selector is connected to the positive output terminal of the fourth D flip-flop. terminal, the output terminal of the second selector is connected to the second output terminal of the two-phase synchronous logic circuit;

The first input terminal of the third selector is connected to the positive output terminal of the fourth D flip-flop, and the second input terminal of the third selector is connected to the positive output terminal of the fifth D flip-flop. terminal, the output terminal of the third selector is connected to the third output terminal of the two-phase synchronous logic circuit;

The two-phase synchronous logic circuit receives the control signal generated by the frequency and phase detection logic circuit from the control end of the two-phase synchronous logic circuit;

The first selector transmits the delay reference signal to the data input end of the time-to-digital converter through the first output end of the two-phase synchronous logic circuit when the control signal is a first level; When the control signal is at the second level, transmit the second clock signal to the data input end of the time-to-digital converter through the first output end of the two-phase synchronous logic circuit;

The second selector transmits the first clock signal to the clock input of the time-to-digital converter through the second output end of the two-phase synchronous logic circuit when the control signal is the first level. terminal; when the control signal is the second level, transmit the third clock signal to the clock input terminal of the time-to-digital converter through the second output terminal of the two-phase synchronous logic circuit;

The third selector transmits the third clock signal to the sampling input of the time-to-digital converter through the third output end of the two-phase synchronous logic circuit when the control signal is the first level. terminal; when the control signal is the second level, the fourth clock signal is transmitted to the sampling input terminal of the time-to-digital converter through the third output terminal of the two-phase synchronous logic circuit.
The frequency and phase detector according to any one of claims 1 to 6, characterized in that the counter is also used to: when the control signal generated by the frequency and phase detection logic circuit is at the first level, according to the The third clock signal samples the first number and stores the first number in the counter.
The frequency and phase detector according to any one of claims 1 to 6, characterized in that the time-to-digital converter is also used when the control signal generated by the frequency and phase detection logic circuit is at the first level. , according to the third time The clock signal samples the second quantity and the second quantity is stored in the time-to-digital converter.
The frequency and phase detector according to any one of claims 4 to 6, characterized in that the time-to-digital converter is further configured to, when the control signal is the second level, generate the signal according to the fourth level when the control signal is the second level. The clock signal samples the coefficients, which are stored in the time-to-digital converter.
The frequency and phase detector according to any one of claims 1-9, characterized in that:

The frequency and phase identification logic circuit is also used to receive the reference clock signal and generate a control signal according to the reference clock signal. The control signal is the second level in the first cycle of the reference clock signal. ; The control signal is the first level within the 2nd cycle to the nth cycle of the reference clock signal.
A phase-locked loop, characterized in that the phase-locked loop includes a filter, an oscillation circuit and a frequency and phase detector according to any one of claims 1-10;

The frequency and phase detector is connected to the oscillation circuit through the filter, and the oscillation circuit is also connected to the frequency and phase detector;

The frequency and phase detector receives a reference clock signal, a local clock signal generated by the oscillator circuit, and a target clock signal, and determines the target based on the reference clock signal, the local clock signal, and the target clock signal. A third phase difference between the clock signal and the local clock signal within n cycles of the reference clock signal, and generating a voltage control signal according to the third phase difference;

The filter receives the voltage control signal and generates a control voltage of the oscillation circuit according to the voltage control signal;

The oscillation circuit receives the control voltage and adjusts the frequency of the local clock signal generated by the oscillation circuit under the control of the control voltage.
An electronic device, characterized in that the electronic device includes a printed circuit board, and further includes: a phase-locked loop as claimed in claim 11 disposed on the printed circuit board, or disposed on the printed circuit board The frequency and phase detector according to any one of claims 1-10.
A frequency and phase identification method, which is characterized by including:

Receive a local clock signal and a reference clock signal; the period length of the reference clock signal is greater than the period length of the local clock signal; after the rising edge of the reference clock signal, according to the first rising edge of the local clock signal Generate a first clock signal, wherein the rising edge of the first clock signal is no earlier than the first rising edge of the local clock signal; after the rising edge of the reference clock signal, according to the The second rising edge generates a second clock signal, wherein the rising edge of the second clock signal is no earlier than the second rising edge of the local clock signal; after the rising edge of the reference clock signal, according to the The third rising edge of the local clock signal generates a third clock signal, wherein the rising edge of the third clock signal is no earlier than the third rising edge of the local clock signal;

Determine the first number of complete cycles of the local clock signal within n cycles of the reference clock signal, where n is a positive integer greater than or equal to 2;

A coefficient is determined according to the second clock signal and the third clock signal, and the coefficient is the ratio of the unit step size of the time-to-digital converter to the length of one cycle of the local clock signal; also according to the reference The clock signal and the first clock signal determine the second number of unit steps in the incomplete cycles of the local clock signal within the n cycles of the reference clock signal;

According to the first quantity, the second quantity, and the coefficient, it is determined that the value of the reference clock signal is Within the n periods, the first phase difference between the reference clock signal and the local clock signal.
The frequency and phase identification method according to claim 13, characterized in that, according to the first quantity, the second quantity, and the coefficient, it is determined that in the n periods of the reference clock signal Within, the first phase difference between the reference clock signal and the local clock signal specifically includes:

Determine a third number of complete cycles of the local clock signal corresponding to the second number according to the second number and the coefficient;

Adding the first number to the third number yields a fourth number of complete cycles of the local clock signal within the n cycles of the reference clock signal;

According to the reference clock signal and the fourth quantity, a first phase difference between the reference clock signal and the local clock signal within the n periods of the reference clock signal is determined.
The method of frequency and phase identification according to claim 14, further comprising:

Determine a second phase difference according to the fourth number within the n cycles and the fourth number within the next n cycles; determine the local clock signal according to the second phase difference. frequency.
The frequency and phase identification method according to any one of claims 13-15, characterized in that:

After receiving the local clock signal and the reference clock signal, the method further includes: after the rising edge of the reference clock signal, generating a fourth clock signal according to the fourth rising edge of the local clock signal, wherein the fourth The rising edge of the clock signal is no earlier than the fourth rising edge of the local clock signal.
The frequency and phase identification method according to claim 13, characterized in that after receiving the local clock signal and the reference clock signal, it includes:

Under the control of the reference clock signal, generate an enable signal according to the third level;

Perform logical OR processing on the received enable signal, the local clock signal and the fourth clock signal to generate a control clock signal;

Under the control of the reference clock signal and the control clock signal, generate the first clock signal according to the third level;

Under the control of the reference clock signal and the control clock signal, generate the second clock signal according to the first clock signal;

Under the control of the reference clock signal and the control clock signal, generate the third clock signal according to the second clock signal;

Under the control of the reference clock signal and the control clock signal, generate the fourth clock signal according to the third clock signal;

Perform delay processing on the reference clock signal to generate a delayed reference clock signal;

Then, according to the reference clock signal and the first clock signal, determine the second number of unit steps in the incomplete cycles of the local clock signal within the n cycles of the reference clock signal, Specifically include:

According to the delayed reference clock signal and the first clock signal, a second number of unit steps in incomplete cycles of the local clock signal within n cycles of the reference clock signal is determined.
The frequency and phase identification method according to any one of claims 13 to 17, further comprising: when the control signal is at the first level, sampling the first quantity according to the third clock signal, Store the first quantity.
The frequency and phase identification method according to any one of claims 13 to 17, characterized in that it further includes: in the control When the clock signal is at the first level, the second quantity is sampled according to the third clock signal, and the second quantity is stored.
The frequency and phase identification method according to claim 16 or 17, further comprising: when the control signal is at the second level, sampling the coefficient according to the fourth clock signal, and storing the coefficient .
The frequency and phase identification method according to any one of claims 13-20, characterized in that,

It also includes: receiving the reference clock signal, generating a control signal according to the reference clock signal, the control signal being a second level in the first cycle of the reference clock signal; The clock signal is at the first level from the 2nd cycle to the nth cycle.
A computer-readable storage medium, characterized in that it includes computer instructions. When the computer instructions are run on an electronic device, the electronic device causes the electronic device to perform frequency identification as described in any one of claims 13-21. phase method.
A computer program product, characterized in that, when the computer program product is run on an electronic device, it causes the electronic device to execute the frequency and phase identification method as described in any one of claims 13-21.