CN113411081A

CN113411081A - Frequency discriminator for phase-locked loop and phase-locked loop

Info

Publication number: CN113411081A
Application number: CN202110904052.1A
Authority: CN
Inventors: 邹勇贤
Original assignee: Mico Microelectronics Shenzhen Co ltd
Current assignee: Xiamen Hexin Semiconductor Co ltd
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2021-09-17

Abstract

The application relates to a frequency identifier of a phase-locked loop and the phase-locked loop, the frequency identifier comprises: the capture signal circuit is used for capturing the signal edge of the standard clock signal and generating a capture signal; the standard clock signal has a standard number of cycles; the signal counting circuit is used for counting the oscillation clock signals under the triggering of the capture signals to obtain the number of oscillation cycles; a number comparison circuit for comparing the number of oscillation cycles with a standard cycle range, the standard cycle range being dependent on the product of the phase-locked loop multiplied frequency and the standard cycle number; wherein the number of oscillation cycles is within the standard cycle range indicating authentication pass. The method and the device identify the oscillation clock signals in the phase-locked loop in a counting mode, are not easily influenced by environment or circuit process, and are accurate in identification result.

Description

Frequency discriminator for phase-locked loop and phase-locked loop

Technical Field

The application belongs to the technical field of electronics, and particularly relates to a frequency identifier of a phase-locked loop and the phase-locked loop.

Background

The phase-locked loop in the electronic technology is a negative feedback system, the output of a voltage-controlled oscillator in a feedback loop is divided by a frequency divider (1/F times) to a lower frequency (fCLK _ FBK), and then a frequency phase difference signal is generated by comparing a Phase Frequency Detector (PFD) with a reference clock (fCLK _ REF), then the difference signal is adopted to be processed in a forward path through a charge pump and a loop filter to generate a voltage or current signal, finally the voltage or current signal is used for controlling the voltage-controlled oscillator, and the frequency (fCLK _ VCO) of the voltage-controlled oscillator is driven to approach a target frequency. In the process, a difference signal obtained by a Phase Frequency Detector (PFD) is the difference between the target frequency and the reference frequency, the phase-locked loop continuously adjusts the frequency of the voltage-controlled oscillator according to the difference signal, and finally the output clock of the voltage-controlled oscillator generated by the loop is locked at F times of the frequency of the reference clock.

A Phase Frequency Detector (PFD) takes two clock signals as input and outputs a frequency phase difference between the two. In the phase-locked loop, the phase difference between the reference clock and the feedback clock is compared and obtained, and then the error signal is converted into a form which can be processed by a subsequent voltage-controlled oscillator through a charge pump + loop filter, such as a voltage signal or a current signal, so as to finally control the frequency output of the oscillator.

The current Phase Frequency Detector (PFD) adopts a True Single Phase Clock (TSPC) dynamic D flip-flop type PFD to compare the jumping edges of two input signals, and then controls a current source to charge and discharge a capacitor by using the generated frequency difference and Phase difference, and if the two input signals have equal frequency and same Phase, the charging and discharging are stopped, and a lock indication signal is generated.

In the prior art, a reference clock and a feedback clock are compared in phase, a circuit is complex, the influence of a process, voltage and temperature (PVT for short) is great, and a frequency discrimination result is unstable; the reason why the above disadvantage is caused is that the phase difference between the reference clock and the feedback clock is adopted to charge and discharge the capacitor in the form of current, so that the adopted current value and the adopted capacitance value have large changes with PVT, sometimes the frequency identification function is disabled due to PVT deviation, even the current is as small as zero, and the locking indication signal cannot be generated.

Disclosure of Invention

The application provides a frequency identifier of a phase-locked loop and the phase-locked loop, which aim to solve the problem of inaccurate frequency identification result in the prior art.

In order to solve the above technical problem, the present application provides a frequency discriminator for a phase-locked loop, including: the capture signal circuit is used for capturing the signal edge of the standard clock signal and generating a capture signal; the standard clock signal has a standard number of cycles; the signal counting circuit is used for counting the oscillation clock signals under the triggering of the capture signals to obtain the oscillation period number; a number comparison circuit for comparing the number of oscillation cycles with a standard cycle range, the standard cycle range being dependent on the product of the phase-locked loop frequency multiplication and the standard cycle number; wherein the number of oscillation cycles is within the standard cycle range indicating authentication pass.

In one embodiment, the capture signal circuit comprises at least one capture flip-flop.

In one embodiment, the trap signal circuit includes three trap flip-flops connected in series.

In one embodiment, the signal counting circuit includes: the input end of the counting trigger is used for inputting the oscillation clock signal, and the output end of the counting trigger is used for outputting a counting signal; and the counting latch is connected with the counting trigger, the input end of the counting latch is used for inputting the capture signal and the counting signal at the capture moment, and the output end of the counting latch is used for outputting the oscillation period number.

In one embodiment, the number of count flip-flops is dependent on a product of the phase locked loop frequency multiplication and the standard number of cycles.

In one embodiment, the standard period range is the product of the phase-locked loop frequency multiplication and the standard period number plus or minus tolerance value.

In one embodiment, the tolerance value is 1/2^ n, n being an integer greater than or equal to 1, of the product.

To solve the above technical problem, the present application provides a phase-locked loop including the above frequency discriminator.

In one embodiment, the phase locked loop circuit further comprises an oscillator connected to the frequency discriminator.

Different from the prior art, the frequency identifier of the phase-locked loop comprises a capture signal circuit, a signal counting circuit and a number comparison circuit, wherein the capture signal circuit is used for capturing the signal edge of a standard clock signal and generating a capture signal; the standard clock signal has a standard number of cycles; the signal counting circuit is used for counting the oscillation clock signals under the triggering of the capture signals to obtain the number of oscillation cycles; the quantity comparison circuit is used for comparing the oscillation period number with a standard period range, and the standard period range depends on the product of the frequency multiplication of the phase-locked loop and the standard period number; wherein the number of oscillation cycles is within the standard cycle range indicating authentication pass.

The capture signal is generated by the capture signal circuit based on a standard clock signal, the oscillation clock signal is counted by the signal counting circuit to obtain the number of oscillation cycles, and then whether the identification is passed or not is determined by comparing the number. The above process adopts digital logic circuit to perform frequency identification, so as to get rid of the influence of the above process, voltage and temperature, and the frequency identification function is robust and stable, and the identification precision is reliable and adjustable.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 is a circuit configuration diagram of a frequency discriminator according to an embodiment of the present application;

fig. 2 is a circuit diagram of a phase-locked loop according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The invention idea of the application is that in a standard clock period (the standard clock period is an accurate frequency clock from the outside, the period of the standard clock period is an accurate fixed value), a locked target clock of a phase-locked loop is counted, and a counting result is compared with a standard value to obtain a difference value. Specifically, whether the counting result is within a frequency doubling target range (the range is adjustable, the range is narrower, and the precision is higher) is judged to obtain a frequency identification result, and whether the phase-locked loop is locked is judged.

Based on the above inventive concept, specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a circuit structure diagram of a frequency discriminator according to an embodiment of the present application, and fig. 2 is a circuit structure diagram of a phase-locked loop according to an embodiment of the present application.

The frequency discriminator 100 of the present embodiment includes a captured signal circuit 11, a signal counting circuit 12, and a number comparison circuit 13.

The capture signal circuit 11 is configured to capture a signal edge of a standard clock signal, thereby generating a capture signal. The signal counting circuit 12 is configured to count the oscillation clock signal under the trigger of the capture signal to obtain the number of oscillation cycles. The quantity comparison circuit 13 is used for comparing the oscillation period number with the standard period range, and the judgment of passing is indicated when the oscillation period number is determined to be in the standard period range.

The capture signal generated by the capture signal circuit 11 is used to trigger the signal counting circuit 12 to count the oscillation clock signal, which is the clock signal that the phase-locked loop needs to lock, i.e. the oscillation clock signal needs to be locked with the standard time signal. After the signal counting circuit 12 generates the oscillation period number, the oscillation period number is input to the number comparison circuit 13, the number comparison circuit 13 compares the oscillation period number with a standard period range, the standard period range depends on the product of the frequency multiplication of the phase-locked loop and the standard period number, the product is also the target clock period number of the phase-locked loop, therefore, whether the locking target is achieved or not can be obtained by comparing the oscillation period number with the product.

Specifically, assuming that the frequency multiplication coefficient of the phase-locked loop is F, within N cycles of the reference clock (CLK _ REF), the standard value of the cycle number of the target clock is F × N for the phase-locked loop that has been accurately locked; if the count monitoring is continuously performed on the controlled clock (CLK _ VCO) of the pll, if the count result is count _ p, then the count _ p should gradually approach the accurate value F × N during the locking process of the pll (the controlled clock gradually approaches the target frequency). In the frequency discrimination process, F × N-count _ p (which may be positive or negative) is the frequency discrimination result; if the count _ p falls within a certain deviation range, namely a standard period range, the phase-locked loop can be considered to be successfully locked, the frequency identification result is passed, and a locking indication signal can be given.

Further, the capture signal circuit 11 includes at least one capture flip-flop, and specifically includes three capture flip-flops DFF _ r1, DFF _ r2, and DFF _ r3 connected in series in this embodiment. The reset and capture signals rst _ range are generated continuously by DFF _ r1, DFF _ r2 and DFF _ r3 at the rising edge (or at the falling edge) of the reference clock, i.e., the standard clock signal (CLK _ REF).

The signal counting circuit 12 includes a counting flip-flop counter _ M and a counting latch _ M, wherein an input terminal of the counting flip-flop is used for inputting an oscillation clock signal, and an output terminal of the counting flip-flop is used for outputting a counting signal; the counting latch is connected with the counting trigger, the input end of the counting latch is used for inputting a capture signal (trigger clock port) and a counting signal (data port) of capture time, and the output end of the counting latch is used for outputting the oscillation period number.

Specifically, in the present embodiment, the count flip-flop is composed of M flip-flops (D _ cnt0, D _ cnt1, D _ cnt2, …, and D _ cnt), and the count latch is also composed of M flip-flops (D _ cp0, D _ cp1, D _ cp2, …, and D _ cpM).

When the rst _ range signal rises, the counting latch _ M captures the counting result of the counting flip-flop counter _ M, and then resets the counting flip-flop counter _ M to restart counting. The value obtained by the count latch M is compared with the lower limit value lower _ limit [ M:0] and the upper limit value upper _ limit [ M:0], and if the value is larger than the lower limit value lower _ limit [ M:0] and smaller than the upper limit value upper _ limit [ M:0], it is concluded that the PLL _ LOCK _ DETECT is high.

Wherein, the standard period range is the product F N plus-minus tolerance value. The particular count is quantized using particular logic, for example using binary. For the tolerance value, it can be obtained by shifting, i.e. shifting by 1 bit, and the tolerance value is 1/2 of the product. In this embodiment, the right shift is set to 3 bits to obtain the tolerance value 1/8, and when the count _ p is within the range of F × N (1-1/8) -F × N (1+1/8), the phase-locked loop is deemed to pass the frequency identification result, and the lock indication signal is positive.

The number of flip-flops M is determined by the product F × N of the pll frequency multiplication F and the standard number of cycles N, and it is necessary to ensure that the counting capability exceeds F × N. Because the embodied process may cause the frequency of the oscillator in the phase-locked loop to overshoot (i.e., overshoot beyond the target frequency), the number M of the flip-flops in the counting flip-flops may be considered to be more than enough to prevent overflow, for example, the number of cycles of the target clock is normalized to F × N, and then 2, 4, or even 8 times the number of flip-flops may be serially connected to form a counter, so that even if the target clock frequency is too high and the counting result count _ p exceeds the target of F × N, the designed circuit may be sufficient to identify the counting result without overflow (causing an error in the counting result).

Specific examples are given below for convenience of understanding, for example, the standard clock period is 1MHz, the pll frequency multiplication factor is 480(F ═ 480), and during the locking process, the oscillating clock is monitored and counted by using the present application in one standard clock period (N ═ 1), and then the difference between the standard value F ═ N ═ 480 and the count value count _ p is the frequency discrimination result.

The criterion F × N is represented by a 10-bit circuit limit [9:0] ═ 10 ' b01_1110_0000 ═ 10'd 480, and the division by 2 is implemented by shifting one bit to the right according to the logic circuit principle, then if the tolerance value is 1/8, i.e., limit [9:3] ═ 011_1100 ═ 7'd 60;

when the count value count _ p falls within the range of (limit [9:0] -limit [9:3]) - (limit [9:0] + limit [9:3]) (the specific value in this case is 480-60 to 480+60), that is, it indicates that the frequency identification is passed, a lock indication signal is given.

In summary, the frequency setter of the present application uses a logic circuit to determine the frequency difference between the standard clock and the oscillation clock, and uses the standard clock as a reference to determine the oscillation clock, so that the frequency setter has high determination accuracy, high stability, and is not affected by the process. In the prior art, the analog circuit is adopted to realize the function, the charging and discharging current and the capacitor for storing the charge are influenced by various environmental factors such as process, voltage, temperature and the like, and the stability is poor, so that the output deviation of the locking indication signal in the phase-locked loop is poor, sometimes even under the condition that the phase-locked loop is locked, the charging failure is caused by the excessively small charging current and the large leakage of the charge storage capacitor, and the locking indication cannot be output.

In addition, the present application further provides a phase-locked loop, and specifically please refer to fig. 2, where fig. 2 is a circuit structure diagram of the phase-locked loop according to an embodiment of the present application. The phase-locked loop 300 of the present embodiment includes the frequency discriminator 100 and the other phase-locked loop portion 200, and the other phase-locked loop portion 200 includes other circuits inside the phase-locked loop, such as a low-pass filter and an oscillator. In addition to outputting the signal to the "other parts of the phase locked loop", the frequency identifier 100 also outputs a lock indication signal to the outside of the phase locked loop for use by higher level systems.

In the above description of the present specification, the terms "fixed," "mounted," "connected," or "connected," and the like, are to be construed broadly unless otherwise expressly specified or limited. For example, with the term "coupled", it can be fixedly coupled, detachably coupled, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship. Therefore, unless the specification explicitly defines otherwise, those skilled in the art can understand the specific meaning of the above terms in the present application according to specific circumstances.

In addition, the terms "first" or "second", etc. used in this specification are used to refer to numbers or ordinal terms for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present specification, "a plurality" means at least two, for example, two, three or more, and the like, unless specifically defined otherwise.

While various embodiments of the present application have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present application. It should be understood that various alternatives to the embodiments of the application described herein may be employed in practicing the application. The following claims are intended to define the scope of the application and, accordingly, to cover module compositions, equivalents, or alternatives falling within the scope of these claims.

Claims

1. A frequency evaluator for a phase locked loop, the frequency evaluator comprising:

the capture signal circuit is used for capturing the signal edge of the standard clock signal and generating a capture signal; the standard clock signal has a standard number of cycles;

the signal counting circuit is used for counting the oscillation clock signals under the triggering of the capture signals to obtain the oscillation period number;

a number comparison circuit for comparing the number of oscillation cycles with a standard cycle range, the standard cycle range being dependent on the product of the phase-locked loop frequency multiplication and the standard cycle number;

wherein the number of oscillation cycles is within the standard cycle range indicating authentication pass.

2. The frequency evaluator of claim 1 wherein said capture signal circuit comprises at least one capture trigger.

3. The circuit of claim 2, wherein the trap signal circuit comprises three trap flip-flops in series.

4. The circuit of claim 1, wherein the signal counting circuit comprises:

the input end of the counting trigger is used for inputting the oscillation clock signal, and the output end of the counting trigger is used for outputting a counting signal;

and the counting latch is connected with the counting trigger, the input end of the counting latch is used for inputting the capture signal and the counting signal at the capture moment, and the output end of the counting latch is used for outputting the oscillation period number.

5. The circuit of claim 4, wherein the number of count flip-flops is dependent on a product of the phase-locked loop frequency multiplication and the number of standard cycles.

6. The circuit of claim 1, wherein the standard period range is a product of the phase-locked loop frequency multiplication and the standard period number plus or minus a tolerance value.

7. The circuit of claim 6, wherein the tolerance value is of the product

n is an integer of 1 or more.

8. A phase locked loop comprising a frequency evaluator as claimed in any one of claims 1 to 7.

9. The phase locked loop of claim 8 wherein the phase locked loop circuit further comprises an oscillator coupled to the frequency discriminator.