CN101557228A - Phase-lock loop system and phase-lock method of phase-lock loop - Google Patents
Phase-lock loop system and phase-lock method of phase-lock loop Download PDFInfo
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- CN101557228A CN101557228A CNA2008100886479A CN200810088647A CN101557228A CN 101557228 A CN101557228 A CN 101557228A CN A2008100886479 A CNA2008100886479 A CN A2008100886479A CN 200810088647 A CN200810088647 A CN 200810088647A CN 101557228 A CN101557228 A CN 101557228A
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Abstract
The invention relates to a phase-lock loop system comprises a phase-lock loop and a locking detector, wherein the phase-lock loop is used for outputting a phase-lock clock, the locking detector is coupled with the phase-lock loop and used for detecting if the frequency of the phase-lock clock is in a predetermined frequency range and if the phase-lock clock is stable, and if the frequency of the phase-lock clock is detected to be already in the predetermined frequency range and the predetermined frequency range is stable, the locking detector outputs a locking signal.
Description
Technical field
The present invention relates to a kind of PHASE-LOCKED LOOP PLL TECHNIQUE, and particularly relate to a kind of phase-locked loop systems with accurate frequency lock function.
Background technology
(phase-lock loop, basic circuit PLL) please refer to the loop feature of Fig. 1 to phase-locked loop.Phase-locked loop mainly contains two inputs, is respectively to receive reference frequency as reference clock Ref_CLK, and receives a feedback frequency.Feedback frequency is a feedback signal of phase-locked loop, just feeds back after the general frequency reducing that for example can be suitable.Phase-locked loop comprises that (Phase/FrequencyDetector PFD) receives aforesaid two input signals to a phase/frequency detector 100.Phase/frequency detector 100 is reference frequency and feedback frequency difference between the two relatively, detects between the two the phase place and the measures of dispersion of frequency, and when reference frequency was higher than feedback frequency, a pulse signal was exported in the meeting of the output (up) of PFD 100; Otherwise when if reference frequency is lower than feedback frequency, the output (DN) of PFD 100 end can another pulse signal of output.The pulse signal that PFD 100 produces is subsequently via charge pump circuit (Charge Pump) 102 and loop filter (Loop Filter) 104, convert a voltage control signal to, voltage-controlled oscillator (Voltage Controlled Oscillator, VCO) 106 with the control next stage.VCO 106 produces a clock signal VCO_CLK according to voltage control signal, and it will feed back to PFD 100, carries out phase-locked loop action.Yet according to the frequency of operation of PFD 100, clock signal VCO_CLK may need a frequency divider (Divider) 108, suitably just feeds back to phase/frequency detector 100 after the frequency reducing.The mechanism of locking for example is the clock signal VCO_CLK that makes output, by feeding back to PFD 100, to reach phase place and the frequency state that is consistent synchronously with reference frequency.When the feedback incoming frequency with reference to the frequency of incoming frequency and phase place when consistent just whole phase loop locked.
Whether in order to detect pll system locking correctly, traditional pll system can be built and put lock detecting circuit, judges with two output signals that detect PFD 100 whether the output frequency of reference frequency and PLL has been in the state of locking.But, in practical operation, may disappear, yet when input signal disappeared, the UP of PFD 100 and the output signal of DN just can forbidden energy (disable), and then cause the erroneous judgement of lock detecting circuit by the reference frequency of outside input.
Therefore, the dealer needs better mechanism, judges the locked condition of pll system.
Summary of the invention
The invention provides the phase-lock technique of a kind of phase-locked loop systems, frequency lock detector and phase-locked loop, cooperate the lock detecting circuit and the method for new mechanism, can promote the accuracy of locking at least.
The present invention proposes a kind of phase-locked loop systems, comprises a phase-locked loop and a lock detector.Phase-locked loop is used for exporting a phase-locked clock.Lock detector is coupled to this phase-locked loop, and whether whether the frequency that is used for detecting this phase-locked clock fall into a scheduled frequency range and detect this phase-locked clock stable.The frequency of this phase-locked clock has fallen into this scheduled frequency range and this phase-locked clock is stable if detect, and then lock detector is exported a locking signal.
According to one embodiment of the invention, in described phase-locked loop systems, for example lock detector comprises a frequency discriminator, is coupled to this phase-locked loop, and whether the frequency that is used for detecting this phase-locked clock falls into this scheduled frequency range, and exports one first testing result according to this.One comparing unit is used for judging whether this phase-locked clock is stable, to export one second testing result.One locking judging unit is coupled to this frequency discriminator and this comparing unit, is used for exporting a frequency lock status signal according to this first testing result and this second testing result.
According to one embodiment of the invention, in described phase-locked loop systems, for example frequency discriminator is coupled to this comparing unit.Frequency discriminator is converted to a frequency number character code signal with this phase-locked clock in addition, and exports this frequency number character code signal to this comparing unit.
Comparing unit for example comprises one first shift register, is used for receiving this frequency number character code signal.One digital comparator is coupled to first shift register, is used for receiving the output of this frequency number character code and this first shift register, so that relatively whether this frequency number character code is identical with the output of this first shift register, and exports one the 3rd testing result according to this.One judging unit is coupled to digital comparator, is used for receiving a plurality of the 3rd testing results continuously, whether judging this frequency number character code number of times identical with the output of this first shift register greater than a pre-determined number, and exports this second testing result according to this.
According to one embodiment of the invention, in described phase-locked loop systems, for example this judging unit is one second shift register, is used for shift LD the 3rd testing result.Again for example, if in these a plurality of the 3rd testing results, have any to represent this frequency number character code different with the output of this first shift register, then this second shift register is to be reset (reset).
According to one embodiment of the invention, in described phase-locked loop systems, for example frequency discriminator is to set this scheduled frequency range according to a frequency setting signal.
According to one embodiment of the invention, in described phase-locked loop systems, for example this phase-locked loop comprises a phase/frequency detector, is used for receiving a reference clock and a feedback signal, and produces an output according to this reference clock and this feedback signal.One charge pump circuit (charge pump) is coupled to this phase/frequency detector, is used for receiving this first level output end of this phase/frequency detector and the output of this second level output end.One loop filter is coupled to this charge pump circuit, is used for receiving the output of this charge pump circuit.One voltage-controlled oscillator is coupled to this loop filter, is used for receiving the output of this loop filter, produces this phase-locked clock.One frequency divider with this phase-locked clock frequency division after output this feed back signal to this phase/frequency detector.
The present invention provides a kind of frequency lock detector again, comprises a frequency discriminator, a comparing unit, and a locking judging unit.Whether the frequency that frequency discriminator is used for detecting a phase-locked clock falls into a scheduled frequency range, and exports one first testing result according to this.Comparing unit is used for judging whether this phase-locked clock is stable, to export one second testing result.The locking judging unit is coupled to this frequency discriminator and this comparing unit, is used for exporting a frequency lock status signal according to this first testing result and this second testing result.
According to one embodiment of the invention, at described frequency lock detector, for example frequency discriminator is coupled to this comparing unit.Frequency discriminator is converted to a frequency number character code signal with this phase-locked clock in addition, and exports this frequency number character code signal to this comparing unit.
Comparing unit for example comprises one first shift register, a digital comparator and a judging unit.First shift register is used for receiving this frequency number character code signal.Digital comparator is coupled to this first shift register, is used for receiving the output of this frequency number character code and this first shift register, so that relatively whether this frequency number character code is identical with the output of this first shift register, and exports one the 3rd testing result according to this.Judging unit is coupled to this digital comparator, is used for receiving a plurality of the 3rd testing results continuously, whether judging this frequency number character code number of times identical with the output of this first shift register greater than a pre-determined number, and exports this second testing result according to this.
According to one embodiment of the invention, in described frequency lock detector, for example this judging unit is to be one second shift register, is used for shift LD the 3rd testing result.For example in described a plurality of the 3rd testing results, if there is any to represent the output of this frequency number character code and this first shift register differing from each other, then this second shift register is to be reset (reset) again.
According to one embodiment of the invention, in described frequency lock detector, for example frequency discriminator is to set this scheduled frequency range according to a frequency setting signal.
The present invention provides a kind of phase-lock technique of phase-locked loop again, comprises obtaining the phase-locked clock that a phase-locked loop will be exported.Detect this phase-locked clock and whether fall into a scheduled frequency range.Whether detect this phase-locked clock stable.The frequency of this phase-locked clock has fallen into this scheduled frequency range and this phase-locked clock is stable if detect, and then exports a locking signal.
According to one embodiment of the invention, in the phase-lock technique of described phase-locked loop, whether this stable step comprises generation one frequency number character code signal for example to detect this phase-locked clock, corresponding this phase-locked clock of representing.Again, utilize one first shift register, receive a frequency number character code signal and an operation clock signal.Utilize a digital comparator, receive the output of this operation clock signal and this first shift register, relatively whether this frequency number character code signal of previous moment is identical with this frequency number character code signal in one moment of back, if identical then export a signal.Utilize one second shift register, receive this signal of this operation clock signal and this digital comparator output, a logic state signal of output decision.
According to one embodiment of the invention, in the phase-lock technique of described phase-locked loop, for example produce this frequency number character code signal by a frequency discriminator.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 shows according to the embodiment of the invention, the circuit diagram of phase-locked loop systems.
The correct frequency signal schematic diagram that Fig. 2 A exports when showing phase-locked loop operation.
Fig. 2 B shows phase-locked loop when operation, the incorrect frequency signal schematic diagram of output.
Fig. 3 shows according to the embodiment of the invention, the circuit diagram of phase-locked loop systems.
The reference numeral explanation
100: phase/frequency detector
102: current controller
104: loop filter
106：VCO
108: frequency divider
110: lock detector
112-128: signal
200: lock detector
202: frequency discriminator
204: shift register
206: shift register
208: digital comparator
210: logical block.
Embodiment
The present invention adds the frequency of frequency discriminator with phase-locked loop output in phase-locked loop systems, be input in the frequency discriminator.Frequency discriminator can be converted to digital code with received phase-locked clock, and it is deposited, enter within the frequency window (window) of desiring locking frequency when frequency, just can utilize the digital code of depositing to compare with the digital code of conversion just, like this just being equivalent to compares last phase-locked clock and the phase-locked clock that newly receives.As both continue to keep, just can accurately be judged to be the frequency lock state.
Fig. 1 shows according to the embodiment of the invention, the circuit diagram of phase-locked loop systems.Referring to Fig. 1, the phase-locked loop in the phase-locked loop systems can be the phase-locked loop of general design, need not special qualification.As previously mentioned, basic phase-locked loop for example comprises PFD 100, one current controllers, 102, one filters 104 and a voltage-controlled oscillator (VCO) 106.In addition if necessary, on the path of feedback, can increase by a frequency divider 108.
Note that the phase-locked function of phase-locked loop at this, except the phase locking of the phase-locked clock exported being aimed at, also must be in desired frequency range with the frequency lock of phase-locked clock.The correct frequency signal schematic diagram that Fig. 2 A exports when showing phase-locked loop operation.Consult Fig. 2 A, the frequency of output is in phase-locked loop, because degenerative function is arranged, so output frequency is after variation after a while, and can tend towards stability reaches the frequency of phase alignment.On behalf of the frequency of this output, this frequency if in the scope (and aforesaid frequency range) of frequency window, then correctly be locked in the required phase place and frequency separation.
Fig. 2 B shows phase-locked loop when operation, the incorrect frequency signal schematic diagram of output.Consult Fig. 2 B, when the existing practice only detects according to PFD high/low (UP/DN) output whether positive frequency is correctly locked, therefore, have under the situation of interrupting or changing at reference clock Ref_CLK, phase-locked loop still can obtain the frequency of phase alignment, but its frequency is not the frequency that will lock.Another reason, traditional lock-in detection that is adopted are to detect the high/low signal of PFD output again.This mode is judged the PLL state, needs an extra electric capacity usually, by the phase error that UP/DN produced, with a fixed current source to this capacitor discharge.Other has a fixed path to making a decision with a comparator after the electric capacity charging.When electric capacity is charged to a fixed level, judge that with the output of comparator PLL is in locking or non-locking.This traditional approach can't accurately be judged the position of actual lock.
The present invention has considered above-mentioned problem at least, proposes the design of another kind of pll system.The present invention directly judges the phase-locked clock of being exported of PLL by a lock detecting circuit.In the circuit box of Fig. 1, lock detector 110 is accepted the phase-locked clock (VCO_CLK) that the VCO 106 of phase-locked loop is exported.Lock detector 110 detects this phase-locked clock and whether falls into the frequency range of desiring to reach, whether and it is stable to detect this phase-locked clock, when these two kinds of detections are all set up, can determine that just PLL has correctly reached semaphore lock, and the phase-locked clock of being exported meet must frequency range.
With regard to function, the circuit that design lock detector 110 can have multiple variation.Fig. 3 shows according to the embodiment of the invention, the circuit diagram of phase-locked loop systems.Consult Fig. 3, phase-locked loop systems comprises a phase-locked loop, and a lock detector 200.A phase-locked clock is exported in phase-locked loop such as previous description, and it for example is the clock VCO_CLK by VCO 106 outputs.When clock VCO_CLK reaches phase alignment, for PLL, be lock-out state, yet, please note at this, such lock-out state does not guarantee that the phase-locked clock of being exported must correctly (may have wrong frequency), that is PLL may be in wrong lock-out state.
And lock detector 200 is to be used for detecting PLL whether to be in phase locked state correctly.In the present embodiment, lock detector 200 receives the phase-locked clock 112 of VCO 106 outputs, and a frequency setting signal 114.Wherein, frequency setting signal 114 be used for setting must frequency range, it can utilize the mode of depositing (register) to set, with the decision frequency that will lock.This note that lock detector 200 except detect this phase-locked clock whether met must frequency needs, whether stable, and export a locking signal 128 when these two kinds of detections are all set up if also detecting this phase-locked clock.
With regard to thinner portion circuit, lock detector 200 for example comprises a frequency discriminator 202, its according to received frequency setting signal 114 set must frequency range (for example aforesaid frequency window), and detect phase-locked clock 112 and whether fall into this frequency range, to produce a detection signal 116.Wherein, this judges on behalf of phase-locked clock 112, signal whether fallen into this frequency range, in the present embodiment, represents phase-locked clock 112 to fall into this frequency range if judge signal, detection signal 116 counterlogic values 1 then, on the contrary then the counterlogic value 0.Note that embodiment among Fig. 3 at this, its frequency discriminator 202 is to represent with the function that will reach, and its circuit that really is used for reaching testing mechanism can be incorporated into the inside or the outside of frequency discriminator 202.Therefore, the present invention does not carry out any restriction to the framework of frequency discriminator, as long as frequency discriminator 202 can be reached aforesaid testing mechanism, and its circuit design can have different variations.
The data of detection signal 116 only represent that the signal of PPL output meets the frequency that will lock, yet phase-locked clock 112 might not restrained (locking) as yet, that is may not reach the state of phase alignment as yet.Therefore, whether lock detector 200 still also need only detect phase-locked clock 112 stable, and in the present embodiment, whether stable the present invention build in addition and put a comparing unit 212 and carry out phase-locked clock 112 the mechanism that detects.In addition, frequency discriminator 202 constantly all can be done detection to phase-locked clock 112 in predetermined each, for example converts phase-locked clock 112 to corresponding digital code 118 by counter (counter), so each all has 118 outputs of corresponding digital code constantly.
With regard to mechanism, because phase-locked clock 112 can be converged on the stabilized frequency in theory, so its corresponding digital code 118 can become a fixed value, that is to say, if the phase-locked clock that PLL exported is stable, the different digital codes 118 constantly in front and back just can be identical so.Therefore, the present invention detects by aforesaid principle; In the present embodiment, the circuit design of comparing unit 212 for example can be reached by two shift registers 204 and 206 and one digital comparator 208.
The effect of shift register 206 is as follows.If the output of digital comparator 208 all continues to maintain high level at several clocks, just export a for example high level detection signal 126 (counterlogic value 1).Quantity at these several clocks is to set according to actual the requirement, and for example two or more, its more a plurality of clocks are represented more stable.In addition, in these several clocks, if a plurality of status signals 126 that received wherein, any detection signal 126 counterlogic value 0 (digital code of its representative digital code and previous moment this moment is also inequality) are arranged, shift register 206 just can be reset (reset) so, whether has entered lock-out state to detect phase-locked clock 112 again.
That is shift register 206 can comprise a spurious lock testing circuit (false lock detectorcircuit).After digital comparator 208 outputs were continuously low level several clock, just representative entered the state of spurious lock.Therefore, after restarting another time phase alignment after the replacement, just can change.
At last, if detection signal 116 and 126 counterlogic value 1 (true (true) state of logic) all, just definite phase-locked clock not only is in correct frequency range, and has entered lock-out state.This judgement can be judged by logical block 210, for example reaches it with one with door (AND gate), therefore only can just can export the signal of a true state when two signals 116 and 126 all are the true state of logic, with this state as expression output locking.
Embodiment provided by the present invention can promote the accuracy of lock-out state really at least.Yet the present invention is not limited only to illustrated embodiment.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (15)
1. phase-locked loop systems comprises:
One phase-locked loop is used for exporting a phase-locked clock; And
One lock detector, be coupled to this phase-locked loop, the frequency that is used for detecting this phase-locked clock whether fall into a scheduled frequency range and detect this phase-locked clock whether stable and if detect the frequency of this phase-locked clock has fallen into this scheduled frequency range and this phase-locked clock is stable, then export a locking signal.
2. phase-locked loop systems as claimed in claim 1, wherein, this lock detector comprises:
One frequency discriminator is coupled to this phase-locked loop, and whether the frequency that is used for detecting this phase-locked clock falls into this scheduled frequency range, and exports one first testing result according to this;
One comparing unit is used for judging whether this phase-locked clock is stable, to export one second testing result; And
One locking judging unit is coupled to this frequency discriminator and this comparing unit, is used for exporting a frequency lock status signal according to this first testing result and this second testing result.
3. phase-locked loop systems as claimed in claim 2, wherein, this frequency discriminator is coupled to this comparing unit, and this frequency discriminator is converted to a frequency number character code signal with this phase-locked clock in addition, and export this frequency number character code signal to this comparing unit, and this comparing unit comprises:
One first shift register is used for receiving this frequency number character code signal;
One digital comparator is coupled to this first shift register, is used for receiving the output of this frequency number character code and this first shift register, so that relatively whether this frequency number character code is identical with the output of this first shift register, and exports one the 3rd testing result according to this; And
One judging unit is coupled to this digital comparator, is used for receiving a plurality of the 3rd testing results continuously, whether judging this frequency number character code number of times identical with the output of this first shift register greater than a pre-determined number, and exports this second testing result according to this.
4. phase-locked loop systems as claimed in claim 3, wherein, this judging unit is one second shift register, is used for shift LD the 3rd testing result.
5. phase-locked loop systems as claimed in claim 4, wherein, if in these a plurality of the 3rd testing results, have any to represent this frequency number character code different with the output of this first shift register, then this second shift register is to be reset.
6. phase-locked loop systems as claimed in claim 1, wherein, this frequency discriminator is to set this scheduled frequency range according to a frequency setting signal.
7. phase-locked loop systems as claimed in claim 1, wherein, this phase-locked loop comprises:
One phase/frequency detector is used for receiving a reference clock and a feedback signal, and produces an output according to this reference clock and this feedback signal;
One charge pump circuit is coupled to this phase/frequency detector, is used for receiving this first level output end of this phase/frequency detector and the output of this second level output end;
One loop filter is coupled to this charge pump circuit, is used for receiving the output of this charge pump circuit;
One voltage-controlled oscillator is coupled to this loop filter, is used for receiving the output of this loop filter, produces this phase-locked clock; And
One frequency divider, this feeds back signal to this phase/frequency detector with output behind this phase-locked clock frequency division.
8. a frequency lock detector comprises
One frequency discriminator, whether the frequency that is used for detecting a phase-locked clock falls into a scheduled frequency range, and exports one first testing result according to this;
One comparing unit is used for judging whether this phase-locked clock is stable, to export one second testing result; And
One locking judging unit is coupled to this frequency discriminator and this comparing unit, is used for exporting a frequency lock status signal according to this first testing result and this second testing result.
9. frequency lock detector as claimed in claim 8, wherein, this frequency discriminator is coupled to this comparing unit, and this frequency discriminator is converted to a frequency number character code signal with this phase-locked clock in addition, and export this frequency number character code signal to this comparing unit, and this comparing unit comprises:
One first shift register is used for receiving this frequency number character code signal;
One digital comparator is coupled to this first shift register, is used for receiving the output of this frequency number character code and this first shift register, so that relatively whether this frequency number character code is identical with the output of this first shift register, and exports one the 3rd testing result according to this; And
One judging unit is coupled to this digital comparator, is used for receiving a plurality of the 3rd testing results continuously, whether judging this frequency number character code number of times identical with the output of this first shift register greater than a pre-determined number, and exports this second testing result according to this.
10. frequency lock detector as claimed in claim 9, wherein, this judging unit is one second shift register, is used for shift LD the 3rd testing result.
11. frequency lock detector as claimed in claim 10, wherein, in these a plurality of the 3rd testing results, if there is any to represent the output of this frequency number character code and this first shift register differing from each other, then this second shift register is to be reset.
12. frequency lock detector as claimed in claim 8, wherein, this frequency discriminator is set this scheduled frequency range according to a frequency setting signal.
13. the phase-lock technique of a phase-locked loop comprises:
Obtain the phase-locked clock that a phase-locked loop will be exported;
Detect this phase-locked clock and whether fall into a scheduled frequency range;
Whether detect this phase-locked clock stable; And
The frequency of this phase-locked clock has fallen into this scheduled frequency range and this phase-locked clock is stable if detect, and then exports a locking signal.
14. the phase-lock technique of phase-locked loop as claimed in claim 13, wherein, whether this stable step comprises to detect this phase-locked clock:
Generation is to a frequency number character code signal that should phase-locked clock;
Utilize one first shift register, receive this a frequency number character code signal and an operation clock signal;
Utilize a digital comparator, whether this frequency number character code signal that comes the comparison previous moment is identical with back one this frequency number character code signal constantly, if identical then export a signal; And
Utilize one second shift register, receive this signal of this operation clock signal and this digital comparator output, and export a logic state signal according to this signal of this operation clock signal and the output of this digital comparator.
15. the phase-lock technique of phase-locked loop as claimed in claim 14, other includes:
Utilize a frequency discriminator to produce this frequency number character code signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008100886479A CN101557228A (en) | 2008-04-10 | 2008-04-10 | Phase-lock loop system and phase-lock method of phase-lock loop |
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| CNA2008100886479A CN101557228A (en) | 2008-04-10 | 2008-04-10 | Phase-lock loop system and phase-lock method of phase-lock loop |
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| CN102291130A (en) * | 2011-04-02 | 2011-12-21 | 长沙景嘉微电子有限公司 | Locking detection circuit with programmable locking accuracy and locking frequency |
| CN102868398A (en) * | 2011-07-05 | 2013-01-09 | 联发科技（新加坡）私人有限公司 | Clock signal generating device and method using same |
| CN103873049A (en) * | 2012-12-10 | 2014-06-18 | 北京普源精电科技有限公司 | Radio-frequency-signal measurement device and use method thereof |
| CN105162457A (en) * | 2010-08-09 | 2015-12-16 | 德州仪器公司 | High-speed frequency divider and phase locked loop using same |
| CN106169932A (en) * | 2015-05-20 | 2016-11-30 | 恩智浦有限公司 | There is the phase-locked loop of lock detector |
| CN112838861A (en) * | 2020-12-31 | 2021-05-25 | 广东大普通信技术有限公司 | Clock locking method, device, equipment and storage medium |
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2008
- 2008-04-10 CN CNA2008100886479A patent/CN101557228A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105162457A (en) * | 2010-08-09 | 2015-12-16 | 德州仪器公司 | High-speed frequency divider and phase locked loop using same |
| CN105162457B (en) * | 2010-08-09 | 2018-07-27 | 德州仪器公司 | High-speed frequency divider and the phase-locked loop for using high-speed frequency divider |
| CN102291130A (en) * | 2011-04-02 | 2011-12-21 | 长沙景嘉微电子有限公司 | Locking detection circuit with programmable locking accuracy and locking frequency |
| CN102291130B (en) * | 2011-04-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | Locking detection circuit with programmable locking accuracy and locking frequency |
| CN102868398A (en) * | 2011-07-05 | 2013-01-09 | 联发科技（新加坡）私人有限公司 | Clock signal generating device and method using same |
| CN102868398B (en) * | 2011-07-05 | 2014-12-17 | 联发科技（新加坡）私人有限公司 | Clock signal generating device and method using same |
| CN103873049A (en) * | 2012-12-10 | 2014-06-18 | 北京普源精电科技有限公司 | Radio-frequency-signal measurement device and use method thereof |
| CN103873049B (en) * | 2012-12-10 | 2019-01-29 | 北京普源精电科技有限公司 | Radiofrequency signal measuring device and its application method |
| CN106169932A (en) * | 2015-05-20 | 2016-11-30 | 恩智浦有限公司 | There is the phase-locked loop of lock detector |
| CN112838861A (en) * | 2020-12-31 | 2021-05-25 | 广东大普通信技术有限公司 | Clock locking method, device, equipment and storage medium |
| CN112838861B (en) * | 2020-12-31 | 2022-08-26 | 广东大普通信技术股份有限公司 | Clock locking method, device, equipment and storage medium |
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