CN112838861B - Clock locking method, device, equipment and storage medium - Google Patents

Clock locking method, device, equipment and storage medium Download PDF

Info

Publication number
CN112838861B
CN112838861B CN202011630437.5A CN202011630437A CN112838861B CN 112838861 B CN112838861 B CN 112838861B CN 202011630437 A CN202011630437 A CN 202011630437A CN 112838861 B CN112838861 B CN 112838861B
Authority
CN
China
Prior art keywords
frequency
clock
preset
determining
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011630437.5A
Other languages
Chinese (zh)
Other versions
CN112838861A (en
Inventor
吴继华
滕成旺
陈健
林潮兴
付珍峰
刘朝胜
张辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Daguangxin Technology Co ltd
Original Assignee
Guangdong Daguangxin Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Daguangxin Technology Co ltd filed Critical Guangdong Daguangxin Technology Co ltd
Priority to CN202011630437.5A priority Critical patent/CN112838861B/en
Publication of CN112838861A publication Critical patent/CN112838861A/en
Application granted granted Critical
Publication of CN112838861B publication Critical patent/CN112838861B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses a method, a device, equipment and a storage medium for locking a clock. The method comprises the following steps: determining a previous state of the local source clock when the local source clock enters a fast locking state; determining the clock frequency of the local source clock according to the last state; determining a preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency; adjusting the clock frequency according to the preset frequency adjustment range to obtain a center frequency and judging whether a first frequency offset change value of the center frequency in first preset time is smaller than a first preset value; and if the first frequency deviation change value is larger than or equal to the first preset value, updating the central frequency and judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining the adjustment range of the preset frequency according to the preset adjustment frequency and the clock frequency until the stable locking state is reached. This method allows the frequency of the local source clock to be changed slowly during the fast lock phase.

Description

Clock locking method, device, equipment and storage medium
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for clock locking.
Background
In the clock keeping time and time service process of communication equipment, a local source is often needed to track a time service source so as to achieve the clock frequency synchronization of the local source and the time service source. In the process of locking the local source, the frequency adjustment amplitude of the local source clock is large at the beginning stage of the tracking process, the frequency of the local source clock begins to tend to be stable after a period of time, and the frequency of the local source clock can be used as the clock reference of other systems when being stable in a reasonable range.
At the beginning of the tracking process, instability of the clock control system may be caused if the frequency of the local source clock changes too quickly.
Disclosure of Invention
Embodiments of the present invention provide a method, an apparatus, a device, and a storage medium for clock locking, which enable a frequency of a local source clock to change slowly in a fast locking stage.
In a first aspect, an embodiment of the present invention provides a method for locking a clock, including:
when a local source clock enters a fast locking state, determining a last state of the local source clock;
determining a clock frequency of the local source clock according to the last state;
determining a preset frequency adjusting range according to a preset adjusting frequency variation and the clock frequency;
adjusting the clock frequency according to the preset frequency adjustment range to obtain a central frequency, and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the preset frequency adjustment range;
and if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency change amount and the clock frequency until the stable locking state is reached.
In a second aspect, an embodiment of the present invention further provides a clock locking apparatus, including:
the device comprises a first determining module, a second determining module and a third determining module, wherein the first determining module is used for determining the last state of a local source clock when the local source clock enters a quick locking state;
a second determining module, configured to determine a clock frequency of the local source clock according to the previous state;
the third determining module is used for determining a preset frequency adjusting range according to a preset adjusting frequency variation and the clock frequency;
the adjusting module is used for adjusting the clock frequency according to the preset frequency adjusting range to obtain a central frequency and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the preset frequency adjustment range;
the updating module is used for updating the central frequency if the first frequency offset change value is greater than or equal to a first preset value; and judging whether the local source clock reaches a stable locking state, if not, returning to execute the operation of determining the preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency until reaching the stable locking state.
In a third aspect, an embodiment of the present invention further provides a communication device, including:
one or more processors;
storage means for storing one or more programs;
the one or more programs are executable by the one or more processors to cause the one or more processors to perform a method of clock locking as described in any embodiment of the invention.
In a fourth aspect, embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a clock locking method as provided in any of the embodiments of the present invention.
The embodiment of the invention provides a method, a device, equipment and a storage medium for locking a clock, which comprises the steps of firstly, determining the last state of a local source clock when the local source clock enters a quick locking state; secondly, determining the clock frequency of the local source clock according to the last state; then determining a preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency; then, adjusting the clock frequency according to the preset frequency adjustment range to obtain a central frequency, and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the set frequency adjustment range; and finally, if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency change and the clock frequency until the stable locking state is reached. By using the technical scheme, the frequency of the local source clock can be slowly changed in the quick locking stage.
Drawings
Fig. 1 is a schematic flowchart of a clock locking method according to an embodiment of the present invention;
fig. 2 is a block diagram of a clock control system according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a clock locking method according to a second embodiment of the present invention;
fig. 4 is a diagram illustrating an overall flow of a clock locking method according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a clock locking apparatus according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of a communication device according to a fourth embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and the embodiments of the present invention are illustrative only and are not intended to limit the scope of the present invention.
It should be understood that the various steps recited in the method embodiments of the present invention may be performed in a different order and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the invention is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the terms "first", "second", and the like in the present invention are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in the present invention are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present invention are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
Example one
Fig. 1 is a flowchart of a clock locking method according to an embodiment of the present invention, where the method is applicable to a situation where a local source clock tracks and locks a time service source clock, and the method may be performed by a clock locking apparatus, where the apparatus may be implemented by software and/or hardware and is generally integrated on a communication device.
As shown in fig. 1, a method for locking a clock according to a first embodiment of the present invention includes the following steps:
s110, when the local source clock enters the quick locking state, determining the last state of the local source clock.
In this embodiment, the local source clock may be a clock in a clock control system in the communication device, and the local source clock has a frequency source, and the frequency source of the local source clock may be a local crystal oscillator, for example.
Fig. 2 is a block diagram of a clock control system according to an embodiment of the present invention, as shown in fig. 2, a local source clock first goes through a preheating state and then goes through a locking state in a process of tracking a reference source, where the locking state may include a fast locking state and a stable locking state, and the local source clock needs to go through the fast locking state and enters the stable locking state after the state is stable. In the process, if the reference source is lost, the local source clock can enter a holding state, and when the reference source is found back again, the local source clock enters a locking state again.
The preheating state can be understood as a stable heating state of the local source clock; the locking state can be understood as the state that the frequency of a local source clock tracks and locks a reference source, and the reference source can be understood as the frequency of a clock acquired from a GPS system; holding state may be understood as the state in which after a reference source is lost, the local source clock continues to hold the frequency before the loss.
It should be noted that the reference source loss may be understood as a reference source loss caused by a broken reference source antenna or other situations during the process of tracking the reference source by the local source clock.
The last state of the local source clock may include a preheat state and a hold state, and it is understood that the local source clock may enter the fast lock state through the preheat state or the hold state.
And S120, determining the clock frequency of the local source clock according to the last state.
The clock frequency may be a frequency of a central point of the clock control system, and may also be understood as a frequency when the local source clock does not enter a steady state.
In this embodiment, the manner of determining the clock frequency according to the last state may include two ways: the method comprises the steps that firstly, if the last state of the system is a preheating state, the clock frequency can be determined according to the current time, the phase value of the local source clock and the first initial frequency of the local source clock; and secondly, if the last state of the system is a holding state, determining the clock frequency by judging whether a second frequency deviation change value of the clock frequency in the holding state is smaller than a second preset value.
Specifically, if the previous state is a preheating state, determining a first frequency offset according to a first time threshold and a phase value of a local source clock; and determining the clock frequency according to the first initial frequency of the local source clock and the first frequency offset.
The time threshold may be a current time range, and the time threshold may include an initial time and an end time. The first frequency offset may be understood as an absolute value of a variation of the phase difference per unit time.
In this embodiment, the first frequency offset may be calculated according to the phase change amounts of the reference source clock and the local source clock within the current first time threshold of the system. The method comprises the following specific steps:
calculating a first phase difference value of the phase of the local source clock and the phase of the reference source at the starting time, calculating a second phase difference value of the phase of the local source clock and the phase of the reference source at the ending time, calculating a phase difference value of the first phase difference value and the second phase difference value, calculating a time difference value of the ending time and the starting time, calculating a ratio of the phase difference value and the time difference value, and taking an absolute value to obtain a first frequency offset; calculating the sum of the first frequency offset and the first initial frequency of the local source clock may result in the clock frequency. The first initial frequency may be automatically obtained by the system, which is not described herein.
Specifically, if the previous state is the holding state, whether a second frequency offset change value of the clock frequency in the holding state relative to the reference source within a second preset time is smaller than a second preset value is judged; if so, determining the clock frequency in the hold state as the clock frequency.
Wherein the clock frequency in the hold state may be understood as the frequency of the local source clock after the loss of the reference source. The second preset time may be a time duration preset in the system, and the second preset time may be understood as a time duration when the reference source is lost. The second preset value may be a frequency value set in the system in advance.
The second frequency offset change value may be an average change value of the clock frequency of the local source clock in the hold state within a second preset time, and the second preset time may include a start time and an end time.
For example, a first phase difference between the local source clock and the reference source at the start time may be calculated, a second phase difference between the local source clock and the reference source at the end time may be calculated, and an absolute value of a ratio of a difference between the second phase difference and the first phase difference to a difference between the end time and the start time may be determined as the second frequency offset change value.
And continuously judging whether the second frequency offset change value is smaller than a second preset threshold, if so, determining the clock frequency in the holding state as the clock frequency, and if the second frequency offset change value of the clock frequency in the holding state relative to the reference source within a second preset time is larger than or equal to the second preset threshold, determining the clock frequency according to the last state.
Specifically, determining the clock frequency according to the previous state may include: determining a second frequency offset according to the phase value of the local source clock and the phase value of the reference source within a second time threshold; and determining the clock frequency according to the second initial frequency of the local source clock and the second frequency offset. The second initial frequency may be a clock frequency in a hold state.
The second frequency offset may be a frequency offset of the local source clock calculated after the local source clock reenters the fast lock state from the hold state.
In the present embodiment, the process of determining the clock frequency described above is similar to the process of determining the clock frequency in step S120. And calculating a second frequency offset according to the phase difference value and the time difference between the local source clock and the reference source within the current second time threshold of the system, and calculating the sum of the second frequency offset and the second initial frequency of the local source clock to obtain the clock frequency.
And S130, determining a preset frequency adjusting range according to the preset adjusting frequency variation and the clock frequency.
The preset adjustment frequency variation may be a frequency value, and the preset adjustment frequency variation may be set according to a system requirement. The preset frequency adjustment range may be a frequency range preset in the system, and the clock frequency may be adjusted within the preset frequency adjustment range.
For example, the preset frequency adjustment range may be [ clock frequency-preset adjustment frequency variation, clock frequency + preset adjustment frequency variation ].
S140, adjusting the clock frequency according to the preset frequency adjustment range to obtain a center frequency, and judging whether a first frequency offset change value of the center frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the preset frequency adjustment range.
In this embodiment, the manner of adjusting the clock frequency according to the preset frequency adjustment range may be: the voltage of the voltage-controlled pin of the frequency device in the system is changed, so that the clock frequency can be changed, and the clock frequency is adjusted to be within a preset frequency adjustment range, namely the adjusted center frequency is within the preset frequency adjustment range.
In this embodiment, the process of determining whether the first frequency offset change value of the center frequency relative to the reference source within the first preset time is smaller than the first preset value may be the same as the process of determining whether the second frequency offset change value of the clock frequency in the hold state relative to the reference source within the second preset time is smaller than the second preset value.
The first preset time may be a preset duration, the first frequency offset change value may be an average change value of a center frequency of the local source clock, the first preset value may be any frequency value preset in the system, and the first preset time may include a start time and an end time.
Specifically, a first phase difference value of the adjusted center frequency and the frequency of the reference source at the starting time is calculated, a second phase difference value of the adjusted center frequency and the frequency of the reference source at the ending time is calculated, a phase difference is obtained by subtracting the second phase difference value from the first phase difference value, the ending time is subtracted from the starting time to obtain a time difference, a ratio of the phase difference to the time difference is calculated, an absolute value is obtained to obtain a first frequency offset change value, whether the first frequency offset change value is smaller than a first preset value or not is judged, if the first frequency offset change value is smaller than the first preset value, the local source clock is judged to reach a stable locking state, and if the first frequency offset change value is not smaller than the first preset value, the operation of determining a preset frequency adjusting range according to a preset adjusting frequency variation and the clock frequency is executed again until the stable locking state is reached.
The setting range may be a preset frequency range. If the difference value between the clock frequency and the reference source frequency is within the set range, it can be determined that the local source clock enters a stable state, and if the difference value between the clock frequency and the reference source frequency is not within the set range, it can be determined that the local source clock cannot enter a stable locking state, and the clock frequency needs to be continuously adjusted.
S150, if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency change amount and the clock frequency until the stable locking state is reached.
The method for updating the center frequency may be: and calculating a new center frequency according to the center frequency and a preset adjusting frequency. Specifically, the updating of the center frequency may be calculated according to the following formula:
f 0 ′＝f 0 + K offset or f 0 ′＝f 0 -K*offset
Wherein f is 0 Is the center frequency, f 0 ' is the updated center frequency, K is the coefficient, and offset is the default adjustment frequency variation.
It should be noted that, if the first frequency offset change value is positive, the center frequency has a positive offset, and if the first frequency offset change value is negative, the center frequency has a negative offset, and the system can automatically update the center frequency according to the above formula according to whether the first frequency offset change value is positive or negative.
It should be noted that, if the first frequency offset change value is smaller than the first preset value, the center frequency does not need to be updated, and whether the local source clock reaches the stable locking state may be directly determined, and if the local source clock does not reach the stable locking state, the operation of determining the preset frequency adjustment range according to the preset adjustment frequency change amount and the clock frequency is returned to be executed until the stable locking state is reached.
Specifically, the determining whether the local source clock reaches the stable locking state may include: determining a phase offset of the clock frequency and the reference source frequency; judging whether the phase deviation is in a set range; if yes, the local source clock reaches a stable locking state; otherwise, the local source clock does not reach a stable locked state.
And returning to execute the operation of determining the adjustment range of the preset frequency according to the preset adjustment frequency and the clock frequency, wherein the clock frequency in the operation can be understood as the center frequency after the adjustment and the update, and the preset adjustment range can also be the adjustment range determined again according to the center frequency after the adjustment and the update.
In this embodiment, after the operation of determining the preset frequency adjustment range according to the preset adjustment frequency variation and the central clock frequency is performed, the clock frequency may be continuously adjusted until the local source clock reaches the stable locking state.
The method for locking the clock provided by the embodiment of the invention comprises the steps of firstly determining the last state of a local source clock when the local source clock enters a quick locking state; secondly, determining the clock frequency of the local source clock according to the last state; then determining a preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency; then, adjusting the clock frequency according to the preset frequency adjustment range to obtain a central frequency, and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the set frequency adjustment range; and finally, if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency and the clock frequency until the stable locking state is reached. The method utilizes the preset adjustment frequency variation and the clock frequency to limit the locking speed, so that the frequency of the local source clock is slowly changed in the fast locking stage.
Example two
Fig. 3 is a flowchart illustrating a clock locking method according to a second embodiment of the present invention. On the basis of the above embodiments, the process of the local source clock tracking reference source in the stable locked state will be further explained.
As shown in fig. 3, a reference source may be input into a system when a local source clock within the system is within a locked state, wherein the locked state may include a fast locked state and a steady locked state. The local source clock needs to enter a fast locking state first, and can enter a stable locking state after the frequency of the local source clock is stable.
In the fast locking stage, the clock frequency can be searched according to the system state, the locking speed of the local source clock for locking the reference source can be limited according to the clock frequency and the preset adjusting frequency, and the limitation on the central frequency can be cancelled after the local source clock enters the stable locking stage, so that the central frequency of the local source clock is a stable numerical value.
Fig. 4 is a flowchart illustrating an overall flow of a clock locking method according to a second embodiment of the present invention, and as shown in fig. 4, in the fast lock state, it may be determined that the local source clock enters the fast lock state from the preheat state or re-enters the fast lock state from the hold state according to a last state of the local source clock.
For example, after the local source clock enters the fast state from the warm-up state, the following steps may be performed:
step 1, obtaining frequency deviation according to time and a phase value, and calculating according to initial frequency and frequency deviation to obtain clock frequency.
And 2, limiting the maximum value and the minimum value of the clock frequency adjustment by using a threshold value, namely a preset frequency adjustment range.
Step 3, adjusting the clock frequency; if the clock frequency is adjusted to be within the threshold value, the center frequency is obtained, then a first frequency offset change value of the center frequency within time t1 may be calculated, and it is determined whether the first frequency offset change value is within m1 × offset, if yes, step 31 is continuously executed without updating the center frequency, and if no, step 4 is executed.
Where m1 is the attenuation coefficient, and m1 may be any value less than 1.
And step 31, judging whether the central frequency reaches a stable locking condition, entering a stable locking state if the central frequency reaches the stable locking condition, and executing step 32 if the central frequency does not reach the stable locking condition.
And step 32, returning to the step 3 again to adjust the center frequency.
And 4, if the central frequency is within the range, not updating the central frequency.
Step 5, according to a formula f 0 ′＝f 0 + K offset or f 0 ′＝f 0 -K offset updates the center frequency.
And 6, judging whether the updated central frequency reaches a stable locking condition, if so, executing the step 7, otherwise, returning to the step 2 to re-determine the threshold value according to the updated central frequency.
The stable locking condition may be to determine whether a deviation between the center frequency and the reference source frequency is within a set range.
And 7, entering a stable locking state.
For example, if the local source clock enters the fast state from the hold state, the following steps may be performed:
step 1, judging whether the clock frequency in the holding state is within m2 × offset relative to a second frequency offset change value of the reference source within a holding time t2, namely a second preset time, if so, determining the frequency in the holding state as the clock frequency, and otherwise, executing step 2.
Where m2 is the attenuation coefficient, and m2 may be any value less than 1.
And 2, solving a second frequency offset according to the time and the phase value, and calculating a new clock frequency.
And step 3, re-determining the adjustment range according to the new clock frequency and the preset adjustment frequency.
And 4, adjusting the new clock frequency to an adjustment range, and calculating whether a second frequency offset change value of the adjusted center frequency relative to the reference source is within m2 × offset, if so, executing step 41 without updating the adjusted center frequency, otherwise, continuing to execute step 5.
And step 41, judging whether the adjusted center frequency reaches a stable condition, if so, entering a stable state, and if not, returning to the step 3 again.
Step 5, according to a formula f 0 ′＝f 0 + K offset or f 0 ′＝f 0 -K x offset updates the adjusted center frequency.
And 6, judging whether the updated center frequency reaches a stable locking condition, if so, executing the step 7, otherwise, returning to the step 3 again.
And 7, entering a stable locking state.
The clock locking method provided by the second embodiment of the invention can ensure that the frequency of the local source clock in the fast locking stage is slowly changed, thereby ensuring the stability of the system and ensuring the fast availability.
EXAMPLE III
Fig. 5 is a schematic structural diagram of a clock locking apparatus according to a third embodiment of the present invention, where the apparatus is applicable to a situation where a local source clock tracks and locks a time service source clock, where the apparatus may be implemented by software and/or hardware and is generally integrated on a communication device.
As shown in fig. 5, the apparatus includes: a first determination module 510, a second determination module 520, a third determination module 530, an adjustment module 540, and an update module 550.
A first determining module 510, configured to determine a last state of a local source clock when the local source clock enters a fast lock state;
a second determining module 520, configured to determine a clock frequency of the local source clock according to the previous state;
a third determining module 530, configured to adjust the frequency variation according to a preset adjustment value and the frequency variation
The clock frequency determines a preset frequency adjustment range;
the adjusting module 540 is configured to adjust the clock frequency according to the preset frequency adjustment range to obtain a center frequency, and determine whether a first frequency offset variation value of the center frequency relative to a reference source within a first preset time is smaller than a first preset value; wherein the center frequency is within the set frequency adjustment range;
an updating module 550, configured to update the center frequency if the first frequency offset variation value is greater than or equal to a first preset value; and judging whether the local source clock reaches a stable locking state, if not, returning to execute the operation of determining the preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency until reaching the stable locking state.
In this embodiment, the apparatus is first used for determining a previous state of a local source clock when the local source clock enters a fast locking state through a first determining module; secondly, a second determining module is used for determining the clock frequency of the local source clock according to the last state; then, a third determining module is used for determining a preset frequency adjusting range according to a preset adjusting frequency variation and the clock frequency; then, an adjusting module is used for adjusting the clock frequency according to the preset frequency adjusting range to obtain a center frequency, and judging whether a first frequency offset change value of the center frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the set frequency adjustment range; finally, the updating module is used for updating the center frequency if the first frequency offset change value is greater than or equal to a first preset value; and judging whether the local source clock reaches a stable locking state, if not, returning to execute the operation of determining the preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency until reaching the stable locking state.
The embodiment provides a clock locking device, which can limit the locking speed by using the preset adjustment frequency variation and the clock frequency, so that the frequency of the local source clock slowly changes in the fast locking stage.
Further, the updating module 550 includes an adjustment state unit, and the adjustment state unit is configured to determine whether the local source clock reaches a stable locking state if the first frequency offset variation value is smaller than the first preset value, and return to perform an operation of determining a preset frequency adjustment range according to a preset adjustment frequency and the center frequency until the stable locking state is reached if the local source clock does not reach the stable locking state.
Further, the second determining module 520 is specifically configured to determine, if the previous state is the preheating state, the first frequency offset according to the phase value of the reference source and the phase value of the local source clock within the first time threshold; and determining the clock frequency according to the first initial frequency of the local source clock and the first frequency offset.
Further, the second determining module 520 is specifically configured to determine whether a second frequency offset variation value of the clock frequency in the hold state relative to the reference source within a second preset time is smaller than a second preset value if the previous state is the hold state; if so, determining the clock frequency in the hold state as the clock frequency.
Further, the second determining module 520 further includes a clock frequency determining unit, where the clock frequency determining unit is configured to determine a second frequency offset according to the phase value of the local source clock and the phase value of the reference source within a second time threshold; and determining the clock frequency according to the second initial frequency of the local source clock and the second frequency offset.
Further, the updating module 450 further includes a calculating unit, configured to update the center frequency according to the following formula:
f 0 ′＝f 0 + K x offset or f 0 ′＝f 0 -K*offset
Wherein f is 0 Is the center frequency, f 0 ' is the updated center frequency, K is the coefficient, and offset is the preset adjustment frequency.
Further, the update module 550 further includes a determining unit, configured to determine whether the local source clock reaches a stable locking state, including: determining a phase offset of the center frequency and the reference source frequency; judging whether the phase deviation is in a set range; if yes, the local source clock reaches a stable locking state; otherwise, the local source clock does not reach a stable locked state.
The clock locking device can execute the clock locking method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Example four
Fig. 6 is a schematic structural diagram of a communication device according to a fourth embodiment of the present invention. As shown in fig. 6, a communication device according to a fourth embodiment of the present invention includes: one or more processors 61 and storage 62; the processor 61 in the communication device may be one or more, and fig. 5 illustrates one processor 61 as an example; storage 62 is used to store one or more programs; the one or more programs are executed by the one or more processors 61, such that the one or more processors 61 implement a method of clock locking as described in any of the embodiments of the present invention.
The communication device may further include: an input device 63 and an output device 64.
The processor 61, the storage means 62, the input means 63 and the output means 64 in the communication device may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 5.
The storage device 62 in the communication apparatus, which is a computer-readable storage medium, can be used to store one or more programs, which may be software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to one or two methods for clock locking according to one or two embodiments of the present invention (for example, modules in a clock-locked device shown in fig. 5 include a first determining module 510, a second determining module 520, a third determining module 530, an adjusting module 540, and an updating module 550). The processor 61 executes various functional applications and data processing of the communication device, i.e., a method of implementing clock locking in the above-described method embodiments, by executing software programs, instructions, and modules stored in the storage device 62.
The storage device 62 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the communication apparatus, and the like. Further, the storage device 62 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the storage device 62 may further include memory located remotely from the processor 61, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 63 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function control of the communication apparatus. The output device 64 may include a display device such as a display screen.
And when the one or more programs comprised by the above-mentioned communication device are executed by the one or more processors 61, the programs perform the following operations:
when a local source clock enters a fast locking state, determining a last state of the local source clock;
determining the clock frequency of the local source clock according to the last state;
determining a preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency;
adjusting the clock frequency according to the preset frequency adjustment range to obtain a central frequency, and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein, the central frequency is within the set frequency adjusting range;
and if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency change and the clock frequency until the stable locking state is reached.
EXAMPLE five
An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program is used to execute a method for clock locking when executed by a processor, and the method includes:
when a local source clock enters a fast locking state, determining a last state of the local source clock;
determining the clock frequency of the local source clock according to the last state;
determining a preset frequency adjustment range according to the preset adjustment frequency variation and the clock frequency;
adjusting the clock frequency according to the preset frequency adjustment range to obtain a central frequency, and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the set frequency adjustment range;
and if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency change amount and the clock frequency until the stable locking state is reached.
Optionally, the program, when executed by a processor, may be further configured to perform a method for clock locking according to any of the embodiments of the present invention.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a flash Memory, an optical fiber, a portable CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. A computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take a variety of forms, including, but not limited to: an electromagnetic signal, an optical signal, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, Radio Frequency (RF), etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.

Claims (10)

1. A method of clock locking, comprising:
determining a last state of a local source clock when the local source clock enters a fast lock state;
determining the clock frequency of the local source clock according to the last state;
determining a preset frequency adjusting range according to a preset adjusting frequency variation and the clock frequency;
adjusting the clock frequency according to the preset frequency adjustment range to obtain a central frequency, and judging whether a first frequency offset change value of the central frequency relative to a reference source in a first preset time is smaller than a first preset value; wherein the center frequency is within the preset frequency adjustment range;
and if the first frequency deviation change value is larger than or equal to a first preset value, updating the center frequency, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency change amount and the clock frequency until the stable locking state is reached.
2. The method of claim 1, after determining whether a first frequency offset variation value of the adjusted center frequency relative to the reference source within a first preset time is smaller than a first preset value, further comprising:
and if the first frequency deviation change value is smaller than a first preset value, judging whether the local source clock reaches a stable locking state, and if not, returning to execute the operation of determining a preset frequency adjustment range according to a preset adjustment frequency and the central frequency until the stable locking state is reached.
3. The method of claim 1, wherein determining a clock frequency based on the previous state comprises:
if the last state is a preheating state, determining a first frequency offset according to a phase value of a reference source and a phase value of a local source clock within a first time threshold;
and determining the clock frequency according to the first initial frequency of the local source clock and the first frequency offset.
4. The method of claim 1, wherein determining a clock frequency based on the previous state comprises:
if the last state is a holding state, judging whether a second frequency offset change value of the clock frequency in the holding state relative to the reference source within a second preset time is smaller than a second preset value;
if so, determining the clock frequency in the hold state as the clock frequency.
5. The method of claim 4, wherein if the clock frequency in the hold state is greater than or equal to a second predetermined value within a second predetermined time relative to a second frequency offset variation value of the reference source, determining the clock frequency according to the previous state comprises:
determining a second frequency offset according to the phase value of the local source clock and the phase value of the reference source within a second time threshold;
and determining the clock frequency according to the second initial frequency of the local source clock and the second frequency offset.
6. The method of claim 1, wherein updating the center frequency is calculated according to the following equation:
f 0 ′＝f 0 + K offset or f 0 ′＝f 0 -K*offset
Wherein f is 0 Is the center frequency, f 0 ' is the updated center frequency, K is the coefficient, and offset is the default adjustment frequency variation.
7. The method of claim 1, wherein determining whether the local source clock reaches a stable locked state comprises:
determining a phase offset of the center frequency and the reference source frequency;
judging whether the phase deviation is in a set range;
if yes, the local source clock reaches a stable locking state; otherwise, the local source clock does not reach a stable locked state.
8. An apparatus for clock locking, comprising:
the device comprises a first determining module, a second determining module and a third determining module, wherein the first determining module is used for determining the last state of a local source clock when the local source clock enters a quick locking state;
a second determining module, configured to determine a clock frequency of the local source clock according to the previous state;
the third determining module is used for determining a preset frequency adjusting range according to a preset adjusting frequency variation and the clock frequency;
the adjusting module is used for adjusting the clock frequency according to the preset frequency adjusting range and judging whether a first frequency offset change value of the adjusted clock frequency relative to a reference source is smaller than a first preset value within a first preset time; wherein, the adjusted clock frequency is within the set frequency adjusting range;
the updating module is used for updating the clock frequency if the first frequency offset change value is greater than or equal to a first preset value; and judging whether the local source clock reaches a stable locking state, if not, returning to execute the operation of determining the adjustment range of the preset frequency according to the preset adjustment frequency and the clock frequency until the stable locking state is reached.
9. A communication device, comprising:
one or more processors;
storage means for storing one or more programs;
the one or more programs being executable by the one or more processors to cause the one or more processors to perform a method of clock locking as recited in any one of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out a method of clock locking according to any one of claims 1 to 7.
CN202011630437.5A 2020-12-31 2020-12-31 Clock locking method, device, equipment and storage medium Active CN112838861B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011630437.5A CN112838861B (en) 2020-12-31 2020-12-31 Clock locking method, device, equipment and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011630437.5A CN112838861B (en) 2020-12-31 2020-12-31 Clock locking method, device, equipment and storage medium

Publications (2)

Publication Number Publication Date
CN112838861A CN112838861A (en) 2021-05-25
CN112838861B true CN112838861B (en) 2022-08-26

Family

ID=75924835

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011630437.5A Active CN112838861B (en) 2020-12-31 2020-12-31 Clock locking method, device, equipment and storage medium

Country Status (1)

Country Link
CN (1) CN112838861B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101222288A (en) * 2008-02-01 2008-07-16 华为技术有限公司 IP network transmission method, system and equipment automatically adapting network jitter
CN101557228A (en) * 2008-04-10 2009-10-14 联咏科技股份有限公司 Phase-lock loop system and phase-lock method of phase-lock loop
CN106100781A (en) * 2016-05-20 2016-11-09 中国南方电网有限责任公司电网技术研究中心 Clock tracking method and system based on E1 channel
CN107135179A (en) * 2017-04-10 2017-09-05 京信通信系统（广州）有限公司 A kind of device frequency calibration method and equipment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100488082C (en) * 2003-07-28 2009-05-13 华为技术有限公司 Clock source frequency shift detecting method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101222288A (en) * 2008-02-01 2008-07-16 华为技术有限公司 IP network transmission method, system and equipment automatically adapting network jitter
CN101557228A (en) * 2008-04-10 2009-10-14 联咏科技股份有限公司 Phase-lock loop system and phase-lock method of phase-lock loop
CN106100781A (en) * 2016-05-20 2016-11-09 中国南方电网有限责任公司电网技术研究中心 Clock tracking method and system based on E1 channel
CN107135179A (en) * 2017-04-10 2017-09-05 京信通信系统（广州）有限公司 A kind of device frequency calibration method and equipment

Also Published As

Publication number Publication date
CN112838861A (en) 2021-05-25

Similar Documents

Publication Publication Date Title
KR102204733B1 (en) Method, device, and server for account login
US10659830B2 (en) Method, system, mobile device, apparatus and computer program product for validating rights objects
CN109766103B (en) Method and apparatus for processing information
WO2017041531A1 (en) Timeout wait duration update method and device
CN111459523A (en) Image quality chip software upgrading method and device, electronic equipment and storage medium
CN112347111A (en) Data updating method and device
CN112838861B (en) Clock locking method, device, equipment and storage medium
US9218295B2 (en) Methods and systems for implementing time-locks
CN112422551A (en) SSL certificate updating method and device, electronic equipment and storage medium
CN115421764A (en) Method, device, equipment and storage medium for identifying module to be upgraded
CN113347083B (en) Network path determination and switching method, device, equipment, medium and program product
CN113407916A (en) Information processing method, device, terminal and storage medium
CN113542022A (en) Networking management method and device of networking system, terminal equipment and storage medium
CN103647647A (en) Automatic correction method for time migration of dynamic password at server side
CN112559898A (en) Item information sending method, item information sending device, electronic equipment and computer readable medium
CN110649913B (en) Frequency adjustment method and device for crystal oscillator, storage medium and electronic equipment
CN116560716A (en) APP construction method, device, equipment and storage medium
CN106293814A (en) Upgrade method and device
CN113824675B (en) Method and device for managing login state
CN110445869B (en) Content publishing method, terminal and server based on distributed subscription
EP3783495B1 (en) Exclusive control system and exclusive control method
CN108712497B (en) Application mode sharing method, device and system
CN112507676A (en) Energy report generation method and device, electronic equipment and computer readable medium
US9473293B2 (en) Systems and methods for operating radio transceivers
CN115633354B (en) Terminal identity authentication method, device, equipment and medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: 523000 Room 401 and 402, building 5, No. 24, industrial East Road, Songshanhu Park, Dongguan City, Guangdong Province

Applicant after: Guangdong daguangxin Technology Co.,Ltd.

Address before: 523808 the first, second and third floors of building 16, small and medium-sized science and technology enterprise Pioneer Park, North Industrial City, Songshanhu high tech Industrial Development Zone, Dongguan City, Guangdong Province

Applicant before: Guangdong Dapu Telecom Technology Co.,Ltd.

GR01 Patent grant
GR01 Patent grant