CN115361003A

CN115361003A - Delay chain control circuit

Info

Publication number: CN115361003A
Application number: CN202210974803.1A
Authority: CN
Inventors: 石欢
Original assignee: Ruizhe Hangzhou Technology Co ltd
Current assignee: Ruizhe Hangzhou Technology Co ltd
Priority date: 2022-08-15
Filing date: 2022-08-15
Publication date: 2022-11-18

Abstract

The application relates to the technical field of digital circuits, and provides a delay chain control circuit which comprises a fine adjustment delay module, a coarse adjustment unit, a thermometer decoding module and a two-way selector; the fine adjustment delay module comprises at least one fine adjustment unit; the thermometer decoding module is used for acquiring service scene requirements and controlling the number of the selected fine tuning units based on the service scene requirements; the coarse tuning unit is connected with the input end of the fine tuning delay module and is used for carrying out first time delay on the input signal; the output end of the fine adjustment delay module is connected with the two-way selector and used for performing second time delay on the input signals based on the determined number of fine adjustment units; the two-way selector is used for determining whether the input signal subjected to the second time delay needs to be delayed continuously or not based on the service scene requirement so as to meet the service scene requirement. Therefore, the delay chain control circuit can perform delay adjustment under different service requirements, has uniformity and can perform accurate delay adjustment.

Description

Delay chain control circuit

Technical Field

The application relates to the technical field of digital circuits, in particular to a delay chain control circuit.

Background

The delay chain circuit is widely applied To a large-scale Digital circuit, and in structures such as a Phase Locked Loop (PLL), a Digital Delay Locked Loop (DLL), a Time To Digital Converter (TDC), and the like, a delay chain circuit with uniform delay is important, and meanwhile, the delay chain circuit is also often applied To a memory interface circuit and used for timing training between a clock and data in a read-write process.

In the prior art, an analog controlled delay chain circuit is usually used, and under the control of the delay chain circuit, an input signal is delayed and then output based on a complex analog unit, so that digital change of delay chain delay is realized, and different delays are achieved.

However, the uniformity of the delay chain circuit is poor, and the accuracy and stability of the whole delay chain circuit are affected due to high power consumption.

Disclosure of Invention

The application provides a delay chain control circuit for under different business scene demands, all can carry out the delay adjustment, and have the linearity, improve delay chain control circuit's homogeneity, and then can carry out accurate delay adjustment.

Specifically, the application provides a delay chain control circuit, which comprises a fine adjustment delay module, a coarse adjustment unit, a thermometer decoding module and a two-way selector; the fine adjustment delay module comprises at least one fine adjustment unit; the thermometer decoding module is used for acquiring service scene requirements and controlling the number of the selected fine-tuning units based on the service scene requirements;

the coarse adjusting unit is connected with the input end of the fine adjusting delay module and is used for receiving an input signal and delaying the input signal for the first time;

the output end of the fine adjustment delay module is connected with the two-way selector, and the fine adjustment delay module is used for receiving the input signals subjected to the first time delay and performing second time delay on the input signals based on the fine adjustment units with the determined number;

the two-way selector is used for receiving the input signal subjected to the second time delay and determining whether the input signal needs to be delayed continuously or not based on the service scene requirement so as to meet the service scene requirement.

Optionally, the fine tuning unit includes: the N-type field effect transistor, the P-type field effect transistor, the first switch tube and the second switch tube;

the N-type field effect transistor is connected with the first switching tube; the N-type field effect transistor is used for controlling the first switch tube to be opened when an input signal is at a high level;

the P-type field effect transistor is connected with the second switch tube; and the P-type field effect transistor is used for controlling the second switch tube to be opened when the input signal is at a low level.

Optionally, a G pole of the N-type field effect transistor is connected to the input end of the fine adjustment unit, and is configured to receive an input signal; the S pole of the N-type field effect transistor is connected with the first switch tube, and the D pole of the N-type field effect transistor is connected with the output end of the fine adjustment unit and used for outputting an input signal;

the G pole of the P-type field effect transistor is connected with the input end of the fine adjustment unit and used for receiving an input signal; and the S pole of the P-type field effect transistor is connected with the second switch tube, and the D pole of the P-type field effect transistor is connected with the output end of the fine adjustment unit and used for outputting an input signal.

Optionally, when the input signal is at a high level, the N-type field effect transistor is in a conducting state, and the P-type field effect transistor is in a closing state, so that the N-type field effect transistor delays the input signal;

when the input signal is in a high level, the P-type field effect transistor is in a conducting state, and the N-type field effect transistor is in a closing state, so that the P-type field effect transistor delays the input signal.

Optionally, the fine tuning unit further includes: a first resistor and a second resistor;

one end of the first resistor is connected with the first switch tube, the other end of the first resistor is connected with a power supply, and the first resistor is used for dividing the voltage of the input signal;

one end of the second resistor is connected with the second switch tube, the other end of the second resistor is connected with the ground, and the second resistor is used for dividing the voltage of the input signal.

Optionally, the delay chain control circuit further includes a coarse delay module, where the coarse delay module includes at least one coarse tuning unit;

the thermometer decoding module is also used for controlling the number of the coarse tuning units based on the service scene requirement;

and after determining that the input signal needs to be delayed continuously, the two-way selector transmits the input signal to a corresponding number of coarse adjusting units selected based on the thermometer decoding module for delaying.

Optionally, the thermometer decoding module is specifically configured to:

when the delay time of the input signal after the second time delay meets the requirement of a service scene, controlling the total number of the coarse tuning units to be 1;

when the delay time of the input signal after the second time delay does not meet the requirement of a service scene, controlling the total number of the coarse tuning units to be M +1; m is a positive integer greater than 1.

Optionally, the delay step of the coarse tuning unit is n times of the delay step of the fine tuning unit; n is a positive integer greater than 1; the delay step length is used for controlling the delay of the delay chain control circuit to be regular.

Optionally, the coarse tuning unit includes: a first NAND gate, a second NAND gate and a third NAND gate;

the first input end of the first NAND gate is used for receiving input signals, and the second input end of the first NAND gate is used for receiving high-level signals; the output end of the first NAND gate is connected with the first input end of the third NAND gate;

the first input end of the second nand gate is also used for receiving input signals, and the second input end of the second nand gate is used for receiving low-level signals; the output end of the second nand gate is connected with the second input end of the third nand gate, and the output end of the third nand gate is used for outputting the delayed input signal.

Optionally, the coarse tuning unit further includes: a fourth NAND gate;

the first input end of the fourth NAND gate is connected with the output end of the first NAND gate, the second input end of the fourth NAND gate is connected with the output end of the second NAND gate, and the fourth NAND gate is used for controlling the output load balance of the first NAND gate and the second NAND gate.

In summary, the present application provides a delay chain control circuit, which includes a fine adjustment delay module, a coarse adjustment unit, a thermometer decoding module, and a two-way selector; the fine adjustment delay module comprises at least one fine adjustment unit; specifically, the service scene requirements can be acquired through the thermometer decoding module, and the number of the selected fine-tuning units is controlled based on the service scene requirements; further, a coarse adjusting unit is used for receiving input signals, the input signals are delayed for the first time, the input signals subjected to the first time delay are transmitted to a fine adjusting delay module, and the fine adjusting delay module delays the input signals for the second time based on the determined number of fine adjusting units; further, the two-way selector determines whether the input signal subjected to the second time delay needs to be delayed continuously or not based on the service scene requirement, if so, the two-way selector continues to perform delay processing so as to meet the service scene requirement; if not, outputting the input signal after time delay. Therefore, the delay chain control circuit provided by the application provides fine adjustment linearity based on the fine adjustment units in the fine adjustment delay module, so that the delay chain control circuit has uniformity and can perform accurate delay adjustment, and the number of the fine adjustment units is determined based on service scene requirements, so that different service requirements can be met, and delay adjustment can be performed under different service requirements.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a delay chain control circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a fine delay module according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a fine adjustment unit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of an N-type field effect transistor and a P-type field effect transistor provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of a specific fine adjustment unit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a coarse tuning unit according to an embodiment of the present disclosure;

FIG. 8A is a schematic diagram of a delay chain circuit corresponding to a range of delay steps;

fig. 8B is a schematic diagram of a range of delay step lengths corresponding to a delay chain control circuit according to an embodiment of the present disclosure;

fig. 9 is a broken-line diagram of a delay step corresponding to a delay chain control circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a coarse tuning unit according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of another coarse tuning unit provided in the embodiment of the present application;

fig. 12 is a schematic structural diagram of a specific delay chain control circuit according to an embodiment of the present disclosure.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. The drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.

In the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same or similar items having substantially the same function and action. For example, the first device and the second device are only used for distinguishing different devices, and the sequence order thereof is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a alone, A and B together, and B alone, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

The following describes an embodiment of the present application with reference to the accompanying drawings, and fig. 1 is a schematic view of an application scenario provided by the embodiment of the present application, and a delay chain control circuit provided by the present application may be applied to the application scenario shown in fig. 1. The application scenario includes: memory 101 and chip in memory 102; the chip 102 includes an interface circuit therein; specifically, the interface circuit includes a delay chain control circuit, which is used for performing delay processing on the input signal, so as to meet the delay requirements in different application scenarios.

In one possible implementation, an analog controlled delay chain circuit is usually used, and under the control of the delay chain circuit, the input signal is delayed and then output based on a complex analog unit, so as to implement digital change of delay chain delay, and achieve different delays.

Therefore, the application provides a delay chain control circuit, this delay chain control circuit is through designing fine tuning delay module, fine tuning delay module comprises a plurality of fine tuning unit, every fine tuning unit can provide the linearity of fine tuning for the time delay step length is more even, and the number of fine tuning unit is confirmed based on business scene demand, can satisfy different business demands, like this, based on fine tuning unit and coarse tuning unit mutually support, carry out the time delay to the input signal, make under different business demands, all can carry out accurate time delay adjustment, and because fine tuning unit provides the linearity, make delay chain control circuit have the homogeneity, the stability of delay chain control circuit delay adjustment has been improved.

It should be noted that, with the continuous increase of the interface speed of the memory, the inherent delay of the delay chain circuit in the DLL inside the memory interface is required to be small, otherwise the locking will fail, and the delay chain control circuit provided by the application has linearity, improves the uniformity of the delay chain circuit, and makes the read-write training have good effect.

The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 2 is a schematic structural diagram of a delay chain control circuit according to an embodiment of the present disclosure, as shown in fig. 2, the delay chain control circuit includes a fine delay adjustment module 201, a coarse adjustment unit 202, a thermometer decoding module 203, and a two-way selector (Mux) 204; the fine-tuning delay module 201 comprises at least one fine-tuning unit 2011; the thermometer decoding module 203 is configured to obtain a service scene requirement, and control and select the number of the fine-tuning units 2011 based on the service scene requirement;

the coarse tuning unit 202 is connected to an input end of the fine tuning delay module 201, and the coarse tuning unit 202 is configured to receive an input signal and perform a first time delay on the input signal;

the output end of the fine adjustment delay module 201 is connected to the two-way selector 204, and the fine adjustment delay module 201 is configured to receive an input signal that is subjected to the first time delay, and perform the second time delay on the input signal based on a determined number of fine adjustment units 2011;

the two-way selector 204 is configured to receive the input signal subjected to the second time delay, and determine whether the input signal needs to be delayed continuously based on the service scene requirement, so as to meet the service scene requirement.

In this embodiment, a service scenario requirement may refer to a delay time required by the delay chain control circuit in a certain service scenario, where the delay time is determined by an external control code, and the external control code refers to the number of fine tuning units and coarse tuning units required in the service scenario, where the fine tuning units and the coarse tuning units both correspond to delay steps, and the delay steps corresponding to the coarse tuning units and the delay steps corresponding to the fine tuning units are in a multiple relationship, that is, the delay steps corresponding to the fine tuning units =1/n delay steps corresponding to the coarse tuning units, and thus, the design may enable the delay of the delay chain control circuit to have linearity, n is a positive integer greater than 1, and the smaller n is, the more accurate the adjustable precision of the delay chain control circuit is.

The fine-tuning delay module 201 includes at least one fine-tuning unit 2011, fig. 3 is a schematic structural diagram of the fine-tuning delay module provided in an embodiment of the present application, and as shown in fig. 3, the fine-tuning delay module 201 has two input ends, i.e., input 1 and input 2, where the two input ends are used to determine a delay range of the fine-tuning delay module 201, i.e., determine the number of the fine-tuning units 2011 based on the service scene requirement, and perform delay using the fine-tuning units 2011 with the determined number.

Specifically, whether the input signal needs to be delayed continuously is determined based on the service scene requirement, that is, whether the input signal needs to be delayed continuously is determined through a selection signal of the two-way selector, the selection signal is determined by an external control code at the lowest position, a sel end of the two-way selector is determined based on a value corresponding to the external control code, if the sel end of the two-way selector is determined to be a 0-way signal based on the external control code, the input signal is output to a corresponding number of coarse tuning units for delay processing so as to meet the service scene requirement, and if the sel end of the two-way selector is determined to be a 1-way signal based on the external control code, the input signal is directly output; the embodiment of the application does not specifically limit the value of the external control code corresponding to the sel end of the two-way selector, can set a preset value and also can manually modify the preset value, and different business scenes are suitable for different values.

It should be noted that the selection signal of the two-way selector is provided based on the selection signal generating circuit, when the high bits of the external control code are all 0, the 0-way signal is selected, otherwise, the 1-way signal is selected, and if the high bits of the external control code are 001, the 1-way signal is selected.

Therefore, the application provides a delay chain control circuit, which can acquire service scene requirements through a thermometer decoding module and control the number of selected fine-tuning units based on the service scene requirements; further, a coarse adjusting unit is used for receiving input signals, the input signals are delayed for the first time, the input signals subjected to the first time delay are transmitted to a fine adjusting delay module, and the fine adjusting delay module delays the input signals for the second time based on the determined number of fine adjusting units; further, the two-way selector determines whether the input signal subjected to the second time delay needs to be delayed continuously or not based on the service scene requirement, and if so, the two-way selector continues to perform delay processing to meet the service scene requirement; if not, outputting the input signal after time delay. Therefore, the delay chain control circuit provided by the application provides fine adjustment linearity based on the fine adjustment units in the fine adjustment delay module, so that the delay chain control circuit has uniformity and can perform accurate delay adjustment, and the number of the fine adjustment units is determined based on service scene requirements, so that different service requirements can be met, and delay adjustment can be performed under different service requirements.

Optionally, fig. 4 is a schematic structural diagram of a fine adjustment unit provided in the embodiment of the present application, and as shown in fig. 4, the fine adjustment unit 2011 includes: an N-type field effect transistor 211, a P-type field effect transistor 212, a first switch tube 213 and a second switch tube 214;

the N-type field effect transistor 211 is connected to the first switch tube 213; the N-type fet 211 is configured to control the first switch tube 213 to be turned on when the input signal is at a high level;

the P-type fet 212 is connected to the second switch tube 214; the P-type fet 212 is configured to control the second switch 214 to be turned on when the input signal is at a low level.

In the embodiment of the present application, each of the N-type field effect transistor 211 and the P-type field effect transistor 212 has a time delay function, and when an input signal flows through the N-type field effect transistor 211 and the P-type field effect transistor 212, a voltage value corresponding to the input signal is required to rise to a saturation value, and then the input signal can be in a conduction state, and the input signal rises to the saturation value, and a certain time is required.

Specifically, the N-type field effect transistor 211 and the P-type field effect transistor 212 are arranged to adapt to the level of different input signals, when the input signal is at a high level, the input signal is delayed through a circuit in which the N-type field effect transistor 211 is connected with the first switch tube 213, and at this time, the N-type field effect transistor controls the first switch tube 213 to be turned on; when the input signal is at a low level, the input signal is delayed through a circuit connecting the pfet 212 and the second switch tube 214, and the pfet controls the second switch tube 214 to be turned on.

Therefore, the embodiment of the application can utilize the fine adjustment unit to perform time delay adjustment, and corresponding time delay circuits can be selected for different levels of input signals, so that the application flexibility is provided.

Optionally, fig. 5 is a schematic structural diagram of an N-type field effect transistor and a P-type field effect transistor provided in the embodiment of the present application, and as shown in fig. 5, a G pole of the N-type field effect transistor 211 is connected to an input end of the fine adjustment unit 2011, and is configured to receive an input signal; the S pole of the N-type fet 211 is connected to the first switching tube 213, and the D pole of the N-type fet 211 is connected to the output end of the fine adjustment unit 2011, so as to output an input signal;

the G pole of the pfet 212 is connected to the input terminal of the fine adjustment unit 2011, and is configured to receive an input signal; the S pole of the P-type fet 212 is connected to the second switch tube 214, and the D pole of the P-type fet 212 is connected to the output end of the fine adjustment unit 2011, so as to output an input signal.

It can be understood that by designing the N-type fet 211 and the P-type fet 212 to receive input signals in different scenarios, the response speed of the circuit can be increased, without relying on a relay, so that the circuit is simplified, and the cost is saved.

Optionally, when the input signal is at a high level, the N-type field effect transistor 211 is in an on state, and the P-type field effect transistor 212 is in an off state, so that the N-type field effect transistor 211 delays the input signal;

when the input signal is at a high level, the P-type fet 212 is in a conducting state, and the N-type fet 211 is in a closing state, so that the P-type fet 212 delays the input signal.

Specifically, the N-type field effect transistor 211 and the P-type field effect transistor 212 form a complementary field effect transistor circuit, an N-type conduction channel can be formed when the N-type field effect transistor 211 is turned on, and a P-type conduction channel can be formed when the P-type field effect transistor 212 is turned on, so that the complementary field effect transistor circuit can be directly connected with any other integrated circuit without considering the load problem of current when being connected.

Therefore, the complementary field effect transistor circuit formed in the embodiment of the application can be directly connected with any integrated circuit, is suitable for input signals under different service scenes, and further delays the input signals, so that the practicability is improved.

It should be noted that since the high level of the output of the N fet 211 is lower than the input high level of the complementary fet circuit, voltage division needs to be performed using one resistor, and the low level of the output of the P fet 212 is lower than the input low level of the complementary fet circuit, voltage division needs to be performed using one resistor.

Optionally, fig. 6 is a schematic structural diagram of a specific fine adjustment unit provided in an embodiment of the present application, and as shown in fig. 6, the fine adjustment unit 2011 further includes: a first resistor 215 and a second resistor 216;

one end of the first resistor 215 is connected to the first switch 213, the other end of the first resistor 215 is connected to a power supply (VDD), and the first resistor 215 is configured to divide the input signal;

one end of the second resistor 216 is connected to the second switch tube 214, the other end of the second resistor 216 is connected to ground, and the second resistor 216 is used for dividing the voltage of the input signal.

In the embodiment of the present application, in the circuit corresponding to the fine tuning unit, the first resistor 215 is added in the circuit corresponding to the N-type fet 211, and the second resistor 216 is added in the circuit corresponding to the P-type fet 212, so as to divide the voltage of the input signal, which is beneficial to the stability of the input signal.

Optionally, the resistor is a source degeneration resistor, and the type of the resistor is not specifically limited in this embodiment.

Therefore, the stability of the delay chain control circuit can be controlled by adding the resistor at the corresponding position in the circuit corresponding to the fine adjustment unit.

Optionally, fig. 7 is a schematic structural diagram of a coarse tuning unit according to an embodiment of the present application, and as shown in fig. 7, the delay chain control circuit further includes a coarse tuning delay module 701, where the coarse tuning delay module 701 includes at least one coarse tuning unit 7011;

the thermometer decoding module 203 is further configured to control the number of the coarse tuning units 7011 to be selected based on the service scene requirement;

after determining that the input signal needs to be delayed continuously, the two-way selector 204 transmits the input signal to a corresponding number of coarse tuning units selected based on the thermometer decoding module 203 for delaying.

In the embodiment of the application, because the adjustable range corresponding to the coarse tuning unit is large, for example, 30ps tuning can be performed, and the adjustable range corresponding to the fine tuning unit is small, for example, 5ps tuning can be performed, therefore, a delay chain control circuit formed by combining the coarse tuning unit and the fine tuning unit is utilized, when the service scene requirement is high, a certain number of coarse tuning units are selected, and then, under the service scene requirement, after the residual delay requirement is low, a certain number of fine tuning units are selected, and if the delay corresponding to the service scene requirement is 65ps, the delay chain control circuit can select two 30ps coarse tuning units and one 5ps fine tuning unit.

Specifically, the thermometer decoding module 203 controls and selects the number of the coarse tuning unit 7011 and the fine tuning unit 2011 based on the service scenario requirement, and after the input signal is subjected to the first time delay through the coarse tuning unit 202 and the second time delay through the fine tuning unit 2011 of a certain number, the input signal subjected to the second time delay is sent to the two-way selector 204, so that the two-way selector 204 transmits the input signal to the coarse tuning unit 7011 of a corresponding number selected based on the thermometer decoding module 203 for time delay after determining that the input signal subjected to the second time delay needs to be further delayed.

It should be noted that the thermometer decoding module may be divided into a coarse tuning thermometer code module and a fine tuning thermometer code module, the coarse tuning thermometer code module is configured to control the number of the coarse tuning units selected, and the fine tuning thermometer code module is configured to control the number of the fine tuning units selected.

Therefore, the embodiment of the application can utilize the delay chain control circuit formed by combining the coarse adjustment unit and the fine adjustment unit to perform delay adjustment on the input signal, so that the flexibility of adjustment is improved.

Optionally, the thermometer decoding module is specifically configured to:

when the delay time of the input signal after the second time delay meets the requirement of a service scene, controlling the total number of the coarse adjusting units to be 1;

Specifically, the thermometer decoding module may be formed by a thermometer decoder, and the thermometer decoder is configured to analyze data resource allocation, that is, select a proper number of coarse tuning units and fine tuning units based on a service scene requirement, where if the service scene requirement is 105ps, a delay time after the second time delay is 45ps, and the delay time does not meet the service scene requirement, the number of coarse tuning units of 30ps needs to be selected to be 2, and it is determined that the total number of the selected coarse tuning units is 2+1= 3.

Therefore, the embodiment of the application can select a proper number of coarse tuning units to perform delay tuning, improve the flexibility of application, and meet the delay requirement without a service scene.

In the embodiment of the application, the more uniform the design of the delay step length is, the better the linearity is, the finer the precision of the delay chain control circuit is, the higher the stability is, the delay step length of the coarse adjustment unit is set to be n times of the delay step length of the fine adjustment unit, so that the delay of the delay chain control circuit is regular, and the total delay from input to output of an input signal in the delay chain control circuit is convenient to calculate; specifically, the total delay is calculated as follows:

Delay_total＝Delay_intrinsic+Code*Delay step

the Delay _ total represents the total Delay of the Delay chain control circuit, the Delay _ inrinsic represents the inherent Delay, the Code represents the external control Code, and the Delay step represents the Delay step; if the number of the coarse tuning units is 2, the number of the fine tuning units is 3, the Delay step of the fine tuning units is 5ps, and n =2, then Code + Delay step = (2 + 3) × 5; the inherent delay can be determined based on a service scene, namely an external control code, for example, different chips correspond to different inherent delays; n is a positive integer greater than 1, and the size of n may be determined based on the performance of a device such as a chip, which is not specifically limited in this embodiment of the present application.

In one example, the delay chain control circuit with 5 bits of external control code is taken as an example, the external control code comprises a high-order control code and a low-order control code, wherein the high-order control code is 3 bits and is input of the coarse tuning thermometer code module, the low-order control code is 2 bits and is input of the fine tuning thermometer code module, and the number of the coarse tuning units can be 2 ³ =8, the delay step is delay _ coarse, the number of fine-tuning units: 2 ² And =4, the delay step is delay _ fine, and the relationship between the delay step of the coarse adjustment unit and the delay step of the fine adjustment unit is delay _ coarse =4 × delay _fine.

For example, fig. 8A is a schematic diagram of a range of delay steps corresponding to a delay chain circuit; as shown in fig. 8A, the delay chain circuit corresponds to uneven delay steps, fig. 8B is a schematic view of a range of the delay chain control circuit corresponding to the delay steps provided in the embodiment of the present application, as shown in fig. 8B, the delay chain control circuit corresponds to even delay steps, fig. 9 is a schematic view of a broken line of the delay chain control circuit corresponding to the delay steps provided in the embodiment of the present application, as shown in fig. 9, a circular point broken line corresponds to the delay steps of the delay chain circuit, and a square point broken line corresponds to the delay steps of the delay chain control circuit.

It should be noted that the smaller the inherent delay, the better the performance of the delay chain control circuit, table 1 is the inherent delays corresponding to different delay chain circuits, as shown in table 1, the first column represents different delay chain circuits, that is, the existing delay chain circuit and the delay chain control circuit provided by the present application, the second column represents the inherent delay of a chip with a fast operation rate, the third column represents the inherent delay of a chip with a medium operation rate, the fourth column represents the inherent delay of a chip with a slow operation rate, and the fifth column represents a unit.

TABLE 1

Therefore, the embodiment of the application designs that the delay step of the coarse tuning unit and the delay step of the fine tuning unit are in a multiple relation, so that the delay steps are uniform, namely, the linearity is improved.

Optionally, fig. 10 is a schematic structural diagram of a coarse tuning unit provided in an embodiment of the present application, and as shown in fig. 10, the coarse tuning unit includes: a first nand gate 1001, a second nand gate 1002, and a third nand gate 1003;

a first input terminal of the first nand gate 1001 is configured to receive an input signal, and a second input terminal of the first nand gate 1001 is configured to receive a high level signal (sel); the output end of the first nand gate 1001 is connected to the first input end of the third nand gate 1003;

the first input terminal of the second nand gate 1002 is also configured to receive an input signal, and the second input terminal of the second nand gate 1002 is configured to receive a low level signal (seln); the output end of the second nand gate 1002 is connected to the second input end of the third nand gate 1003, and the output end of the third nand gate 1003 is used for outputting the delayed input signal.

In this embodiment of the application, the first nand gate 1001 determines whether the output is a high level or a low level based on the input signal, specifically, if all the inputs to the first nand gate 1001 are high levels (1), the output is a low level (0); if at least one of the input first nand gates 1001 is at a low level (0), the output is at a high level, and it is determined whether the output input signal is at a high level or a low level based on whether the input signal is at a high level or a low level, where the high level signal (sel) received by the second input terminal of the first nand gate 1001 is a signal provided by an external circuit.

Optionally, a second input end of the first nand gate 1001 is connected to one end of a controller in the memory, and the controller is configured to access a circuit externally connected to the memory chip, that is, an external circuit.

It should be noted that the control logic of the second nand gate 1002 and the third nand gate 1003 is similar to that of the first nand gate 1001, and details are not repeated herein, the second input end of the second nand gate 1002 may be connected to an inverter, the other end of the controller in the memory is connected to the inverter, and the inverter is configured to invert the phase of the signal by 180 degrees; the second input of the second nand gate 1002 receives a low signal (seln) which is also provided to the external circuit.

Therefore, the design coarse tuning unit in the embodiment of the application is composed of the combinational logic gate, is easy to integrate, has a small area and low power consumption, and is beneficial to the alignment of bus data.

Optionally, fig. 11 is a schematic structural diagram of another coarse tuning unit provided in the embodiment of the present application, and as shown in fig. 11, the coarse tuning unit further includes: a fourth NAND gate 1004;

a first input end of the fourth nand gate 1004 is connected to an output end of the first nand gate 1001, a second input end of the fourth nand gate 1004 is connected to an output end of the second nand gate 1002, and the fourth nand gate 1004 is used for controlling output load balance of the first nand gate 1001 and the second nand gate 1002.

It can be understood that, in the embodiment of the present application, by adding the fourth nand gate 1004 to the coarse tuning unit, the output loads of the first nand gate 1001 and the second nand gate 1002 reach a balanced state, so as to improve the stability of the coarse tuning unit in performing the delay.

Fig. 12 is a schematic structural diagram of a specific delay chain control circuit according to an embodiment of the present application, and as shown in fig. 12, after the delay chain control circuit receives an input signal, the input signal is connected to an input of a fine-tuning delay module based on a coarse tuning unit, an output end of the fine-tuning delay module is connected to an input of a coarse tuning delay module, the coarse tuning delay module is composed of a plurality of cascaded coarse tuning units, and each coarse tuning unit is composed of a NAND logic gate; all the coarse tuning units are controlled by a thermometer decoding module, the thermometer decoding module controls the number of the selected coarse tuning units based on the service scene requirements, the output of the fine tuning delay module and the output of the coarse tuning delay module are simultaneously connected to a two-way selector (Mux), and the two-way selector determines whether the input signal needs to be delayed continuously or not based on the service scene requirements, namely whether a certain number of coarse tuning units in the coarse tuning delay module are selected to be delayed continuously or not so as to meet the service scene requirements; if the two-way selector determines that the input signal does not need to be delayed continuously based on the service scene requirement, the input signal is directly output; the service scenario requirement may be an external control code.

It should be noted that, modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to implement the solution of the embodiment.

In addition, functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The unit formed by the modules can be realized in a hardware form, and can also be realized in a form of hardware and a software functional unit.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. A delay chain control circuit is characterized by comprising a fine adjustment delay module, a coarse adjustment unit, a thermometer decoding module and a two-way selector; the fine adjustment delay module comprises at least one fine adjustment unit; the thermometer decoding module is used for acquiring service scene requirements and controlling the number of the selected fine-tuning units based on the service scene requirements;

the coarse adjustment unit is connected with the input end of the fine adjustment delay module, and is used for receiving an input signal and performing first time delay on the input signal;

2. The delay chain control circuit of claim 1, wherein the fine-tuning unit comprises: the N-type field effect transistor, the P-type field effect transistor, the first switch tube and the second switch tube are connected in series;

the N-type field effect transistor is connected with the first switch tube; the N-type field effect transistor is used for controlling the first switch tube to be opened when an input signal is at a high level;

3. The delay chain control circuit of claim 2, wherein the G pole of the N-type fet is connected to the input of the fine tuning unit for receiving an input signal; the S pole of the N-type field effect transistor is connected with the first switch tube, and the D pole of the N-type field effect transistor is connected with the output end of the fine adjustment unit and used for outputting an input signal;

4. The delay chain control circuit of claim 2, wherein when the input signal is at a high level, the N-fet is in an on state and the P-fet is in an off state, so that the N-fet delays the input signal;

when the input signal is at a high level, the P-type field effect transistor is in a conducting state, and the N-type field effect transistor is in a closing state, so that the P-type field effect transistor delays the input signal.

5. The delay chain control circuit of claim 3, wherein the fine-tuning unit further comprises: a first resistor and a second resistor;

6. The delay chain control circuit of claim 1, further comprising a coarse delay module, the coarse delay module comprising at least one coarse tuning unit;

and after determining that the input signal needs to be delayed continuously, the two-way selector transmits the input signal to the coarse adjusting units with corresponding number selected based on the thermometer decoding module for delaying.

7. The delay chain control circuit of claim 6, wherein the thermometer decoding module is specifically configured to:

8. The delay chain control circuit of claim 1, wherein the delay step of the coarse tuning unit is n times the delay step of the fine tuning unit; n is a positive integer greater than 1; the delay step length is used for controlling the delay of the delay chain control circuit to be regular.

9. The delay chain control circuit of any of claims 1-8, wherein the coarse tuning unit comprises: a first NAND gate, a second NAND gate and a third NAND gate;

10. The delay chain control circuit of claim 9, wherein the coarse tuning unit further comprises: a fourth NAND gate;