CN116758971B - Time sequence test circuit and chip of register file - Google Patents
Time sequence test circuit and chip of register file Download PDFInfo
- Publication number
- CN116758971B CN116758971B CN202310686313.6A CN202310686313A CN116758971B CN 116758971 B CN116758971 B CN 116758971B CN 202310686313 A CN202310686313 A CN 202310686313A CN 116758971 B CN116758971 B CN 116758971B
- Authority
- CN
- China
- Prior art keywords
- fine
- signal
- control signal
- tuning
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 119
- 238000000034 method Methods 0.000 abstract description 9
- 238000005259 measurement Methods 0.000 abstract description 5
- 230000010355 oscillation Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 7
- 230000001105 regulatory effect Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 102100031024 CCR4-NOT transcription complex subunit 1 Human genes 0.000 description 4
- 102100031025 CCR4-NOT transcription complex subunit 2 Human genes 0.000 description 4
- 102100031033 CCR4-NOT transcription complex subunit 3 Human genes 0.000 description 4
- 102100032981 CCR4-NOT transcription complex subunit 4 Human genes 0.000 description 4
- 101000919674 Caenorhabditis elegans CCR4-NOT transcription complex subunit let-711 Proteins 0.000 description 4
- 101001092183 Drosophila melanogaster Regulator of gene activity Proteins 0.000 description 4
- 101000919672 Homo sapiens CCR4-NOT transcription complex subunit 1 Proteins 0.000 description 4
- 101000919667 Homo sapiens CCR4-NOT transcription complex subunit 2 Proteins 0.000 description 4
- 101000919663 Homo sapiens CCR4-NOT transcription complex subunit 3 Proteins 0.000 description 4
- 101000942594 Homo sapiens CCR4-NOT transcription complex subunit 4 Proteins 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 101100294409 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NOT5 gene Proteins 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/842—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by introducing a delay in a signal path
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a time sequence test circuit and a chip of a register file, wherein the time sequence test circuit comprises: the enabling control module generates corresponding coarse control signals based on the test enabling signal and the coarse selection signal, and generates two groups of fine control signals based on the fine selection signal and the test enabling signal; the delay chain adjustment module generates a first delay time signal for coarse adjustment based on the test enable signal, the coarse adjustment control signal, and the first set of fine adjustment control signals, and generates a second delay time signal for fine adjustment based on the second set of fine adjustment control signals; the data acquisition module adjusts the second delay time signal by comparing the timing of the read data signal with the second delay time signal, thereby causing the data in the register file to be normally latched. The method adopts the mode of combining coarse adjustment and fine adjustment to furthest improve the precision of the time sequence test of the register file, has simple structure, simple and convenient operation and wide applicability, and the measurement precision is close to the limit of the process.
Description
Technical Field
The present invention relates to the field of chip design and application technologies, and in particular, to a timing sequence test circuit of a register file and a chip.
Background
The timing test circuit of Register file (Register file) generally uses a combination of a built-in self-test (MBIST) design of a memory and a test machine, and the test machine provides logic control, and the built-in self-test design of the memory provides test accuracy. For the mature process, the existing test method has relatively large memory data reading time and low time sequence test precision requirement. However, as the process is continuously advanced, the time sequence of the register file is smaller and smaller, the requirement of time sequence test is more and more severe, and the existing test method has difficulty in meeting the precision requirement of the time sequence test.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a timing test circuit and a chip for a register file, which are used for solving the problem that the accuracy of the timing test of the register file is difficult to be improved along with the development of the process in the prior art.
To achieve the above and other related objects, the present invention provides a timing test circuit of a register file, the timing test circuit and the register file being located in the same chip, wherein the timing test circuit and the register file share a system clock signal and a read enable signal, the timing test circuit at least comprises: the system comprises an enabling control module, a delay chain adjusting module and a data acquisition module, wherein:
the enabling control module generates a corresponding coarse tuning control signal based on an accessed test enabling signal and a coarse tuning selection signal, and generates a first group of fine tuning control signals and a second group of fine tuning control signals based on an accessed fine tuning selection signal and the test enabling signal;
the input end of the delay chain adjusting module is connected with the output end of the enabling control module, a first delay time signal for coarse adjustment is generated based on the test enabling signal, the coarse adjustment control signal and the first group of fine adjustment control signals, and a second delay time signal for fine adjustment is generated based on the second group of fine adjustment control signals;
the input end of the data acquisition module is connected with the output end of the delay chain adjusting module and the output end of the register file, and the second delay time signal is adjusted by comparing the time sequence of the read data signal and the second delay time signal, so that the data in the register file is normally latched.
Optionally, the enabling control module includes a coarse control component and a fine control component, wherein: the fine tuning control component generates a corresponding enabling control signal based on the accessed test enabling signal and the read enabling signal, and generates a fine tuning control signal based on the accessed test enabling signal and a corresponding fine tuning selection signal; the coarse control component generates a coarse control signal based on the accessed enable control signal, the system clock signal, and a corresponding coarse selection signal.
Optionally, the coarse control assembly includes M coarse delay control units, wherein M includes a positive integer greater than 1, wherein: the input end of the first coarse tuning delay control unit is connected with the enabling control signal, the system clock signal and the first coarse tuning selection signal to generate a first coarse tuning control signal; the input end of the second coarse tuning delay control unit is connected with the enabling control signal, the system clock signal and the second coarse tuning selection signal to generate a second coarse tuning control signal; similarly, the input end of the Mth coarse tuning delay control unit is connected with the enabling control signal, the system clock signal and the Mth coarse tuning selection signal to generate an Mth coarse tuning control signal.
Optionally, the coarse tuning delay control unit includes a three-input nand gate, where an input end of the three-input nand gate is connected to the enable control signal, the system clock signal and a corresponding coarse tuning selection signal, and generates a corresponding coarse tuning control signal through an output end of the three-input nand gate.
Optionally, the fine control assembly comprises: a first fine tuning nand gate, a second fine tuning nand gate, a third fine tuning nand gate, a fourth fine tuning nand gate, a fifth fine tuning nand gate, a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, and a sixth nor gate, wherein: the input end of the fifth NOT gate is connected with the test enabling signal; the input end of the fifth fine-tuning NAND gate is connected with the read enabling signal and is connected with the output end of the fifth NAND gate; the input end of the sixth NOT gate is connected with the output end of the fifth fine-tuning NAND gate, and the enabling control signal is output through the output end of the sixth NOT gate; the input end of the first fine tuning NAND gate is connected with a first fine tuning selection signal and the test enabling signal; the input end of the first NOT gate is connected with the output end of the first fine adjustment NAND gate, and a first fine adjustment control signal is generated through the output end of the first NOT gate; the input end of the second fine tuning NAND gate is connected with a second fine tuning selection signal and the test enabling signal; the input end of the second NOT gate is connected with the output end of the second fine adjustment NAND gate, and a second fine adjustment control signal is generated through the output end of the second NOT gate, wherein the first group of fine adjustment control signals comprise the first fine adjustment control signal and the second fine adjustment control signal; the input end of the third fine tuning NAND gate is connected with a third fine tuning selection signal and the test enabling signal; the input end of the third NOT gate is connected with the output end of the third fine adjustment NAND gate, and a third fine adjustment control signal is generated through the output end of the third NOT gate; the input end of the fourth fine tuning NAND gate is connected with a fourth fine tuning selection signal and the test enabling signal; the input end of the fourth NOT gate is connected with the output end of the fourth fine adjustment NAND gate, and a fourth fine adjustment control signal is generated through the output end of the fourth NOT gate, wherein the second group of fine adjustment control signals comprises the third fine adjustment control signal and the fourth fine adjustment control signal.
Optionally, the delay chain adjustment module includes a coarse delay component and a fine delay component, wherein: the coarse delay component generates the first delay time signal based on the test enable signal, a coarse control signal, a first fine control signal, and a second fine control signal that are accessed; the input end of the fine tuning delay component is connected with the output end of the coarse tuning delay component, and the fine tuning delay component generates a second delay time signal based on a third fine tuning control signal and a fourth fine tuning control signal.
Optionally, the coarse delay component includes: selector, delay NAND gate and (2N+1) delay units, wherein, (2N+1) > M, N is a positive integer greater than 1, wherein: a first input end of the delay NAND gate is accessed to a test enabling signal; the input end of the selector is connected with the test enabling signal and the first signal and is connected with the output end of the delay NAND gate; the input end of the first-stage delay unit is connected with a first coarse adjustment control signal, a first fine adjustment control signal and a second fine adjustment control signal and is connected with the output end of the selector; the input end of the second-stage delay unit is connected with a second coarse adjustment control signal, a first fine adjustment control signal and a second fine adjustment control signal and is connected with the output end of the first-stage delay unit; and so on, the input end of the M-th stage delay unit is connected with the M-th coarse adjustment control signal, the first fine adjustment control signal and the second fine adjustment control signal, and is connected with the output end of the (M-1) -th stage delay unit; the input end of the (M+1) th stage delay unit is connected with the first signal, the first fine adjustment control signal and the second fine adjustment control signal and is connected with the output end of the M th stage delay unit; the input end of the (M+2) th stage delay unit is connected with the first signal, the first fine adjustment control signal and the second fine adjustment control signal, and is connected with the output end of the (M+1) th stage delay unit; and so on, the input end of the 2N-stage delay unit is connected with the first signal, the first fine adjustment control signal and the second fine adjustment control signal and is connected with the output end of the (2N-1) -stage delay unit, wherein the output end of the 2N-stage delay unit is connected with the second input end of the delay NAND gate; the first delay time signal is generated through the output end of the K-th stage delay unit, wherein M is more than or equal to K and less than or equal to 2N, and K is a positive integer greater than 1; the input end of the (2N+1) th stage delay unit is connected with the output end of the K stage delay unit, and the next stage component is controlled by accessing the read enable signal, the first delay time signal, the first fine adjustment control signal and the second fine adjustment control signal.
Optionally, the delay unit includes: the input end of the first fine adjustment subunit is connected with the output end of the two-input NAND gate, and is adjusted by accessing a first fine adjustment control signal and a second fine adjustment control signal.
Optionally, the fine tuning delay component includes a second fine tuning subunit, where an input end of the second fine tuning subunit is connected to an output end of the coarse tuning delay component, and the second fine tuning subunit generates a second delay time signal by accessing a third fine tuning control signal and a fourth fine tuning control signal.
Optionally, the first fine tuning subunit and the second fine tuning subunit each comprise: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the seventh NOT gate, the eighth NOT gate and the ninth NOT gate, wherein: the drain electrode of the first PMOS tube is connected with the output end of the seventh NOT gate; the input end of the eighth NOT gate is connected with the source electrode of the first PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube; the drain electrode of the second PMOS tube is connected with the output end of the seventh NOT gate; the input end of the ninth NOT gate is connected with the source electrode of the second PMOS tube; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second NMOS tube is connected with the source electrode of the second PMOS tube, wherein the grid electrode of the first PMOS tube in the first fine-tuning subunit is connected with a first fine-tuning control signal, the polarity of the signal connected with the grid electrode of the first NMOS tube in the first fine-tuning subunit is opposite to that of the first fine-tuning control signal, the grid electrode of the second PMOS tube in the first fine-tuning subunit is connected with a second fine-tuning control signal, and the polarity of the signal connected with the grid electrode of the second NMOS tube in the first fine-tuning subunit is opposite to that of the second fine-tuning control signal; the grid electrode of the first PMOS tube in the second fine-tuning subunit is connected with a third fine-tuning control signal, the polarity of the signal connected with the grid electrode of the first NMOS tube in the second fine-tuning subunit is opposite to that of the third fine-tuning control signal, the grid electrode of the second PMOS tube in the second fine-tuning subunit is connected with a fourth fine-tuning control signal, and the polarity of the signal connected with the grid electrode of the second NMOS tube in the second fine-tuning subunit is opposite to that of the fourth fine-tuning control signal.
To achieve the above and other related objects, the present invention provides a chip including the timing test circuit.
As described above, the time sequence test circuit and the chip of the register file have the following beneficial effects:
the time sequence test circuit and the chip of the register file of the invention adopt a mode of combining coarse adjustment and fine adjustment to furthest improve the precision of the time sequence test of the register file, have simple structure and convenient operation, and have wide applicability, and the measurement precision is close to the limit of the process.
Drawings
FIG. 1 is a schematic diagram of a timing test circuit of a register file according to the present invention.
Fig. 2 is a schematic diagram of an internal circuit of the timing test circuit according to the present invention.
FIG. 3 is a schematic diagram of the internal circuit of the delay unit of the present invention
Fig. 4 shows an internal circuit schematic of the second fine-tuning subunit of the present invention.
FIG. 5 is a timing diagram of a memory timing test mode according to the present invention.
FIG. 6 is a timing diagram of the delay chain self-test mode according to the present invention.
Description of the reference numerals
1. Time sequence test circuit
11. Enabling control module
111. Coarse control assembly
112. Fine tuning control assembly
12. Delay chain adjustment module
121. Coarse delay assembly
1211. Delay NAND gate
1212. Delay unit
1212a first fine-tuning subunit
122. Fine-tuning delay assembly
1221. Second fine tuning subunit
13. Data acquisition module
2. Register file
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1 and 2, the present embodiment provides a timing test circuit 1 of a register file, the timing test circuit 1 and the register file 2 are located in the same chip, wherein the timing test circuit 2 and the register file 2 share a system clock signal CLK and a read enable signal rd_en, and the timing test circuit 1 includes: an enabling control module 11, a delay chain adjusting module 12 and a data acquisition module 13, wherein:
as shown in fig. 2, the enabling control module 11 generates a corresponding coarse control signal out < M:1> based on the accessed test enable signal test_en and the coarse selection signal ctrl_option < M:1>, wherein M comprises a positive integer greater than 1; the first and second sets of fine control signals are generated based on the accessed fine selection signals ctrl_sel <4:1> and the test enable signal test_en.
Specifically, as an example, as shown in fig. 2, the enabling control module 11 includes a coarse control component 111 and a fine control component 112, wherein: the fine control component 112 generates a corresponding enable control signal EN based on the accessed test enable signal test_en and the read enable signal rd_en, and the fine control component 112 generates a fine control signal based on the accessed test enable signal test_en and the corresponding fine selection signal ctrl_sel <4:1 >; the coarse control component 111 generates a coarse control signal out < M:1> based on the accessed enable control signal EN, the system clock signal CLK, and the corresponding coarse selection signal ctrl_option < M:1>.
More specifically, the coarse control component 111 includes M coarse delay control units (coarse delay control units are not shown in FIG. 2), where M includes a positive integer greater than 1, where: the input end of the first coarse delay control unit is connected with an enable control signal EN, a system clock signal CLK and a first coarse selection signal ctrl_option <1>, and generates a first coarse control signal out <1>; the input end of the second coarse delay control unit is connected with an enable control signal EN, a system clock signal CLK and a second coarse selection signal ctrl_option <2>, and generates a second coarse control signal out <2>; similarly, the input terminal of the Mth coarse delay control unit is connected to the enable control signal EN, the system clock signal CLK and the Mth coarse selection signal ctrl_option < M >, so as to generate an Mth coarse control signal out < M >. Further, the coarse delay control unit comprises a three-input NAND gate, wherein the input end of the three-input NAND gate is connected with an enable control signal EN, a system clock signal CLK and a corresponding coarse selection signal, and the output end of the three-input NAND gate generates a corresponding coarse selection signal ctrl_option < M:1>.
More specifically, the fine control assembly 112 includes: a first fine tuning NAND gate nand_1, a second fine tuning NAND gate nand_2, a third fine tuning NAND gate nand_3, a fourth fine tuning NAND gate nand_4, a fifth fine tuning NAND gate nand_5, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, a fifth NOT gate NOT5, and a sixth NOT gate NOT6, wherein: the input end of the fifth NOT gate NOT5 is connected with a test enabling signal test_en; the input end of the fifth fine-tuning NAND gate NAND_5 is connected with a read enable signal rd_en and is connected with the output end of the fifth fine-tuning NAND gate NAND_5; the input end of the sixth NOT6 is connected with the output end of the fifth fine-tuning NAND gate NAND_5, and an enable control signal EN is output through the output end of the sixth NOT 6; the input end of the first fine NAND gate NAND_1 is connected with a first fine selection signal ctrl_sel <1> and a test enabling signal test_en; the input end of the first NOT1 is connected with the output end of the first fine-tuning NAND gate NAND_1, and a first fine-tuning control signal sel_a is generated through the output end of the first NOT gate NOT1, wherein the input end of the first NOT gate NOT1 is connected with a signal sel_ab; the input end of the second fine NAND gate NAND_2 is connected with a second fine selection signal ctrl_sel <2> and a test enabling signal test_en; the input end of the second NOT2 is connected with the output end of the second fine tuning NAND gate NAND_2, and a second fine tuning control signal sel_b is generated through the output end of the second NOT2, wherein the input end of the second NOT2 is connected with a signal sel_bb, and the first group of fine tuning control signals comprise a first fine tuning control signal sel_a and a second fine tuning control signal sel_b; the input end of the third fine NAND gate NAND_3 is connected with a third fine selection signal ctrl_sel <3> and a test enabling signal test_en; the input end of the third NOT3 is connected with the output end of the third fine-tuning NAND gate NAND_3, and a third fine-tuning control signal sel_c is generated through the output end of the third NOT3, wherein the input end of the third NOT3 is connected with a signal sel_cb; the input end of the fourth fine NAND gate NAND_4 is connected with a fourth fine selection signal ctrl_sel <4> and a test enabling signal test_en; the input end of the fourth NOT4 is connected with the output end of the fourth fine tuning NAND gate NAND_4, and a fourth fine tuning control signal sel_d is generated through the output end of the fourth NOT4, wherein the input end of the fourth NOT4 is connected with a signal sel_db, and the second group of fine tuning control signals comprise a third fine tuning control signal sel_c and a fourth fine tuning control signal sel_d.
As shown in fig. 2, the input of the delay chain adjusting module 12 is connected to the output of the enable control module 11, and generates a first delay time signal ring_clk for coarse adjustment based on the test enable signal test_en and the coarse adjustment control signal out < M:1> and a first set of fine adjustment control signals (including a first fine adjustment control signal sel_a and a second fine adjustment control signal sel_b), and generates a second delay time signal ck_lat for fine adjustment based on a second set of fine adjustment control signals (including a third fine adjustment control signal sel_c and a fourth fine adjustment control signal sel_d).
Specifically, as an example, as shown in fig. 2, the delay chain adjustment module 12 includes a coarse delay component 121 and a fine delay component 122, wherein: the coarse delay component 121 generates a first delay time signal ring_clk based on the accessed test enable signal test_en and the coarse control signal out < M:1>, the first fine control signal sel_a and the second fine control signal sel_b; an input terminal of the fine delay element 122 is connected to an output terminal of the coarse delay element 121, and the fine delay element 122 generates a second delay time signal ck_lat based on the third fine control signal sel_c and the fourth fine control signal sel_d.
More specifically, the coarse delay component 121 includes: selector, delay NAND gate 1211, and (2N+1) delay cells 1212, where (2N+1) > M, N is a positive integer greater than 1, where: a first input of the delay nand gate 1211 is connected to a test enable signal test_en; the input terminal of the selector is connected to the test enable signal test_en and the first signal TIEH, and is connected to the output terminal of the delay nand gate 1211, it should be noted that the selector and the delay nand gate 1211 may be equivalent to a delay unit, different from the (2n+1) delay units in the coarse delay component 121, the selector is regulated by the test enable signal test_en, and when the test enable signal test_en is effective, the delay unit obtained by the selector and the delay nand gate 1211 by equivalent can be effective. The input end of the first stage delay unit is connected with a first coarse adjustment control signal out <1>, a first fine adjustment control signal sel_a and a second fine adjustment control signal sel_b, and is connected with the output end of the selector; the input end of the second-stage delay unit is connected with a second coarse adjustment control signal out <2>, a first fine adjustment control signal sel_a and a second fine adjustment control signal sel_b, and is connected with the output end of the first-stage delay unit; and so on, the input end of the Mth-stage delay unit is connected with the Mth coarse control signal out < M >, the first fine control signal sel_a and the second fine control signal sel_b, and is connected with the output end of the (M-1) -th-stage delay unit, namely, the first-stage delay unit to the Mth-stage delay unit are in one-to-one correspondence with the coarse control signal out < M:1 >; the input end of the (M+1) th stage delay unit is connected with the first signal TIEH, the first fine adjustment control signal sel_a and the second fine adjustment control signal sel_b and is connected with the output end of the M th stage delay unit; the input end of the (M+2) th stage delay unit is connected with the first signal TIEH, the first fine adjustment control signal sel_a and the second fine adjustment control signal sel_b, and is connected with the output end of the (M+1) th stage delay unit; and so on, the input end of the 2N-stage delay unit is connected to the first signal TIEH, the first fine adjustment control signal sel_a and the second fine adjustment control signal sel_b and is connected with the output end of the (2N-1) -stage delay unit, wherein the output end of the 2N-stage delay unit is connected with the second input end of the delay NAND gate 1211; the method comprises the steps of generating a first delay time signal ring_clk through an output end of a K-th stage delay unit, wherein M is more than K and less than or equal to 2N, and K is a positive integer greater than 1. Wherein the first stage delay unit, the second stage delay unit, & gt2N stage delay unit, the selector and the delay NAND gate 1211 form a ring oscillation part (the selector and the delay NAND gate are equivalent to one delay unit), the ring oscillation section includes (2n+1) delay units, and the oscillation period of the ring oscillation section is defined by a test enable signal test_en and a coarse control signal out < M:1> and a first signal TIEH. The number of delay units in effect of the ring oscillator is determined by setting the test enable signal test_en, the coarse control signal out < M:1> and the first signal TIEH, thereby determining the period of the first delay time signal ring_clk, wherein the (2N+1) th stage of delay units is not in the ring oscillator. The input end of the (2N+1) th stage delay unit is connected with the output end of the K stage delay unit, and the next stage component is controlled by accessing the read enable signal rd_en, the first delay time signal ring_clk, the first fine adjustment control signal sel_a and the second fine adjustment control signal sel_b. It should be noted that the first signal TIEH represents a stable high level, and the coarse tuning selection signal ctrl_option < M:1> is used to adjust the number of delay units that are connected, thereby implementing the coarse tuning function. When the first coarse tuning control signal out <1> is effective, the first-stage delay unit, the second-stage delay unit, & gtand the M-th-stage delay unit are effective, and then a first delay time signal ring_clk is generated through the output end of the K-th-stage delay unit, wherein M is less than K and less than or equal to 2N (the supplementary explanation is needed, the first delay time signal ring_clk is generated for the output end of the corresponding delay unit according to the actual requirement setting); when the first coarse control signal out <1> is not validated and the second coarse control signal out <2> is validated, the second-stage delay unit, the third-stage delay unit, & gtand the Mth-stage delay unit are validated, and then a first delay time signal ring_clk is generated through the output end of the Kth-stage delay unit, and a coarse selection signal ctrl_option < M is set according to actual requirements: 1>.
Further, when the test enable signal test_en is at a high level, the coarse tuning delay component 121 is asserted, at this time, the enable control signal EN is pulled low, the coarse tuning control component 111 is turned off, the timing test circuit 1 enters a delay chain self-test mode, and the period of the first delay time signal ring_clk is equal to the oscillation period of the ring oscillation section. Specifically, since the selector and the delay nand gate 1211 may be equivalently a delay unit, which is equivalent to the ring oscillation portion including (2n+1) delay units, after each delay unit in effect generates a delay operation, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 are controlled to be further delayed by adjusting the levels of the first fine control signal sel_a and the second fine control signal sel_b, so as to adjust the period of the first delay time signal ring_clk, where the period of the first delay time signal ring_clk is equal to the sum of delay times generated by the delay units in effect, and it can be seen that the delay times generated by the delay units in effect are equal. In the delay chain self-test mode, the levels of the first fine control signal sel_a and the first fine control signal sel_b include: each of the four cases (0, 0), (0, 1), (1, 0) and (1, 1) further adjusts each delay unit 1212 to obtain delay times of four delay units with different loads, wherein the four delay times are TD1, TD2, TD3 and TD4 respectively, and when (sel_a, sel_b) is (0, 0), the delay time is TD1; when (sel_a, sel_b) is (0, 1), the delay time is TD2; when (sel_a, sel_b) is (1, 0), the delay time is TD3; when (sel_a, sel_b) is (1, 1), the delay time is TD4; wherein, TD1 is the shortest; TD4 is longest. It should be further noted that the delay generated by the coarse delay component 121 includes: the delay generated by the delay units from the first stage to the K stage in the ring oscillation part and the delay generated by the delay unit from the (2N+1) th stage in effect; and whether the (2n+1) th stage delay unit is effective is controlled by the read enable signal rd_en, and the (2n+1) th stage delay unit is also regulated by the first fine regulating control signal sel_a and the second fine regulating control signal sel_b, so that when the (2n+1) th stage delay unit is effective, the delay generated by the (2n+1) th stage delay unit is equal to the delay generated by a single delay unit in the ring oscillation.
Further, in order to facilitate calculation of the delay parameter of the second delay time signal ck_lat, when the coarse control component 111 is turned on, the three-input nand gate corresponding to the coarse control signal out < M:1> that is in effect is equivalent to the fine delay component 122 as a delay unit, and is set as an equivalent delay unit. In design, the parameters of the three-input nand gate and the parameters of the two-input nand gate in the delay unit 1212 may be set to be approximately equal, so that the delay of the equivalent delay unit corresponds to the delay generated by the delay unit 1212 in the coarse delay assembly 121 one by one. Specifically, the second fine tuning subunit 1221 in the fine tuning delay assembly 122 is tuned by a third fine tuning control signal sel_c and a fourth fine tuning control signal sel_d, and the levels of the third fine tuning control signal sel_c and the fourth fine tuning control signal sel_d include: four cases (0, 0), (0, 1), (1, 0) and (1, 1), when (sel_c, sel_d) is (0, 0), the delay generated by the equivalent delay unit is equal to TD1; when (sel_c, sel_d) is (0, 1), the delay generated by the equivalent delay unit is equal to TD2; when (sel_c, sel_d) is (1, 0), the delay generated by the equivalent delay unit is equal to TD3; when (sel_c, sel_d) is (1, 1), the delay produced by the equivalent delay unit is equal to TD4.
When the test enable signal test_en is low, the timing test circuit 1 enters a memory timing test mode, the ring oscillation part in the coarse delay component 121 is interrupted, the period of the first delay time signal ring_clk is regulated only by the coarse selection signal ctrl_option < M:1> and the system clock signal CLK, and the coarse selection signal ctrl_option < M:1> can be used to adjust the number of delay units accessed, and the first delay time signal ring_clk is adjusted by the active delay units and the system clock signal CLK. By setting (sel_a, sel_b) to (0, 0) in the delay chain self-test mode, the delay time of the delay unit 1212 in the coarse delay component 121 is TD1. While in the memory timing test mode, (sel_c, sel_d) is set to (0, 0) first, the number of delay units 1212 connected to the coarse delay unit 121 is adjusted by setting the coarse selection signal ctrl_option < M:1>, as an example, if the first coarse control signal out <1> is asserted, the data in the register file 2 is normally latched, and the second coarse control signal out <2> is asserted, the data in the register file 2 is not latched, the second coarse control signal out <2> is maintained asserted, and the adjustment (sel_c, sel_d) is performed until the data in the register file 2 is normally latched, and the adjustment sequence of (sel_c, sel_d) is performed from (0, 0) to (1, 1), thereby improving the accuracy of the data latching.
More specifically, as shown in fig. 2 and 3, the delay unit 1212 includes: the input end of the first fine tuning subunit 1212a is connected to the output end of the two-input nand gate, and the first fine tuning control signal sel_a and the second fine tuning control signal sel_b are connected to the two-input nand gate for tuning.
More specifically, as shown in fig. 2 and 3, the fine tuning delay element 122 includes a second fine tuning subunit 1221, wherein an input terminal of the second fine tuning subunit 1221 is connected to an output terminal of the coarse tuning delay element 121, and the second fine tuning subunit 1221 generates the second delay time signal ck_lat by accessing the third fine tuning control signal sel_c and the fourth fine tuning control signal sel_d.
Further, as shown in fig. 3 and 4, the first fine tuning subunit 1212a and the second fine tuning subunit 1221 each include: the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the second NMOS transistor N2, the seventh NOT gate NOT7, the eighth NOT gate NOT8, and the ninth NOT gate NOT9, wherein: the drain electrode of the first PMOS tube P1 is connected with the output end of the seventh NOT gate NOT 7; the input end of the eighth NOT gate NOT8 is connected with the source electrode of the first PMOS tube P1; the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1, and the source electrode of the first NMOS tube N1 is connected with the source electrode of the first PMOS tube P1; the drain electrode of the second PMOS tube P2 is connected with the output end of the seventh NOT gate NOT 7; the input end of the ninth NOT gate NOT9 is connected with the source electrode of the second PMOS tube P2; the drain electrode of the second NMOS transistor N2 is connected to the drain electrode of the second PMOS transistor P2, the source electrode of the second NMOS transistor N2 is connected to the source electrode of the second PMOS transistor P2, wherein the gate electrode of the first PMOS transistor P1 in the first fine tuning subunit 1212a is connected to the first fine tuning control signal sel_a, the polarity of the signal connected to the gate electrode of the first NMOS transistor N1 in the first fine tuning subunit 1212a is opposite to the polarity of the first fine tuning control signal sel_a (i.e., the gate electrode of the first NMOS transistor N1 is connected to the signal sel_ab), the gate electrode of the second PMOS transistor P2 in the first fine tuning subunit 1212a is connected to the second fine tuning control signal sel_b, and the polarity of the signal connected to the gate electrode of the second NMOS transistor N2 in the first fine tuning subunit 1212a is opposite to the polarity of the second fine tuning control signal sel_b (i.e., the gate electrode of the second NMOS transistor N2 is connected to the signal sel_bb); the gate of the first PMOS transistor P1 in the second fine tuning subunit 1221 is connected to the third fine tuning control signal sel_c, the polarity of the signal connected to the gate of the first NMOS transistor N1 in the second fine tuning subunit 1221 is opposite to the polarity of the third fine tuning control signal sel_c (i.e., the gate connection signal sel_cb of the first NMOS transistor N1), the gate of the second PMOS transistor P2 in the second fine tuning subunit 1221 is connected to the fourth fine tuning control signal sel_d, and the polarity of the signal connected to the gate of the second NMOS transistor N2 in the second fine tuning subunit 1221 is opposite to the polarity of the fourth fine tuning control signal sel_d (i.e., the gate connection signal sel_db of the second NMOS transistor N2).
It should be noted that, as shown in fig. 3 and fig. 4, when the fine tuning control signals (including the first fine tuning control signal sel_a, the second fine tuning control signal sel_b, the third fine tuning control signal sel_c and the fourth fine tuning control signal sel_d) are asserted, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2 are all turned on, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2 form a MOS transistor capacitor, and further the delay function is performed, because the delay chain of the first fine tuning subunit 1212a and the second fine tuning subunit 1221 is formed by only the second input nand gate and the first inverter (NOT gate NOT 7), and the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2 are only controlled by the fine tuning control signals, so that the load delay is small, and the second fine tuning subunit 1221 can be further delayed by the delay signal to generate the first fine tuning signal at the fine delay time delay clock_delay stage_delay signal.
As shown in fig. 2, the input end of the data acquisition module 13 is connected to the output end of the delay chain adjusting module 12 and the output end of the register file 2, and the second delay time signal ck_lat is adjusted by comparing the timing of the read data signal rd_data and the second delay time signal ck_lat, so that the data in the register file is normally latched, wherein the signal out_lat is output through the data acquisition module 13.
As shown in fig. 5, when the timing test circuit works in the memory timing test mode, the system clock signal CLK regulates and controls, tcq is represented as memory read time, tdelay is represented as delay time generated by the second delay time signal ck_lat, and when the register file reads data, the system clock signal CLK is delayed by the second delay time signal ck_lat, and the timing of the second delay time signal ck_lat needs to be later than the timing of the read data signal rd_data, i.e., tdelay > Tcq data can be normally latched.
As an example, as shown in fig. 6, when the coarse delay component 121 operates in the delay chain self-test mode (the test enable signal test_en is high, the enable control signal EN is low, the coarse control component 111 is turned off), the levels of the first fine control signal sel_a and the second fine control signal sel_b include four cases (0, 0), (0, 1), (1, 0) and (1, 1), and the oscillation period generated by the ring oscillation section is Tx, and the delay of each delay unit is equal to Tx/(2n+1), where (sel_a, sel_b) is (0, 0), tx/(2n+1) =td1; when (sel_a, sel_b) is (0, 1), tx/(2n+1) =td2; when (sel_a, sel_b) is (1, 0), tx/(2n+1) =td3; when (sel_a, sel_b) is (1, 1), tx/(2n+1) =td4, and thus the appropriate (sel_a, sel_b) is selected to obtain Tx.
Further, the coarse delay unit 121 is operated in the memory timing test mode (the enable signal test_en is set to a low level, the ring oscillation section is turned off, the level of the enable control signal EN is determined by the read enable signal rd_en, the number of active delay units among the first to mth delay units is determined by the enable control signal EN, the coarse selection signal ctrl_option < M:1> and the system clock signal CLK), and assuming that there are L delay units related to the delay time generated by the coarse delay unit 121, L includes: the number of delay units effective in the first to M-th delay units, the (m+1) -th to K-th delay units, and the (2n+1) -th delay unit, and the delay time of each delay unit is Tx/(2n+1), the delay time generated by the coarse tuning delay component 121 is equal to (Tx/(2n+1)). Since the three-input NAND gate corresponding to the fine tuning delay element and the coarse tuning control signal out < M:1> is equivalent to a delay unit, and the delay time generated by the equivalent delay unit is Ty, ty is regulated by the third fine tuning control signal sel_c and the fourth fine tuning control signal sel_d, the levels of the third fine tuning control signal sel_c and the fourth fine tuning control signal sel_d include: four cases (0, 0), (0, 1), (1, 0) and (1, 1), thus four Ty can be obtained, where Ty is equal to TD1 when (sel_c, sel_d) is (0, 0); when (sel_c, sel_d) is (0, 1), ty is equal to TD2; when (sel_c, sel_d) is (1, 0), ty is equal to TD3; when (sel_c, sel_d) is (1, 1), ty is equal to TD4. The appropriate Ty should be selected according to the use scenario, and specific operations will not be described here in detail. Further, tdelay= (Tx/(2n+1)). L+ty is obtained, and if the second delay time signal ck_lat needs to be adjusted, the corresponding adjustment is performed on L and Ty, so that the data in the register file is normally latched.
It should be noted that, an ASIC (Application Specific Integrated Circuit, i.e., an application specific integrated circuit, is a special application chip designed and manufactured for a specific user requirement and a specific electronic system, and its computing power and computing efficiency may be customized according to an algorithm requirement) may be used to set the enable control module 11, the delay chain adjustment module 12 and the data acquisition module 13, or an IP core (IP core, collectively referred to as an intellectual property core, and english collectively referred to as intellectual property core) may be used, which is a reusable module provided by a certain party and designed in the form of a logic unit and a chip, in the reusable design methodology of the integrated circuit.
The embodiment also provides a chip, which comprises the time sequence testing circuit and is used for improving the time sequence measurement precision of the read data signals of the register file.
In summary, the timing test circuit and the chip of the register file according to the present invention are used for improving the timing measurement precision of the read data signal of the register file, the timing test circuit and the register file are located in the same chip, wherein the timing test circuit and the register file share the system clock signal and the read enable signal, and the timing test circuit is characterized in that the timing test circuit at least comprises: the system comprises an enabling control module, a delay chain adjusting module and a data acquisition module, wherein: the enabling control module generates corresponding coarse adjustment control signals based on the accessed test enabling signals and coarse adjustment selection signals, and generates two groups of fine adjustment control signals based on the accessed fine adjustment selection signals and the test enabling signals; the input end of the delay chain adjusting module is connected with the output end of the enabling control module, a first delay time signal for coarse adjustment is generated based on the test enabling signal, the coarse adjustment control signal and the first group of fine adjustment control signals, and a second delay time signal for fine adjustment is generated based on the second group of fine adjustment control signals; the input end of the data acquisition module is connected with the output end of the delay chain adjusting module and the output end of the register file, and the second delay time signal is adjusted by comparing the time sequence of the read data signal and the second delay time signal, so that the data in the register file is normally latched. The time sequence test circuit and the chip of the register file of the invention adopt a mode of combining coarse adjustment and fine adjustment to furthest improve the precision of the time sequence test of the register file, have simple structure and convenient operation, and have wide applicability, and the measurement precision is close to the limit of the process. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. A timing test circuit of a register file, the timing test circuit and the register file being located within the same chip, wherein the timing test circuit and the register file share a system clock signal and a read enable signal, the timing test circuit comprising at least: the system comprises an enabling control module, a delay chain adjusting module and a data acquisition module, wherein:
the enabling control module generates a corresponding coarse tuning control signal based on an accessed test enabling signal and a coarse tuning selection signal, and generates a first group of fine tuning control signals and a second group of fine tuning control signals based on an accessed fine tuning selection signal and the test enabling signal;
the input end of the delay chain adjusting module is connected with the output end of the enabling control module, a first delay time signal for coarse adjustment is generated based on the test enabling signal, the coarse adjustment control signal and the first group of fine adjustment control signals, and a second delay time signal for fine adjustment is generated based on the second group of fine adjustment control signals;
The input end of the data acquisition module is connected with the output end of the delay chain adjusting module and the output end of the register file, and the second delay time signal is adjusted by comparing the time sequence of the read data signal and the second delay time signal, so that the data in the register file is normally latched.
2. The timing testing circuit of claim 1, wherein: the enabling control module comprises a coarse control component and a fine control component, wherein: the fine tuning control component generates a corresponding enabling control signal based on the accessed test enabling signal and the read enabling signal, and generates a fine tuning control signal based on the accessed test enabling signal and a corresponding fine tuning selection signal; the coarse control component generates a coarse control signal based on the accessed enable control signal, the system clock signal, and a corresponding coarse selection signal.
3. The timing testing circuit of claim 2, wherein: the coarse control assembly includes M coarse delay control units, where M includes a positive integer greater than 1, where: the input end of the first coarse tuning delay control unit is connected with the enabling control signal, the system clock signal and the first coarse tuning selection signal to generate a first coarse tuning control signal; the input end of the second coarse tuning delay control unit is connected with the enabling control signal, the system clock signal and the second coarse tuning selection signal to generate a second coarse tuning control signal; similarly, the input end of the Mth coarse tuning delay control unit is connected with the enabling control signal, the system clock signal and the Mth coarse tuning selection signal to generate an Mth coarse tuning control signal.
4. A timing testing circuit according to claim 3, wherein: the coarse-adjustment delay control unit comprises a three-input NAND gate, wherein the input end of the three-input NAND gate is connected with the enabling control signal, the system clock signal and the corresponding coarse-adjustment selection signal, and the corresponding coarse-adjustment control signal is generated through the output end of the three-input NAND gate.
5. The timing testing circuit of claim 4, wherein: the fine control assembly includes: a first fine tuning nand gate, a second fine tuning nand gate, a third fine tuning nand gate, a fourth fine tuning nand gate, a fifth fine tuning nand gate, a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, and a sixth nor gate, wherein: the input end of the fifth NOT gate is connected with the test enabling signal; the input end of the fifth fine-tuning NAND gate is connected with the read enabling signal and is connected with the output end of the fifth NAND gate; the input end of the sixth NOT gate is connected with the output end of the fifth fine-tuning NAND gate, and the enabling control signal is output through the output end of the sixth NOT gate; the input end of the first fine tuning NAND gate is connected with a first fine tuning selection signal and the test enabling signal; the input end of the first NOT gate is connected with the output end of the first fine adjustment NAND gate, and a first fine adjustment control signal is generated through the output end of the first NOT gate; the input end of the second fine tuning NAND gate is connected with a second fine tuning selection signal and the test enabling signal; the input end of the second NOT gate is connected with the output end of the second fine adjustment NAND gate, and a second fine adjustment control signal is generated through the output end of the second NOT gate, wherein the first group of fine adjustment control signals comprise the first fine adjustment control signal and the second fine adjustment control signal; the input end of the third fine tuning NAND gate is connected with a third fine tuning selection signal and the test enabling signal; the input end of the third NOT gate is connected with the output end of the third fine adjustment NAND gate, and a third fine adjustment control signal is generated through the output end of the third NOT gate; the input end of the fourth fine tuning NAND gate is connected with a fourth fine tuning selection signal and the test enabling signal; the input end of the fourth NOT gate is connected with the output end of the fourth fine adjustment NAND gate, and a fourth fine adjustment control signal is generated through the output end of the fourth NOT gate, wherein the second group of fine adjustment control signals comprises the third fine adjustment control signal and the fourth fine adjustment control signal.
6. The timing testing circuit of claim 5, wherein: the delay chain adjustment module includes a coarse delay component and a fine delay component, wherein: the coarse delay component generates the first delay time signal based on the test enable signal, a coarse control signal, a first fine control signal, and a second fine control signal that are accessed; the input end of the fine tuning delay component is connected with the output end of the coarse tuning delay component, and the fine tuning delay component generates a second delay time signal based on a third fine tuning control signal and a fourth fine tuning control signal.
7. The timing testing circuit of claim 6, wherein: the coarse delay component includes: selector, delay NAND gate and 2N+1 delay units, wherein 2N+1 > M, N is a positive integer greater than 1, wherein: a first input end of the delay NAND gate is accessed to a test enabling signal; the input end of the selector is connected with the test enabling signal and the first signal and is connected with the output end of the delay NAND gate; the input end of the first-stage delay unit is connected with a first coarse adjustment control signal, a first fine adjustment control signal and a second fine adjustment control signal and is connected with the output end of the selector; the input end of the second-stage delay unit is connected with a second coarse adjustment control signal, a first fine adjustment control signal and a second fine adjustment control signal and is connected with the output end of the first-stage delay unit; and the input end of the Mth-level delay unit is connected with the Mth coarse adjustment control signal, the first fine adjustment control signal and the second fine adjustment control signal, and is connected with the output end of the M-1 th-level delay unit; the input end of the M+1th stage delay unit is connected with the first signal, the first fine adjustment control signal and the second fine adjustment control signal and is connected with the output end of the M stage delay unit; the input end of the M+2-stage delay unit is connected with the first signal, the first fine adjustment control signal and the second fine adjustment control signal and is connected with the output end of the M+1-stage delay unit; and so on, the input end of the 2N-stage delay unit is connected with a first signal, a first fine adjustment control signal and a second fine adjustment control signal, and is connected with the output end of the 2N-1-stage delay unit, wherein the output end of the 2N-stage delay unit is connected with the second input end of the delay NAND gate; the first delay time signal is generated through the output end of the K-th stage delay unit, wherein M is more than or equal to K and less than or equal to 2N, and K is a positive integer greater than 1; the input end of the 2N+1-th stage delay unit is connected with the output end of the K-th stage delay unit, and the next stage component is controlled by accessing the read enabling signal, the first delay time signal, the first fine adjustment control signal and the second fine adjustment control signal.
8. The timing testing circuit of claim 7, wherein: the delay unit includes: the input end of the first fine adjustment subunit is connected with the output end of the two-input NAND gate, and is adjusted by accessing a first fine adjustment control signal and a second fine adjustment control signal.
9. The timing testing circuit of claim 8, wherein: the fine tuning delay assembly comprises a second fine tuning subunit, wherein the input end of the second fine tuning subunit is connected with the output end of the coarse tuning delay assembly, and the second fine tuning subunit generates a second delay time signal by accessing a third fine tuning control signal and a fourth fine tuning control signal.
10. The timing testing circuit of claim 9, wherein: the first fine tuning subunit and the second fine tuning subunit each comprise: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the seventh NOT gate, the eighth NOT gate and the ninth NOT gate, wherein: the drain electrode of the first PMOS tube is connected with the output end of the seventh NOT gate; the input end of the eighth NOT gate is connected with the source electrode of the first PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube; the drain electrode of the second PMOS tube is connected with the output end of the seventh NOT gate; the input end of the ninth NOT gate is connected with the source electrode of the second PMOS tube; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second NMOS tube is connected with the source electrode of the second PMOS tube, wherein the grid electrode of the first PMOS tube in the first fine-tuning subunit is connected with a first fine-tuning control signal, the polarity of the signal connected with the grid electrode of the first NMOS tube in the first fine-tuning subunit is opposite to that of the first fine-tuning control signal, the grid electrode of the second PMOS tube in the first fine-tuning subunit is connected with a second fine-tuning control signal, and the polarity of the signal connected with the grid electrode of the second NMOS tube in the first fine-tuning subunit is opposite to that of the second fine-tuning control signal; the grid electrode of the first PMOS tube in the second fine-tuning subunit is connected with a third fine-tuning control signal, the polarity of the signal connected with the grid electrode of the first NMOS tube in the second fine-tuning subunit is opposite to that of the third fine-tuning control signal, the grid electrode of the second PMOS tube in the second fine-tuning subunit is connected with a fourth fine-tuning control signal, and the polarity of the signal connected with the grid electrode of the second NMOS tube in the second fine-tuning subunit is opposite to that of the fourth fine-tuning control signal.
11. A chip, characterized in that: the chip comprising a timing test circuit according to any of claims 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310686313.6A CN116758971B (en) | 2023-06-09 | 2023-06-09 | Time sequence test circuit and chip of register file |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310686313.6A CN116758971B (en) | 2023-06-09 | 2023-06-09 | Time sequence test circuit and chip of register file |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116758971A CN116758971A (en) | 2023-09-15 |
| CN116758971B true CN116758971B (en) | 2024-02-02 |
Family
ID=87960161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310686313.6A Active CN116758971B (en) | 2023-06-09 | 2023-06-09 | Time sequence test circuit and chip of register file |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116758971B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016040875A (en) * | 2014-08-12 | 2016-03-24 | マイクロン テクノロジー， インク． | Semiconductor device and control method of the same |
| CN115361003A (en) * | 2022-08-15 | 2022-11-18 | 锐掣(杭州)科技有限公司 | Delay chain control circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7339364B2 (en) * | 2006-06-19 | 2008-03-04 | International Business Machines Corporation | Circuit and method for on-chip jitter measurement |
| JP5607289B2 (en) * | 2007-09-07 | 2014-10-15 | ピーエスフォー ルクスコ エスエイアールエル | Timing control circuit and semiconductor memory device |
-
2023
- 2023-06-09 CN CN202310686313.6A patent/CN116758971B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016040875A (en) * | 2014-08-12 | 2016-03-24 | マイクロン テクノロジー， インク． | Semiconductor device and control method of the same |
| CN115361003A (en) * | 2022-08-15 | 2022-11-18 | 锐掣(杭州)科技有限公司 | Delay chain control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116758971A (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9912322B2 (en) | Clock generation circuit that tracks critical path across process, voltage and temperature variation | |
| US7486125B2 (en) | Delay cells and delay line circuits having the same | |
| US7138844B2 (en) | Variable delay circuitry | |
| US6986072B2 (en) | Register capable of corresponding to wide frequency band and signal generating method using the same | |
| EP0773548A2 (en) | Semiconductor memory device | |
| KR19990013465A (en) | Semiconductor integrated circuit device, semiconductor memory system and clock synchronization circuit | |
| US20060253822A1 (en) | Semiconductor integrated circuit and method for designing same | |
| US20190196999A1 (en) | Fpga-based square-wave generator and square-wave generation method | |
| US5467041A (en) | Variable delay buffer circuit | |
| US7605629B2 (en) | Adjusting circuit and method for delay circuit | |
| US8508278B2 (en) | Apparatus and method for external to internal clock generation | |
| US9964596B2 (en) | Integrated circuit with low power scan system | |
| US20210028776A1 (en) | Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scaling in Ultra Low Voltage Designs | |
| CN111859828B (en) | Replicated critical path circuit and chip | |
| US6661728B2 (en) | Supply voltage generating circuit and semiconductor memory device using same | |
| CN115361003A (en) | Delay chain control circuit | |
| Wu et al. | A multiple-stage parallel replica-bitline delay addition technique for reducing timing variation of SRAM sense amplifiers | |
| CN116758971B (en) | Time sequence test circuit and chip of register file | |
| US20230179206A1 (en) | Clock gating cells | |
| US7548099B2 (en) | Semiconductor device with delay section | |
| US7605628B2 (en) | System for glitch-free delay updates of a standard cell-based programmable delay | |
| CN100550628C (en) | Semiconductor integrated circuit | |
| US8115532B2 (en) | Linear monotonic delay chain circuit | |
| US7961009B2 (en) | Domino logic block having data holding function and domino logic including the domino logic block | |
| US6335645B1 (en) | Semiconductor integrated circuit having built-in self-test circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |