CN110830035B - Phase-locked loop and locking detection method and circuit thereof - Google Patents
Phase-locked loop and locking detection method and circuit thereof Download PDFInfo
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- CN110830035B CN110830035B CN201911204646.0A CN201911204646A CN110830035B CN 110830035 B CN110830035 B CN 110830035B CN 201911204646 A CN201911204646 A CN 201911204646A CN 110830035 B CN110830035 B CN 110830035B
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
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Abstract
The application discloses a phase-locked loop and locking detection method, circuit thereof, the locking detection circuit includes: a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal; the pulse width conversion unit is connected with the phase identification unit and is used for outputting a voltage pulse width signal with the pulse width corresponding to the phase difference under the action of the detection result signal; the judging output unit is connected with the pulse width conversion unit and comprises a charge-discharge module and a voltage indication module; the charge-discharge module is used for switching charge-discharge states according to pulse width of the voltage pulse width signal, and the voltage indication module is used for generating a level indication signal corresponding to the periodic charge-discharge average voltage of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indication signal. According to the method and the device, the phase difference is indicated based on the periodic charge-discharge average voltage, so that misjudgment of the locking state caused by instantaneous signal interference is effectively avoided, and the accuracy of locking detection is improved.
Description
Technical Field
The present disclosure relates to the field of analog integrated circuits, and in particular, to a phase locked loop and a method and circuit for detecting the same.
Background
A phase locked loop is an analog circuit commonly found in radio frequency or digital-to-analog hybrid chips for generating a radio frequency carrier signal or clock signal in the chip. The phase-locked loop circuit needs a certain locking time after power-on to enable the phase-locked loop to finish locking and then can output stable carrier signals or clock signals. Therefore, it is necessary to use a lock detection circuit in combination to detect whether the phase-locked loop has completed locking when the phase-locked loop circuit is applied. The basis for determining that the phase locked loop completes locking is that the phase difference (the time interval between the rising edges of the REF (reference clock) signal and the FBK (feedback clock) signal in the phase locked loop circuit) is always smaller than a preset threshold (typically set to 1% of the period of the REF signal of the reference clock).
Referring to fig. 1, fig. 1 shows a lock detection circuit of a phase-locked loop disclosed in the prior art, in which an FBK signal and a REF signal are respectively sent to input terminals of D flip-flops D1 and D2, and are respectively sent to clock terminals of D flip-flops D2 and D1 after being delayed (delay time is equal to a preset threshold) by clock buffers BUF1 and BUF 2. Thus, when the REF signal advances the FBK signal, D2 outputs a high level, when the advance time length is smaller than a preset threshold value, D1 also outputs a high level, AND the high level is output after passing through the AND gate AND1; when the FBK signal advances the REF signal, D1 outputs a high level, AND when the advance time length is smaller than a preset threshold value, D2 also outputs a high level, AND the high level is output after passing through the AND gate AND 1. That is, when the phase difference of the FBK signal, the REF signal is within the preset threshold, the AND gate AND1 will output a high level.
However, in practical applications, when the phase locked loop is not locked, the phase difference between the FBK signal and the REF signal is instantaneously smaller than the threshold value, and for this case, the lock detection circuit shown in fig. 1 outputs a high level, which causes erroneous judgment on the locked state of the phase locked loop and causes logic erroneous processing in the subsequent receiving circuit.
In view of this, it has been a great need for a person skilled in the art to provide a solution to the above-mentioned technical problems.
Disclosure of Invention
The purpose of the application is to provide a phase-locked loop, a locking detection method and a circuit thereof, so as to effectively avoid misjudgment of a locking state caused by instantaneous state interference and improve the accuracy of locking detection.
To solve the above technical problem, in a first aspect, the present application discloses a lock detection circuit of a phase-locked loop, including:
a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal;
the pulse width conversion unit is connected with the phase identification unit and is used for outputting a voltage pulse width signal with the pulse width corresponding to the phase difference under the action of the detection result signal;
the judging output unit is connected with the pulse width conversion unit and comprises a charging and discharging module and a voltage indicating module; the charge-discharge module is used for switching charge-discharge states according to pulse width of the voltage pulse width signal, and the voltage indication module is used for generating a level indication signal corresponding to periodic charge-discharge average voltage of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indication signal.
Optionally, the detection result signal includes a first control pulse width signal and a second control pulse width signal;
the phase identification unit is specifically configured to: outputting a first control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the REF signal is ahead of the FBK signal; and outputting a second control pulse width signal with a pulse width corresponding to the magnitude of the phase difference when the FBK signal leads the REF signal.
Optionally, the voltage pulse width signal is high during the period when the first control pulse width signal is high or the second control pulse width signal is high.
Optionally, the phase identification unit comprises a first D flip-flop, a second D flip-flop, and a nand gate;
the clock end of the first D trigger is used for receiving the REF signal, the positive output end is used for outputting the first control pulse width signal, and the negative output end is used for outputting a first inverse control pulse width signal;
the clock end of the second D trigger is used for receiving the FBK signal, the positive output end is used for outputting the second control pulse width signal, and the negative output end is used for outputting a second inverse control pulse width signal;
the input end of the first D trigger and the input end of the second D trigger are connected with a power supply; the reset end of the first D trigger and the reset end of the second D trigger are connected with the output end of the NAND gate; the two input ends of the NAND gate are respectively used for receiving the first control pulse width signal and the second control pulse width signal.
Optionally, the pulse width conversion unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the source electrode of the first PMOS tube is connected to a power supply, and the drain electrode of the first PMOS tube is connected to the source electrode of the third PMOS tube; the source electrode of the second PMOS tube is connected to a power supply, and the drain electrode of the second PMOS tube is connected to the source electrode of the fourth PMOS tube; the drains of the third PMOS tube, the fourth PMOS tube, the first NMOS tube and the second NMOS tube are all connected with each other and serve as the output end of the pulse width conversion unit;
the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are all connected with each other; the sources of the third NMOS tube and the fourth NMOS tube are grounded;
the grid electrodes of the first PMOS tube and the first NMOS tube are used for receiving the first control pulse width signal; the grid electrodes of the fourth PMOS tube and the fourth NMOS tube are used for receiving the first reverse phase control pulse width signal; the grid electrodes of the second PMOS tube and the third NMOS tube are used for receiving the second control pulse width signal; and the grid electrodes of the third PMOS tube and the second NMOS tube are used for receiving the second reverse phase control pulse width signal.
Optionally, the charge-discharge module includes a fifth PMOS transistor, a fifth NMOS transistor, a ground resistor, and a first capacitor;
the grid electrodes of the fifth PMOS tube and the fifth NMOS tube are connected in parallel and connected with the output end of the pulse width conversion unit; the drains of the fifth PMOS tube and the fifth NMOS tube are connected with the first capacitor and serve as the output end of the charge-discharge module to be connected with the voltage indication module; the other end of the first capacitor is grounded; and the source electrode of the fifth PMOS tube is connected to a power supply, and the source electrode of the fifth NMOS tube is connected to the grounding resistor.
Optionally, the voltage indication module comprises a sixth PMOS tube, a second capacitor, a current source, and an inverter;
the source electrode of the sixth PMOS tube is connected to a power supply, and the grid electrode of the sixth PMOS tube is connected with the output end of the charge-discharge module; the first end of the second capacitor is connected to a power supply; the output end of the current source is grounded; the drain electrode of the sixth PMOS tube, the second end of the second capacitor and the input end of the current source are all connected with each other and are connected with the input end of the inverter; the output end of the inverter is used as the output end of the voltage indication module and is used for outputting the level indication signal.
In a second aspect, the present application also discloses a phase locked loop comprising any of the lock detection circuits described above.
In a third aspect, the present application further discloses a lock detection method of a phase-locked loop, including:
detecting the phase difference of the REF signal and the FBK signal and generating a detection result signal;
generating a voltage pulse width signal with a pulse width corresponding to the magnitude of the phase difference based on the detection result signal;
switching the charge and discharge states of the charge and discharge module according to the pulse width of the voltage pulse width signal;
a level indication signal corresponding to a periodic charge-discharge average voltage of the charge-discharge module is generated so as to indicate whether the phase difference is smaller than a preset value.
Optionally, the detection result signal includes a first control pulse width signal and a second control pulse width signal;
the detecting the phase difference of the REF signal and the FBK signal and generating a detection result signal includes: generating a first control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the REF signal leads the FBK signal; generating a second control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the FBK signal leads the REF signal; the voltage pulse width signal is high during the period when the first control pulse width signal is high or the second control pulse width signal is high.
The lock detection circuit of the phase-locked loop provided by the application comprises: a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal; the pulse width conversion unit is connected with the phase identification unit and is used for outputting a voltage pulse width signal with the pulse width corresponding to the phase difference under the action of the detection result signal; the judging output unit is connected with the pulse width conversion unit and comprises a charging and discharging module and a voltage indicating module; the charge-discharge module is used for switching charge-discharge states according to pulse width of the voltage pulse width signal, and the voltage indication module is used for generating a level indication signal corresponding to periodic charge-discharge average voltage of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indication signal.
Therefore, the charging and discharging module is controlled to charge and discharge based on the phase detection results of the REF signal and the FBK signal, the phase difference is indicated based on the periodic charging and discharging average voltage, the misjudgment of the locking state when the phase difference of the REF signal and the FBK signal is instantaneously smaller than the preset threshold value is effectively avoided by utilizing the non-mutation of the average voltage, and the anti-interference performance on the instantaneous signal state and the accuracy of locking detection are improved. The phase-locked loop and the locking detection method thereof also have the beneficial effects.
Drawings
In order to more clearly illustrate the prior art and the technical solutions in the embodiments of the present application, the following will briefly describe the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following figures related to the embodiments of the present application are only some of the embodiments of the present application, and it is obvious to those skilled in the art that other figures can be obtained from the provided figures without any inventive effort, and the obtained other figures also belong to the protection scope of the present application.
Fig. 1 is a circuit configuration diagram of a lock detection circuit of a phase-locked loop in the prior art;
fig. 2 is a block diagram of a lock detection circuit of a phase-locked loop according to an embodiment of the present disclosure;
fig. 3 is a circuit configuration diagram of a phase identification unit according to an embodiment of the present application;
fig. 4 is a circuit configuration diagram of a pulse width conversion unit and a judgment output unit according to an embodiment of the present application;
fig. 5 is a flowchart of a lock detection method of a phase-locked loop according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a phase-locked loop, a locking detection method and a circuit thereof, so as to effectively avoid misjudgment of a locking state caused by instantaneous state interference and improve the accuracy of locking detection.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The lock detection circuit of the phase locked loop is a circuit for detecting whether the phase locked loop has completed locking, and detects by determining whether the phase difference (time interval between rising edges of two) of the REF (reference clock) signal and the FBK (feedback clock) signal inside the phase locked loop circuit is always smaller than a preset threshold (typically set to 1% of the period of the REF signal of the reference clock). However, in practical application, when the phase-locked loop is not locked, the phase difference between the FBK signal and the REF signal is instantaneously smaller than the threshold value, and for this case, the lock detection circuit in the prior art outputs a high level as well, which causes erroneous judgment on the locked state of the phase-locked loop and causes the subsequent receiving circuit to generate logic erroneous processing. In view of the above, the present application provides a phase locked loop and a lock detection scheme thereof, which can effectively solve the above-mentioned problems.
Referring to fig. 2, an embodiment of the present application discloses a lock detection circuit of a phase-locked loop. The lock detection circuit includes a phase identification unit 10 for detecting a phase difference of the REF signal and the FBK signal and outputting a detection result signal.
Specifically, the phase difference may be a phase difference that the REF signal leads the FBK signal or a phase difference that the FBK signal leads the REF signal, that is, as long as the phase difference between the two signals is continuously smaller than a preset threshold, it may be determined that the phase lock loop is locked. Thus, as a specific embodiment, the detection result signal may include a first control pulse width signal a and a second control pulse width signal B, and the phase identification unit 10 may be specifically configured to output the first control pulse width signal a having a pulse width corresponding to the magnitude of the phase difference when the REF signal leads the FBK signal; when the FBK signal leads the REF signal, a second control pulse width signal B having a pulse width corresponding to the magnitude of the phase difference is outputted.
Referring to fig. 3, the embodiment of the present application discloses a circuit configuration of the phase identification unit 10. In the present embodiment, the phase evaluating unit 10 specifically includes a first D flip-flop DFF1, a second D flip-flop, a NAND gate NAND1;
the clock end of the first D trigger DFF1 is used for receiving the REF signal, the positive output end is used for outputting a first control pulse width signal A, and the negative output end is used for outputting a first inverse control pulse width signal An; the clock end of the second D trigger is used for receiving the FBK signal, the positive output end is used for outputting a second control pulse width signal B, and the negative output end is used for outputting a second inverse control pulse width signal Bn;
the input end of the first D trigger DFF1 and the input end of the second D trigger are connected with a power supply; the reset end of the first D trigger DFF1 and the reset end of the second D trigger are connected with the output end of the NAND gate NAND1; the two input terminals of the NAND gate NAND1 are respectively used for receiving the first control pulse width signal a and the second control pulse width signal B.
The phase identification unit 10 can identify the magnitude of the phase difference between the REF signal and the FBK signal and determine the lead and lag relationship therebetween. The specific working principle is as follows: if the phase of the REF signal is advanced by the FBK signal (i.e., the rising edge of the REF signal is advanced by the FBK), a outputs a high level, an outputs a low level, B outputs a high level, and Bn outputs a low level when the rising edge of the FBK signal is coming, and at this time, since A, B is both high, the NAND gate NAND1 outputs a low level to reset the first D flip-flop DFF1 and the second D flip-flop DFF2, A, B is reset to a low level, and An and Bn are reset to a high level. The high level (low level of An) duration of a is the phase difference of the REF signal leading the FBK signal throughout the signal period, and the high level (low level of Bn) duration of B is negligible.
Similarly, if the phase of the FBK signal leads the REF signal, the duration of the high level of the second control pulse width signal B (the low level of the second inversion control pulse width signal Bn) is the phase difference of the FBK signal which leads the REF signal, and the duration of the high level of the first control pulse width signal a (the low level of the first inversion control pulse width signal An) is negligible.
As can be seen, the phase identification unit 10 converts the phase difference of the REF signal ahead of the FBK signal into a high level pulse width of the first control pulse width signal a (a low level pulse width of the first inversion control pulse width signal An), and converts the phase of the FBK signal ahead of the REF signal into a high level pulse width of the second control pulse width signal B (a low level pulse width of the second inversion control pulse width signal Bn).
The lock detection circuit disclosed in the present application further includes a pulse width conversion unit 20 connected to the phase identification unit 10, for outputting a voltage pulse width signal having a pulse width corresponding to the magnitude of the phase difference under the action of the detection result signal.
Specifically, the pulse width conversion unit 20 functions to represent the phase difference of the two signals in terms of signal pulse width, whether the REF signal leads the FBK signal or the FBK signal leads the REF signal. That is, the voltage pulse width signals are both high during the period when the first control pulse width signal a is high or the second control pulse width signal B is high.
Referring to fig. 4, the embodiment of the present application discloses a specific circuit structure of the pulse width conversion unit 20. In this embodiment, the pulse width conversion unit 20 includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a first NMOS transistor Mn1, a second NMOS transistor Mn2, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn4;
the source electrode of the first PMOS tube MP1 is connected to a power supply, and the drain electrode is connected to the source electrode of the third PMOS tube MP 3; the source electrode of the second PMOS tube MP2 is connected to a power supply, and the drain electrode is connected to the source electrode of the fourth PMOS tube MP 4; the drains of the third PMOS tube Mp3, the fourth PMOS tube Mp4, the first NMOS tube Mn1 and the second NMOS tube Mn2 are connected with each other and serve as the output end of the pulse width conversion unit 20; the voltage of the node Vx is the voltage pulse width signal;
the source electrode of the first NMOS tube Mn1, the source electrode of the second NMOS tube Mn2, the drain electrode of the third NMOS tube Mn3 and the drain electrode of the fourth NMOS tube Mn4 are all connected with each other; the sources of the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are grounded;
the grid electrodes of the first PMOS tube MP1 and the first NMOS tube Mn1 are used for receiving a first control pulse width signal A; the grid electrodes of the fourth PMOS tube MP4 and the fourth NMOS tube Mn4 are used for receiving the first inversion control pulse width signal An; the grid electrodes of the second PMOS tube MP2 and the third NMOS tube Mn3 are used for receiving a second control pulse width signal B; the gates of the third PMOS transistor Mp3 and the second NMOS transistor Mn2 are both configured to receive the second inversion control pulse width signal Bn.
The pulse width conversion unit 20 may specifically convert both the high level pulse width of a and the high level pulse width of B into the high level pulse width of the output node Vx. The specific working principle is as follows: when A is high level, an is low level, B is low level, bn is high level, the second PMOS tube MP2 and the fourth PMOS tube MP4 are conducted, the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are cut off, and the voltage of the output node Vx is pulled up to VDD; when B is high level, bn is low level, A is low level, an is high level, the first PMOS tube MP1 and the third PMOS tube MP3 are conducted, the first NMOS tube Mn1 and the second NMOS tube Mn2 are cut off, and the voltage of the output node Vx is pulled up to VDD; when the first D flip-flop DFF1 and the second D flip-flop DFF2 are both in the reset state, a and B are low level, an and Bn are high level, the second NMOS transistor Mn2 and the fourth NMOS transistor Mn4 are turned on, the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4 are turned off, and the voltage of the output node Vx is pulled down to low level.
It can be seen that, both the high pulse width of a when the REF signal is advanced and the high pulse width of B when the FBK signal is advanced, the voltage pulse width signal of Vx node with the same width, which is specifically the magnitude of the phase difference between the REF signal and the FBK signal, is converted by the pulse width conversion unit 20.
The lock detection circuit disclosed in the present application further includes a judgment output unit 30 connected to the pulse width conversion unit 20, including a charge and discharge module 301 and a voltage indication module 302; the charge-discharge module 301 is configured to switch the charge-discharge state according to the pulse width of the voltage pulse width signal, and the voltage indicating module 302 is configured to generate a level indicating signal corresponding to the periodic charge-discharge average voltage of the charge-discharge module 301, so as to indicate whether the phase difference is smaller than a preset value by using the level indicating signal.
Among them, it is easily understood that the charge and discharge module 301 may be implemented based on capacitance. Specifically, as described above, the pulse width of the voltage pulse width signal outputted from the pulse width conversion unit 20 is equal to the phase difference between the REF signal and the FBK signal, and the charge/discharge module 301 in the judgment output unit 30 switches to charge/discharge according to the high-low level state of the voltage pulse width signal, so that the pulse width of the voltage pulse width signal determines the magnitude of the periodic charge/discharge average voltage outputted from the charge/discharge module 301, that is, the phase difference between the REF signal and the FBK signal determines the magnitude of the periodic charge/discharge average voltage outputted from the charge/discharge module 301.
The level indication signal output by the voltage indication module 302 indicates the magnitude of the periodic charge-discharge average voltage, and by adjusting the circuit parameter setting of the voltage indication module 302, the level indication signal can be made to be high level when the periodic charge-discharge average voltage is greater than a certain fixed value, and be made to be low level when the periodic charge-discharge average voltage is less than the fixed value, and the fixed value of the periodic charge-discharge average voltage corresponds to a preset threshold value of the phase difference. Thus, the magnitude of the phase difference between the REF signal and the FBK signal can be indicated by the level indication signal, and the phase difference can be used as an output result of the lock detection circuit.
As a specific embodiment, fig. 4 also discloses a circuit structure of the determination output unit 30 provided in the embodiment of the present application. In this embodiment, the charge-discharge module 301 includes a fifth PMOS transistor Mp5, a fifth NMOS transistor Mn5, a ground resistor R1, and a first capacitor C1; the grid electrodes of the fifth PMOS tube MP5 and the fifth NMOS tube Mn5 are connected in parallel and connected with the output end of the pulse width conversion unit 20; the drains of the fifth PMOS tube Mp5 and the fifth NMOS tube Mn5 are connected with the first capacitor C1 and serve as the output end of the charge-discharge module 301 to be connected with the voltage indication module 302; the other end of the first capacitor C1 is grounded; the source of the fifth PMOS Mp5 is connected to the power supply, and the source of the fifth NMOS Mn5 is connected to the ground resistor R1. The voltage of the node Vc is the average charge-discharge voltage in the period.
Meanwhile, in the present embodiment, the voltage indication module 302 includes a sixth PMOS transistor, a second capacitor C2, a current source, and an inverter INV1; the source electrode of the sixth PMOS tube is connected to a power supply, and the grid electrode is connected with the output end of the charge-discharge module 301; the first end of the second capacitor C2 is connected to a power supply; the output end of the current source is grounded; the drain electrode of the sixth PMOS tube, the second end of the second capacitor C2 and the input end of the current source are all connected with each other and are connected with the input end of the inverter INV1; an output terminal of the inverter INV1 serves as an output terminal of the voltage indication module 302 for outputting the level indication signal ld_out.
The specific operation principle of the judgment output unit 30 will be described below.
The phase difference of the REF signal and the FBK signal is set to w, and the preset threshold for determining the phase difference of the locked phase of the phase-locked loop is 1% of the period of the REF signal, i.e., 1% Tref (Tref is the period of the REF signal).
The output node Vx of the pulse width conversion unit 20 outputs a pulse width of w width. When Vx is in a high level, the fifth NMOS transistor Mn5 is turned on, the charge stored in the plate on the first capacitor C1 is discharged to the ground through the fifth NMOS transistor Mn5 and the ground resistor R1, and the voltage of the node Vc is reduced. When Vx is at a low level, the fifth PMOS transistor Mp5 is turned on, ignoring the on-resistance of the fifth NMOS transistor Mp5, the voltage of the node Vc is pulled up to VDD rapidly. Under the action of the periodic voltage pulse width signal at the node Vx, the balance voltage of the Vc node is: the method comprises the steps of carrying out a first treatment on the surface of the
The balance voltage of the Vc node acts on the gate of the sixth PMOS transistor Mp6, and the drain current I3 of the sixth PMOS transistor Mp6 is:
where k is a constant, determined by the size and process of Mp 6; vth3 is the threshold voltage of the sixth PMOS transistor Mp 6. It can be seen that the magnitude of the drain current I3 depends on the phase difference w.
Because the drain electrode of the sixth PMOS transistor Mp6 is connected to the lower electrode plate of the second capacitor C2 and the input end of the current source at the same time, the current of the current source is IDC1, so when I3> IDC1, the lower electrode plate of the second capacitor C2 has a net charge flowing in, and then the voltage of the node Vd is stabilized at VDD (high level), and the level indication signal output after passing through the inverter INV1 is low level; when I3 is less than or equal to IDC1, the lower polar plate of the second capacitor C2 has net charges flowing out, then the voltage of the node Vd is stabilized at 0 (low level), and the level indicating signal output after passing through the inverter INV1 is high level.
When I3 is less than or equal to IDC1, it can be inferred that w should satisfy:
by adjusting the size of IDC1, the right side of the inequality can be made equal to 1% tref, i.e
Therefore, when w is less than or equal to 1% tref, I3 is less than or equal to IDC1, vd is low level, and the level indication signal LD_OUT finally output by the circuit is high level, so that the phase-locked loop is indicated to complete locking, and the function of detecting whether the phase-locked loop is complete or not is realized.
It should be noted that, in the present application, the determination output unit 30 indicates the magnitude of the phase difference based on the average voltage of the periodic charge and discharge of the charge and discharge module 301, where the average voltage is the voltage after the equalization of the periodic switching charge and discharge states, and has no variability, so that even if the phase difference of the REF signal and the FBK signal is only instantaneously smaller than the preset threshold value and the phase lock loop does not complete the locking, the magnitude of the average voltage of the periodic charge and discharge will not change suddenly, and the determination output unit 30 will not output a high level indication signal, which causes erroneous determination of the locking state.
The lock detection circuit of the phase-locked loop disclosed in the embodiment of the application comprises: a phase identification unit 10 for detecting a phase difference of the REF signal and the FBK signal and outputting a detection result signal; a pulse width conversion unit 20 connected to the phase identification unit 10, for outputting a voltage pulse width signal corresponding to the magnitude of the pulse width and the phase difference under the action of the detection result signal; a judgment output unit 30 connected to the pulse width conversion unit 20, including a charge/discharge module 301 and a voltage indication module 302; the charge-discharge module 301 is configured to switch the charge-discharge state according to the pulse width of the voltage pulse width signal, and the voltage indicating module 302 is configured to generate a level indicating signal corresponding to the periodic charge-discharge average voltage of the charge-discharge module 301, so as to indicate whether the phase difference is smaller than a preset threshold by using the level indicating signal.
Therefore, the lock detection circuit of the phase-locked loop disclosed by the embodiment of the application controls the charge and discharge module to charge and discharge based on the phase detection results of the REF signal and the FBK signal, further indicates the phase difference based on the periodic charge and discharge average voltage, and effectively avoids misjudgment of the lock state when the phase difference of the REF signal and the FBK signal is instantaneously smaller than the preset threshold value by utilizing the non-mutation of the average voltage, thereby improving the anti-interference performance of the instantaneous signal state and the accuracy of the lock detection.
Further, the application also discloses a phase locked loop comprising any of the lock detection circuits described above.
Referring to fig. 5, the embodiment of the application also discloses a lock detection method of a phase-locked loop, which mainly includes:
s101: the phase difference between the REF signal and the FBK signal is detected and a detection result signal is generated.
In one embodiment, the detection result signal may include a first control pulse width signal a and a second control pulse width signal B. Step S101 may specifically include: generating a first control pulse width signal A with a pulse width corresponding to the magnitude of the phase difference when the REF signal leads the FBK signal; when the FBK signal leads the REF signal, a second control pulse width signal B having a pulse width corresponding to the magnitude of the phase difference is generated.
S102: a voltage pulse width signal having a pulse width corresponding to the magnitude of the phase difference is generated based on the detection result signal.
Specifically, the voltage pulse width signal is at a high level during the period when the first control pulse width signal a is at a high level or the second control pulse width signal B is at a high level.
S103: and switching the charge and discharge states of the charge and discharge module according to the pulse width of the voltage pulse width signal.
S104: a level indication signal corresponding to the periodic charge-discharge average voltage of the charge-discharge module is generated so as to indicate whether the phase difference is smaller than a preset value.
Therefore, according to the lock detection method of the phase-locked loop disclosed by the embodiment of the application, the charge and discharge module is controlled to charge and discharge based on the phase detection results of the REF signal and the FBK signal, and further the phase difference is indicated based on the periodic charge and discharge average voltage, so that the misjudgment of the lock state when the phase difference of the REF signal and the FBK signal is instantaneously smaller than the preset threshold value is effectively avoided by utilizing the non-mutation of the average voltage, and the anti-interference performance of the instantaneous signal state and the accuracy of lock detection are improved.
For the specific details of the lock detection method of the pll, reference is made to the foregoing detailed description of the lock detection circuit of the pll, and the details are not repeated here.
In this application, each embodiment is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, since it corresponds to the circuit disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The technical scheme provided by the application is described in detail. Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the present application.
Claims (10)
1. A lock detection circuit of a phase locked loop, comprising:
a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal;
the pulse width conversion unit is connected with the phase identification unit and is used for outputting a voltage pulse width signal with the pulse width corresponding to the phase difference under the action of the detection result signal;
the judging output unit is connected with the pulse width conversion unit and comprises a charging and discharging module and a voltage indicating module; the charge-discharge module is used for switching charge-discharge states according to pulse width of the voltage pulse width signal, and the voltage indication module is used for generating a level indication signal corresponding to periodic charge-discharge average voltage of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indication signal.
2. The lock detection circuit of claim 1, wherein the detection result signal comprises a first control pulse width signal and a second control pulse width signal;
the phase identification unit is specifically configured to: outputting a first control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the REF signal is ahead of the FBK signal; and outputting a second control pulse width signal with a pulse width corresponding to the magnitude of the phase difference when the FBK signal leads the REF signal.
3. The lock detection circuit of claim 2, wherein the voltage pulse width signal is high during the period when the first control pulse width signal is high or the second control pulse width signal is high.
4. The lock detection circuit of claim 3, wherein the phase qualification unit comprises a first D flip-flop, a second D flip-flop, a nand gate;
the clock end of the first D trigger is used for receiving the REF signal, the positive output end is used for outputting the first control pulse width signal, and the negative output end is used for outputting a first inverse control pulse width signal;
the clock end of the second D trigger is used for receiving the FBK signal, the positive output end is used for outputting the second control pulse width signal, and the negative output end is used for outputting a second inverse control pulse width signal;
the input end of the first D trigger and the input end of the second D trigger are connected with a power supply; the reset end of the first D trigger and the reset end of the second D trigger are connected with the output end of the NAND gate; the two input ends of the NAND gate are respectively used for receiving the first control pulse width signal and the second control pulse width signal.
5. The lock detection circuit of claim 4, wherein the pulse width conversion unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor;
the source electrode of the first PMOS tube is connected to a power supply, and the drain electrode of the first PMOS tube is connected to the source electrode of the third PMOS tube; the source electrode of the second PMOS tube is connected to a power supply, and the drain electrode of the second PMOS tube is connected to the source electrode of the fourth PMOS tube; the drains of the third PMOS tube, the fourth PMOS tube, the first NMOS tube and the second NMOS tube are all connected with each other and serve as the output end of the pulse width conversion unit;
the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are all connected with each other; the sources of the third NMOS tube and the fourth NMOS tube are grounded;
the grid electrodes of the first PMOS tube and the first NMOS tube are used for receiving the first control pulse width signal; the grid electrodes of the fourth PMOS tube and the fourth NMOS tube are used for receiving the first reverse phase control pulse width signal; the grid electrodes of the second PMOS tube and the third NMOS tube are used for receiving the second control pulse width signal; and the grid electrodes of the third PMOS tube and the second NMOS tube are used for receiving the second reverse phase control pulse width signal.
6. The lock detection circuit according to any one of claims 1 to 5, wherein the charge-discharge module includes a fifth PMOS transistor, a fifth NMOS transistor, a ground resistor, and a first capacitor;
the grid electrodes of the fifth PMOS tube and the fifth NMOS tube are connected in parallel and connected with the output end of the pulse width conversion unit; the drains of the fifth PMOS tube and the fifth NMOS tube are connected with the first capacitor and serve as the output end of the charge-discharge module to be connected with the voltage indication module; the other end of the first capacitor is grounded; and the source electrode of the fifth PMOS tube is connected to a power supply, and the source electrode of the fifth NMOS tube is connected to the grounding resistor.
7. The lock detection circuit of claim 6, wherein the voltage indication module comprises a sixth PMOS transistor, a second capacitor, a current source, and an inverter;
the source electrode of the sixth PMOS tube is connected to a power supply, and the grid electrode of the sixth PMOS tube is connected with the output end of the charge-discharge module; the first end of the second capacitor is connected to a power supply; the output end of the current source is grounded; the drain electrode of the sixth PMOS tube, the second end of the second capacitor and the input end of the current source are all connected with each other and are connected with the input end of the inverter; the output end of the inverter is used as the output end of the voltage indication module and is used for outputting the level indication signal.
8. A phase locked loop comprising a lock detection circuit as claimed in any one of claims 1 to 7.
9. A lock detection method of a phase locked loop, comprising:
detecting the phase difference of the REF signal and the FBK signal and generating a detection result signal;
generating a voltage pulse width signal with a pulse width corresponding to the magnitude of the phase difference based on the detection result signal;
switching the charge and discharge states of the charge and discharge module according to the pulse width of the voltage pulse width signal;
a level indication signal corresponding to a periodic charge-discharge average voltage of the charge-discharge module is generated so as to indicate whether the phase difference is smaller than a preset value.
10. The lock detection method according to claim 9, wherein the detection result signal includes a first control pulse width signal and a second control pulse width signal;
the detecting the phase difference of the REF signal and the FBK signal and generating a detection result signal includes: generating a first control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the REF signal leads the FBK signal; generating a second control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the FBK signal leads the REF signal; the voltage pulse width signal is high during the period when the first control pulse width signal is high or the second control pulse width signal is high.
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