JPH11289251A - Phase comparator and phase synchronizng loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To variably set the minimum pulse width of a phase difference signal outputted from a phase comparator. SOLUTION: The leading edges of a reference signal Sref , and an oscillation signal Sosc are respectively detected by edge detection circuits 10a, 10b in the phase comparator 200 and detected results are inputted to SR flip flops(FFs) 30a, 30b respectively constituted of ECL circuits to set these FFs 30a, 30b. A reset signal is generated by a reset circuit constituted of an OR circuit OR1 and an inversion circuit INV5 in accordance with the states of the FFs 30a, 30b and the FFs 30a, 30b are set to a reset state, so that an UP signal Sup and a DOWN signal Sdw having prescribed width are generated in accordance with a phase difference between the reference signal Sref and the oscillation signal Sosc . Delay time required for delaying the reset signal by a delay circuit DL is variable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit and a phase locked loop circuit provided with the phase comparison circuit for use in portable telephones and the like.

[0002]

2. Description of the Related Art A phase locked loop (PLL) is a PLL (Phase L) circuit.
ocked Loop) circuit. Voltage controlled oscillator (VCO) for PLL circuit
And a phase comparison circuit are generally used. The phase comparison circuit compares the phase of the oscillation signal S _OSC from, for example, a frequency generation circuit having a voltage-controlled oscillation circuit with the reference signal _Sref, and outputs a phase difference signal corresponding to the phase difference. Then, based on the phase difference signal, the charge pump circuit charges and discharges the capacitor (charge and discharge).
And a voltage signal corresponding to the phase difference is generated. The voltage signal is supplied to a voltage-controlled oscillation circuit as a control signal after suppressing a high-frequency component including noise through, for example, a low-pass filter. The voltage controlled oscillation circuit oscillates at a frequency according to the control signal and outputs an oscillation signal having a desired frequency.

FIG. 11 is a circuit diagram showing an example of a conventional phase comparison circuit. This phase comparison circuit is an edge detection circuit 1
0a, 10b, RS flip-flops 20a, 20b,
It comprises an inverting circuit (inverter) INV3 and AND circuits (AND circuits) AND3, AND4 and AND5.

The edge detection circuit 10a includes an inversion circuit INV
1 and an AND circuit AND1, and the edge detection circuit 10b is configured by an inverting circuit INV2 and an AND circuit AND2. Edge detecting circuit 10a detects the rising edge of the reference signal S _ref input to the input terminal T _1, the detection result is input to the input terminal S of the RS flip-flop 20a. The output signal of the inverting circuit INV3 is input to the input terminal R of the RS flip-flop 20a. Edge detecting circuit 10b detects the rising edge of the oscillation signal S _osc, which is input to the input terminal T _2, the detection result is input to the input terminal S of the RS flip-flop 20b. The output signal of the inverting circuit INV3 is input to the input terminal R of the RS flip-flop 20b.

The input terminal of the inversion circuit INV3 is connected to the output terminal of the AND circuit AND3, and the input terminal of the AND circuit AND3 is connected to the output terminals of the AND circuits AND4 and AND5, respectively. One input terminal of the AND circuit AND4 is connected to the output terminal of the edge detection circuit 10a, and the other input terminal is connected to the inverted output terminal Qz of the RS flip-flop 20a. AND circuit AND
5, one input terminal is connected to the output terminal of the edge detection circuit 10b, and the other input terminal is connected to the inverted output terminal Qz of the RS flip-flop 20b.

The output terminal Q of the RS flip-flop 20a
Is connected to the up signal S _up output terminal T ₃ of the phase comparison circuit, and the output terminal Q of the RS flip-flop 20 b is connected to the down signal S _dw output terminal T ₄ of the phase comparison circuit.

[0007] RS flip-flops 20a and 20b
Is constituted by a NAND circuit (NAND circuit). FIG. 12 shows an equivalent circuit of the NAND circuit 2.
The NAND circuit 2 receives an input signal A and an input signal B, and outputs an inverted logical product Q of these signals.

FIG. 13 shows an example of a NAND circuit 2 composed of bipolar transistors. The NAND circuit 2 includes npn transistors Q1, Q2, Q3, Q4, resistance elements R1, R2, and a current source IS1.

The input signal A and its inverted signal AX are applied to the bases of the transistors Q1 and Q2, respectively, and the emitters are connected to the collector of the transistor Q3. Further, the collector of the transistor Q1 and Q2 are connected to the supply line of the power supply voltage V _CC through a respective resistance elements R1, R2. The AND signal Q is output from the collector of the transistor Q1, and the inverted signal QX is output from the collector of the transistor Q2. The input signal B is applied to the base of the transistor Q3, and the inverted signal BX of the signal B is applied to the base of the transistor Q4. The collector of the transistor Q4 is connected to the collector of the transistor Q2, and the emitters of the transistors Q3 and Q4 are connected to the current source IS1.

In the NAND circuit 2, for example, when the input signals A and B are both at logic "1", that is, at a high level, the transistors Q1 and Q3 are both kept on, so that the collector of the transistor Q1 is low. Retained on level. That is, the output signal Q becomes logic “0”. When either of the input signals A and B is at logic "0", that is, at a low level, the output signal Q is held at logic "1", that is, at a high level. Thus, the inverted logical product Q of the input signals A and B is obtained by the circuit of FIG.

FIG. 14 shows an equivalent circuit of the RS flip-flop 20 composed of two NAND circuits 2a and 2b. One input terminal of the NAND circuit 2a is connected to the input terminal of the set signal S, and the other input terminal is connected to the output terminal of the NAND circuit 2b. One input terminal of the NAND circuit 2b is connected to an input terminal of the reset signal R, and the other input terminal is connected to an output terminal of the NAND circuit 2a. Output terminals of the NAND circuits 2a and 2b form output terminals of the signal Q and its inverted signal Qz, respectively.

The RS flip-flop 20 shown in FIG. 14 is effective when the input signals S and R are at a low level. For example, by setting the set signal S to a low level, the RS flip-flop 20 is set, the output terminal Q is held at a high level, and the inverted output terminal Qz is held at a low level. By setting the reset signal R to low level, the RS flip-flop 20 is reset, and the output terminal Q is held at low level and the inverted output terminal Qz is held at high level. When both the set signal S and the reset signal R are set to the high level, the original state of the RS flip-flop 20 is maintained. When both the set signal S and the reset signal R are set to the low level, the RS flip-flop 20 is reset. Is uncertain,
prohibited.

FIG. 15 is a circuit diagram of an R circuit constituted by a NAND circuit.
1 shows a configuration example of an S flip-flop 20a. Note that this RS flip-flop 20a is an RS flip-flop 20a that constitutes the phase comparison circuit shown in FIG.
It has the same configuration as 20b.

The RS flip-flop 20a has an np
, Q28, resistance elements R21, R22, R23, R24 and current source IS2
1, IS22.

In the RS flip-flop 20a, the input set signal S and reset signal R are valid at a high level. That is, when the set signal S is at the high level and the reset signal R is at the low level, the RS flip-flop 20a is set, the output terminal Q is held at the high level, and the inverted output terminal Qz is held at the low level. Conversely, when the set signal S is at a low level and the reset signal R is at a high level, the RS flip-flop 20a is reset, the output terminal Q is held at a low level, and the inverted output terminal Qz is held at a high level.

When both the set signal S and the reset signal R are at the high level, the transistor Q28 is in the on state, so that the output terminal Q is at the low level and the inverted output terminal Q
z is held at a high level. Further, when both the set signal S and the reset signal R are at low level, R
The original state of S flip-flop 20a is maintained.
FIG. 19 shows a truth table of the RS flip-flop 20a. In the RS flip-flop 20a, the input signal S
And R, the state of the flip-flop is set, and there is no prohibited state, and a stable operation can be obtained.

FIG. 16 shows a configuration example of a PLL circuit configured using a phase comparison circuit. This PLL circuit includes a phase comparison circuit 100, a reference oscillation circuit 110, a capacitor C ₀ , a charge pump circuit 120, a low-pass filter 130, a voltage controlled oscillation circuit 140, a frequency dividing circuit 150, and a frequency dividing circuit 160.

An oscillation signal having a frequency f ₀ is generated by the reference oscillation circuit 110. This oscillation signal is frequency-divided by N (frequency is reduced to 1 / N) by the frequency divider 160, and the frequency- _divided signal is input to the phase comparator 100 as the reference signal _Sref . On the other hand, the oscillation signal from the voltage controlled oscillation circuit 140 is frequency-divided by M (frequency is reduced to 1 / M) by the frequency division circuit 150, and the frequency- _divided signal is input to the phase comparison circuit 100 as the oscillation signal S _osc. You. Here, M and N are integers of 2 or more.

The phase comparison circuit 100 generates an up signal S _up and a down signal S _dw having a predetermined pulse width according to the phase difference between the input oscillation signal S _osc and the reference signal S _ref.
Is generated and input to the charge pump circuit 120. The charge pump circuit 120 includes an up signal S _up and a down signal S _dw that are phase difference signals from the phase comparison circuit 100.
, The capacitor C _{0 is} charged or discharged, and the level of the output voltage V ₀ is controlled.

The output voltage V ₀ of the charge pump circuit 120
The high-frequency noise is removed by the low-pass filter 130, and only the low-frequency component is output to the voltage-controlled oscillation circuit 140 as a control signal. In the voltage controlled oscillation circuit 140,
Frequency f _s of the oscillating signal is controlled according to the voltage level of the input signal. The oscillation signal is input to the frequency dividing circuit 150,
After the frequency division, the phase comparison circuit 10 generates the oscillation signal S _osc.
Input to 0.

In this PLL circuit, the frequency dividing circuit 150
Is controlled so that the phase of the oscillation signal S _osc always follows the reference signal S _ref from the frequency divider 160, so that the frequency of the oscillation signal S _osc and the frequency of the reference signal S _ref are controlled to match. Therefore, the frequency f _s of the oscillation signal from the voltage controlled oscillation circuit 140 is obtained by the following equation. f _s = f ₀ · M / N (1) where M and N are frequency dividing circuits 150 and 1 respectively.
The division ratio is 60.

FIG. 17 shows the PLL circuit shown in FIG.
An up signal S which is an output signal of the phase comparison circuit 100 according to the phase difference between the oscillation signal S _osc and the reference signal S _ref.
The waveform of the _up and down signal _Sdw is shown.

In FIGS. 17A and 17B, the reference signal S
_ref indicates the waveforms of the output signals S _up and S _dw when the phase is advanced as compared with the oscillation signal S _osc . As shown, in this case, the width of the up signal S _up is set wider than the width of the down signal S _dw by a phase difference. The width ΔT of the down signal S _dw is set according to the signal delay time of the reset circuit and the signal delay time of the RS flip-flop as described above. The reset circuit in this case is an AND circuit AND in the phase comparison circuit of FIG.
3, AND4, AND5 and an inverting circuit INV3.

In FIGS. 17C and 17D, the reference signal S
_ref shows the waveforms of the output signals S _up and S _dw when the phase is delayed as compared with the oscillation signal S _osc . As shown, in this case, the width of the down signal S _dw is set wider than the width of the up signal S _up by a phase difference. Note that the width ΔT of the up signal S _up is set according to the signal delay time of the reset circuit and the signal delay time of the RS flip-flop, as described above.

FIGS. 17E and 17F show the reference signal S _ref.
7 shows the waveforms of the output signals S _up and S _dw when the phase of the oscillation signal S _osc coincides with that of the oscillation signal S _osc . As shown, in this case, the widths of the up signal S _up and the down signal S _dw are both set to ΔT.

According to the pulse widths of the up signal S _up and the down signal S _dw generated by the phase comparison circuit 100,
In the charge pump circuit 120, with respect to the capacitor C _0, the charge or discharge is performed. Therefore, the voltage level of the output signal V ₀ of the charge pump circuit 120 changes according to the pulse widths of the up signal S _up and the down signal S _dw , and a level fluctuation of ± ΔV occurs as an error voltage.

The frequency f _s of the output signal of the voltage controlled oscillator 140 is controlled in accordance with the level change of the output voltage of the charge pump circuit 120. As a result, the oscillation signal S _osc from the frequency divider 150 is Control is performed so that the phase of the reference signal _Sref from the circuit 160 matches.

[0028]

In the conventional phase comparator, the sum of the signal delay time of the reset circuit and the signal delay time of the RS flip-flop is a minimum pulse width ΔT, and the minimum pulse width ΔT is a fixed value. is there. When the minimum pulse width ΔT is almost zero, that is, when ΔT = T0 ≒ 0, and when the minimum pulse width ΔT is larger than this, that is, when ΔT >> T0
FIG. 18 shows an example of the noise characteristic of the output signal of the PLL circuit in the case where. When the minimum pulse width ΔT is almost zero, the noise component near the frequency f ₀ increases instead.
This is because the pulse width of the up signal S _up and the pulse width of the down signal S _dw are small when the phase of the oscillation signal S _osc and the reference signal S _ref are equal or almost equal to each other, and their phase difference signal is a dead band of the next stage charge pump circuit. It is because it enters. Then, in the range of the dead zone, even if disturbance occurs in the output signal of the voltage controlled oscillator and the phase fluctuates, the phase comparison circuit _{converts the} phase difference into a phase difference signal (up signal S _up and down signal S _dw ). This cannot be reflected sufficiently, and the noise component increases.

On the other hand, if the minimum pulse width ΔT is too large, an increase in the noise component is expected. Therefore, a phase comparison circuit and a PLL circuit in which the minimum pulse width ΔT of the phase difference signal is variable are desired. An object of the present invention is to provide a phase comparison circuit and a PLL circuit in which the minimum pulse width ΔT of the phase difference signal is variable.

[0030]

According to the present invention, there is provided a phase comparison circuit for detecting a rising edge of a first signal.
An edge detection circuit, a second edge detection circuit for detecting a rising edge of the second signal, and a signal of one level corresponding to an output signal of the first edge detection circuit. And a first flip-flop for supplying a signal of the other level to the first output terminal in response to a reset signal, and one of the first flip-flops in response to an output signal of the second edge detection circuit. A second flip-flop for supplying a signal of a level to a second output terminal of the phase comparison circuit, and supplying a signal of the other level to the second output terminal in response to a reset signal; 2
And a delay circuit that outputs the reset signal when the output level of the flip-flop is the one level, and a delay circuit that delays the reset signal is variable.

In the phase locked loop circuit (PLL circuit) of the present invention, a phase comparison circuit for outputting a signal corresponding to the phase difference between the first signal and the second signal, and a signal output from the phase comparison circuit A voltage generation circuit for generating a voltage signal of a corresponding level, a frequency generation circuit for outputting a signal of a frequency corresponding to the voltage signal of the voltage generation circuit as the first signal to the phase comparison circuit, Signal to the second
A phase locked loop circuit comprising: a reference frequency generation circuit that outputs the signal as a signal to the phase comparison circuit, wherein the phase comparison circuit includes a first edge detection circuit that detects a rising edge of the first signal; A second edge detection circuit for detecting a rising edge of the second signal, and a signal of one level according to an output signal of the first edge detection circuit, to a first output terminal of the phase comparison circuit. A first flip-flop for supplying a signal of the other level to the first output terminal in response to a reset signal, and a signal of one level in response to an output signal of the second edge detection circuit. A second flip-flop for supplying a signal of the other level to the second output terminal in response to a reset signal, the second flip-flop supplying the signal to the second output terminal of the phase comparison circuit, and the first and second flip-flops; Has a reset circuit output level of the flop outputs said reset signal in the case of the one level, and a delay circuit delay time is variable for delaying the reset signal.

In the phase locked loop circuit of the present invention, preferably, the delay time of the delay circuit is set to a value that minimizes a noise component in the first signal.

In the phase locked loop circuit according to the present invention, preferably, the reset circuit calculates a logical sum of an inverted output signal of the first flip-flop and an inverted output signal of the second flip-flop. An OR circuit; and a first inverting circuit that supplies a signal obtained by inverting an output signal of the OR circuit as the reset signal to reset terminals of the first and second flip-flops.

In the phase comparison circuit of the present invention and the phase locked loop circuit of the present invention, since the delay circuit for delaying the reset signal is variable, the output signals of the first and second flip-flops are provided. Is variable from one level to being reset to the other level.

[0035]

FIG. 1 is a circuit diagram showing an embodiment of a PLL circuit according to the present invention. This PLL circuit includes a phase comparison circuit 200 that outputs a signal corresponding to the phase difference between the first signal and the second signal, and a level corresponding to the signals S _up and S _dw output from the phase comparison circuit 200. A voltage generation circuit for generating a voltage signal; a frequency generation circuit for outputting a signal S _osc having a frequency corresponding to the voltage signal of the voltage generation circuit to the phase comparison circuit 200 as the first signal; a reference frequency generation circuit that outputs _ref as the second signal to the phase comparison circuit 200.

The voltage generating circuit includes a capacitor C ₀ and a charge pump circuit 120 for controlling charging and discharging of the capacitor C ₀ . The frequency generation circuit includes a voltage control generation circuit 140 and the voltage control generation circuit 1.
A first frequency dividing circuit 15 which supplies a frequency-divided signal obtained by dividing the output signal of the forty signal 40 to the phase comparison circuit 200 as the first signal.
0. The reference frequency generation circuit includes a reference oscillation circuit 110, a second frequency division circuit 160 that supplies a frequency-divided signal obtained by dividing the output signal of the reference oscillation circuit 110 to the phase comparison circuit 200 as the second signal, It consists of.

The reference oscillation circuit 110 generates a reference oscillation signal having a frequency f ₀ . This reference oscillation signal is frequency-divided by N by the frequency divider 160, and the frequency- _divided signal is input to the phase comparator 200 as the reference signal _Sref . On the other hand, the oscillation signal from the voltage controlled oscillation circuit 140 is divided by M by the frequency dividing circuit 150, and the divided signal is input to the phase comparison circuit 200 as the oscillation signal S _osc .

The phase comparison circuit 200 generates an up signal S _up and a down signal S _dw having a predetermined pulse width according to the phase difference between the input oscillation signal S _osc and the reference signal S _ref.
Is generated and input to the charge pump circuit 120. The charge pump circuit 120 charges or discharges the capacitor C ₀ according to the up signal S _up and the down signal S _dw from the phase comparison circuit 200, and controls the level of the output voltage V ₀ .

The output voltage V ₀ of the charge pump circuit 120
The high-frequency noise is removed by the low-pass filter 130, and only the low-frequency component is output to the voltage-controlled oscillation circuit 140 as a control signal. Voltage controlled oscillator 140, the frequency f _s of the oscillating signal is controlled according to the voltage level of the input signal. After the oscillation signal is M division is input to the frequency divider 150, as an oscillation signal S _osc, the phase comparator circuit 200
Is input to

In this PLL circuit, the frequency dividing circuit 150
Is controlled so that the phase of the oscillation signal S _osc from the clock signal always follows the reference signal S _ref from the frequency divider 160, so that the frequency of the oscillation signal S _osc and the frequency of the reference signal S _ref are controlled to match. Therefore, the frequency f _s of the oscillation signal from the voltage controlled oscillation circuit 140 is obtained by the following equation. f _s = f ₀ · M / N Here, M and N are division ratios of the frequency dividing circuits 150 and 160, respectively.

FIG. 2 is a circuit diagram of the phase comparison circuit according to the present invention, and is a circuit diagram of the phase comparison circuit 200 of FIG. The phase comparison circuit 200 includes the edge detection circuits 10a, 1
0b, RS flip-flops 30a, 30b, AND circuits AND3, AND4, inverting circuits INV3, INV
4, INV5, OR circuit OR1, and delay circuit D
L.

The edge detecting circuit 10a includes an inverting circuit INV
1 and an AND circuit AND1. The edge detection circuit 10b includes an inversion circuit INV2 and an AND circuit AN.
D2. In the edge detection circuit 10a, the input terminal of the inverter circuit INV1 is connected to the terminal T _1, the output terminal is connected to one input terminal of the AND circuit AND1. The other input terminal of the AND circuit AND1 is connected to the terminal T _1. The output terminal of the AND circuit AND1 is connected to one input terminal of the AND circuit AND3, and the other input terminal of the AND circuit AND3 is connected to the output terminal of the inverting circuit INV3. Inverting circuit INV
3 is connected to the output terminal of the inverting circuit INV5 via the delay circuit DL. In the edge detection circuit 10b, an input terminal of the inverter circuit INV2 is connected to the terminal T _2, the output terminal is connected to one input terminal of the AND circuit AND2. The other input terminal of the AND circuit AND2 is connected to the terminal T _2. AND circuit AND2
Is connected to one input terminal of the AND circuit AND4, and the other input terminal of the AND circuit AND4 is connected to the output terminal of the inverting circuit INV4. Inverting circuit IN
The input terminal of V4 is connected to the output terminal of the inverting circuit INV5 via the delay circuit DL.

The input terminal of the inversion circuit INV5 is connected to the output terminal of the OR circuit OR1, and the input terminals of the OR circuit OR1 are connected to the RS flip-flops 30a and 30a, respectively.
b is connected to the inverted output terminal Qz. OR circuit O
A reset circuit is constituted by R1 and the inverting circuit INV5. By the output signal of the reset circuit, R
The S flip-flops 30a and 30b are reset.
This reset circuit is equivalent to a NOR circuit.

The edge detecting circuit 10a detects the rising edge of the reference signal S _ref input to the input terminal T _1, and inputs the detection result to one input terminal of the AND circuit AND3. The other input terminal of the AND circuit AND3 has
The output signal of the inverting circuit INV3 is input. The output signal of the AND circuit AND3 is input to the input terminal S of the RS flip-flop 30a. Edge detecting circuit 10b detects the rising edge of the oscillation signal S _OSC input to the input terminal T _2, and inputs the detection result to one input terminal of the AND circuit AND4. The output signal of the inverting circuit INV4 is input to the other input terminal of the AND circuit AND4. The output signal of the AND circuit AND4 is RS flip-flop 3
0b is input to the input terminal S.

In the initial state, the RS flip-flops 30a and 30b are both set to the reset state. That is, since the output terminals Q of the RS flip-flops 30a and 30b are held at the low level and the inverted output terminal Qz is held at the high level, the output terminal of the OR circuit OR1 is held at the high level. In response, the output terminals of the inverting circuits INV3 and INV4 are both held at a high level, so that the output signals of the AND circuits AND3 and AND4 are set by the output signals of the edge detection circuits 10a and 10b, respectively.

FIG. 3 is a waveform diagram showing the operation of the phase comparison circuit 200. Hereinafter, the phase comparison operation will be described with reference to FIGS. FIG. 3 shows three sections A, B, and C. In the section A, the oscillation signal S _osc has a phase advanced from the reference signal S _ref , in the section B, the phase of the oscillation signal S _osc matches the phase of the reference signal S _ref , and in the section C, the oscillation signal S _osc is The phase is behind the reference signal _Sref . Hereinafter, the operation of the phase comparison circuit 200 in each section will be described.

First, in the section A, when the phase of the oscillation signal S _osc is advanced from the reference signal S _ref , the pulse signal S _o is output by the edge detection circuit 10b in accordance with the rising edge of the oscillation signal S _osc . after the pulse signal S _r in response to the rising edge of the reference signal S _ref by the edge detection circuit 10a is output. The RS flip-flops 30b, 30b,
30a are sequentially set. RS flip-flop 30
When b and 30a are both set, the output signal level of the OR circuit OR1 is inverted, and the RS flip-flops 30a and 30b are reset accordingly.

More specifically, for example, at the rising edge of the oscillation signal S _OSC , a positive pulse signal _So having a predetermined width is output from the output terminal of the edge detection circuit 10b. The width of the pulse signal S _o is determined by the delay time of the inverter circuit INV2 constituting the edge detection circuit 10b. Since the output signal of the inversion circuit INV4 is held at a high level, the output signal of the AND circuit AND4 is the same as the output signal of the edge detection circuit 10b. Therefore, RS flip-flop 30b is set by the pulse signal S _o from the edge detection circuit 10b. That is, the output terminal Q of the RS flip-flop 30b is switched from low level to high level, and its inverted output terminal Qz is switched from high level to low level. That is, the down signal S _dw is held at the high level. In addition,
At this time, since the state of the RS flip-flop 30a has not changed, the output signal of the OR circuit OR1 does not change and remains at the high level.

Next, at the rising edge of the reference signal S _ref, the output terminal of the edge detection circuit 10a, a positive pulse signal S _r with a predetermined width is outputted. The width of the pulse signal S _r is determined by the delay time of the inverter circuit INV1 which constitutes the edge detection circuit 10a.
Since the output signal of the inversion circuit INV3 is held at the high level, the output signal of the AND circuit AND3 is the same as the output signal of the edge detection circuit 10a. Therefore, RS flip-flop 30a by the pulse signal S _r from the edge detection circuit 10a is set, RS output terminal Q of the flip-flop 30a is switched from the low level to the high level, a low inverted output terminal Qz from the high level Switch to level. That is, the up signal S _up is also held at the high level.

When the state of the RS flip-flop 30a changes, both input signals of the OR circuit OR1 become low level, and the output signal of the OR circuit OR1 switches from high level to low level. In response, the output signal of the inverting circuit INV5 switches from low level to high level. In response to the rising edge of the output signal of the inverting circuit INV5, both the RS flip-flops 30a and 30b are reset, and both the up signal S _up and the down signal S _dw are switched from high level to low level.

As described above, the oscillation signal S _osc becomes the reference signal S
_{When the} phase is ahead of _ref , first the oscillation signal S _osc
The down signal S _dw rises in response to the rising edge of, and the up signal S _up also rises in response to the rising edge of the reference signal _Sref . After that, both the down signal S _dw and the up signal S _up are reset. Therefore, the width of the up signal S _up is set by the delay time of the reset circuit and the reset time of the RS flip-flop 30a (the time required from the input of the reset signal until the reset state is determined). The width of the down signal S _dw is wider than the width of the up signal S _up by an amount corresponding to the phase difference between the oscillation signal S _osc and the reference signal S _ref .

Next, in the section B, the oscillation signal S _osc
And the phase of the reference signal S _ref almost coincide with each other. In this case, the edge detection circuit 10a and 10b outputs substantially simultaneously pulse signal S _r and S _o. In response, RS
The flip-flops 30a and 30b are set almost simultaneously. Then, at the rising edge of the output signal of the reset circuit, both the RS flip-flops 30a and 30b are reset. Therefore, when the phases of the oscillation signal S _osc and the reference signal S _ref match, an up signal S _up and a down signal S _dw having the same width are obtained.

In the section C, the phase of the oscillation signal S _osc lags behind that of the reference signal S _ref.
The RS flip-flop 30a is set according to the rising edge of _ref , and the up signal S _up signal is held at a high level. Then, the RS flip-flop 30b is set according to the rising edge of the oscillation signal S _osc , and the down signal S _dw is also held at a high level. Then, at the rising edge of the output signal of the reset circuit, both the RS flip-flops 30a and 30b are reset. Therefore, the width of the down signal S _dw depends on the delay time of the reset circuit and the RS flip-flop 30b.
The width of the up signal S _up is wider than the width of the down signal S _dw by an amount corresponding to the phase difference between the reference signal S _ref and the oscillation signal S _osc .

The pulse width ΔT of the up signal S _{up in} the section A is the minimum pulse width, the pulse width ΔT of the up signal S _up and the down signal S _{dw in} the section B is the minimum pulse width, and the section C is the minimum pulse width.
The pulse width ΔT of the down signal S _dw is the minimum pulse width and the same width.

FIG. 4 shows an ECL (emitter coupling logic).
3 shows a circuit example of an RS flip-flop 30 formed by a circuit. Hereinafter, RS will be described with reference to this circuit diagram.
The structure and operation of the flip-flop will be described.

The RS flip-flop 30 has a resistance element R
31, R32, npn transistors Q31, Q32, Q
33, Q34, Q35, Q36, Q37 and current source I
S31 and IS32. Further, the transistor Q37 is a dual-emitter transistor as shown.

The emitters of transistors Q31 and Q32 are connected to each other, and the collectors are connected to resistance elements R31 and R31, respectively.
32, it is connected to the supply line of the power supply voltage V _CC . The base of the transistor Q31 is the transistor Q32
And the base of the transistor Q32 is connected to the collector of the transistor Q31. The collector of the transistor Q31 is the RS flip-flop 30
, And the collector of the transistor Q32 is connected to the output terminal Q of the RS flip-flop 30.

The emitters of transistors Q33 and Q34 are connected to each other, the base of transistor Q33 is connected to the input terminal of set signal S, and the collector is connected to transistor Q33.
It is connected to 31 collectors. Transistor Q34
Is connected to the input terminal of the inverted signal SX of the set signal S, and the collector is connected to the connection point between the emitters of the transistors Q31 and Q32. Further, a current source IS31 is connected to a connection point between the emitters of the transistors Q33 and Q34. The base of the transistor Q37 is connected to the input terminal of the reset signal R, the collector is connected to the collector of the transistor Q32, and the two emitters are both connected to the connection point between the emitters of the transistors Q33 and Q34.

The emitters of the transistors Q35 and Q36 are connected to each other, and the connection point is connected to the current source IS32. The base of the transistor Q35 is connected to the input terminal of the inverted signal RX of the reset signal R, and the collector is connected to the connection point between the emitters of the transistors Q31 and Q32. The base of the transistor Q36 has the reset signal R
Of the transistor Q32
Connected to the collector.

In the RS flip-flop 30 configured as described above, the output terminal Q and the inverted output terminal Qz according to the set signal S and the reset signal R input.
Is set.

This RS flip-flop (RSFF) 3
The truth table of 0 is as shown in FIG. Note that FIG.
, “L” indicates a low level, and “H” indicates a high level. When the input signals S and R are both at the low level, the state immediately before the RS flip-flop is held. When the set signal S is at the low level and the reset signal R is at the high level, the output terminal Q of the RS flip-flop is held at the low level, and the inverted output terminal Q
z is held at a high level. When the set signal S is at a high level and the reset signal R is at a low level, the output terminal Q of the RS flip-flop is at a high level and the inverted output terminal Qz
Are held low. When both the set signal S and the reset signal R are at a high level, the output terminal Q is kept at a low level, and the inverted output terminal Qz is kept at a high level.

As shown in the circuit of FIG. 4, when the set signal S and the reset signal R are both at the low level, the inverted signals SX and RX of these signals are both held at the high level. In this case, transistors Q34 and Q35 are kept on, and transistors Q33, Q36 and Q3
7 is kept off. Therefore, the transistor Q
31 and Q32 constitute a latch circuit, and the latch circuit makes use of the output terminal Q and the inverted output terminal Qz.
Is latched, and the state of the RS flip-flop is held as it is.

When the set signal S is at low level and the reset signal R is at high level, the inverted signal SX is at high level and R
X is held at a low level. In this case, the transistors Q33 and Q35 are kept off, and the transistors Q37, Q34 and Q36 are kept on. Therefore, a current flows through the resistance element R32, and the output terminal Q is kept at a low level. Further, since the potential of the output terminal Q is applied to the base of the transistor Q31, the transistor Q31 is off, and the inverted output terminal Qz is kept at a high level.

Next, when the set signal S is at the high level and the reset signal R is at the low level, the inverted signal SX is held at the low level and RX is held at the high level. In this case, transistors Q33 and Q35 are kept on, and transistors Q37, Q34 and Q36 are kept off. Therefore, a current flows through the resistance element R31, and the inverted output terminal Qz is kept at a low level. Further, since the potential of the output terminal Q is applied to the base of the transistor Q32, the transistor Q32 is off, and the output terminal Q is kept at a high level.

When both the set signal S and the reset signal R are held at a high level, the inverted signals SX and RX are both held at a low level. In this case, transistors Q37, Q33 and Q36 are kept on, and transistors Q34 and Q35 are kept off. Therefore, the transistors Q37 and Q36 in the ON state are connected to the output terminal Q, and the inverted output terminal Qz is
Only the transistor Q33 in the ON state is connected. As described above, the transistor Q37 is a dual-emitter transistor, and both emitters are connected to the current source IS31, so that the current driving capability is higher than that of the transistor Q33. Therefore, the current of the current source IS31 flows through the transistor Q37, and almost no current flows through the transistor Q33. As a result, the current driving capability on the output terminal Q side is stronger than that on the inverted output terminal Qz side, the output terminal Q is held at a low level, and the inverted output terminal Qz is held at a high level.

The transistor Q37 is not limited to a dual-emitter transistor.
It is also possible to use transistors larger in size than transistors Q33 and Q34.

As described above, the output state of the RS flip-flop 30 shown in FIG. 4 is set according to the truth table shown in FIG. Further, the level change of the set signal S and the reset signal R, which are the input signals, is caused by the output terminal Q or the inverted output terminal Qz via only one stage of the transistor.
, The set or reset time from the signal input until the output state of the RS flip-flop is determined is short, and the delay time of the RS flip-flop is short. This RS flip-flop 30 is connected to the R
Used for the S flip-flops 30a and 30b.

As described above, according to the phase comparison circuit of the present embodiment, the rising edges of the reference signal _Sref and the oscillation signal _Sosc are detected by the edge detection circuits 10a and 10b, and the detection result is configured by the ECL circuit. R
Input to S flip-flops 30a and 30b to set the states of these flip-flops. According to the state of the RS flip-flops 30a and 30b, the OR circuit OR
1 and an inverting circuit INV5, a reset signal is generated, and the RS flip-flops 30a and 30b are set to a reset state by the reset signal. Therefore, the phase difference between the reference signal _Sref and the oscillation signal _Sosc is reduced. Accordingly, an up signal S _up and a down signal S _dw having a predetermined pulse width can be generated by the RS flip-flops 30a and 30b.

FIG. 5 is a circuit diagram showing one configuration example of the edge detection circuit 10. As shown in FIG. The edge detection circuit 10 includes resistance elements R11, R12, R13, R14, npn transistors Q11, Q12, Q13, Q14, Q15, Q16,
Q17, Q18 and current sources IS11, IS12, IS
13, IS14.

The emitters of the transistors Q11 and Q12 are connected to each other, and the connection point is connected to the current source IS11. Inverted signal / S _IN base of the input signal S _IN of the transistor Q11 (hereinafter, the sign of the inverted signal. Indicating put at the head of the "/") is connected to the terminal of the power supply voltage V collector through a resistor R11 Connected to _CC supply line. The base of the transistor Q12 is connected to the terminal of the input signal S _IN , and the collector is connected to the supply line of the power supply voltage V _CC via the resistor R12. In this way, the transistors Q11 and Q12, the resistance elements R11 and R12, and the current source IS11 form an inversion circuit INV1.

The emitters of the transistors Q13 and Q14 are connected to each other, and the connection point is connected to the collector of the transistor Q15. The base of transistor Q13 is connected to the collector of transistor Q12, and the collector is connected to power supply voltage V _CC via resistor R13. The base of the transistor Q14 is the transistor Q11
, And the collector is connected to the supply line of the power supply voltage V _CC via the resistance element R14. The emitters of the transistors Q15 and Q16 are connected to each other, and the connection point is connected to the current source IS12. The base of the transistor Q15 is connected to the terminal of the input signal S _IN , and the base of the transistor Q16 is connected to the terminal of the inverted input signal / S _IN . Further, the collector of the transistor Q16 is connected to the collector of the transistor Q14.
Thus, the transistors Q13, Q14, Q15, Q
16, an AND circuit AND1 is constituted by the resistance elements R13 and R14 and the current source IS12.

The base of transistor Q17 is connected to the collector of transistor Q14, and the collector is connected to power supply voltage V
_It is connected to the _CC supply line, and the emitter is connected to the current source IS13. The base of transistor Q18 is connected to the collector of transistor Q13, the collector is connected to the supply line of power supply voltage V _CC , and the emitter is connected to current source IS14. Transistor Q17, current source IS13
, Transistor Q18 and current source IS14 form an emitter follower, respectively.
7, a signal corresponding to the collector potential of transistors Q14 and Q13 is output from the emitters of Q18.

[0073] the input signal S _IN, for example, when a square wave having a constant width as shown in FIG. 5, the input signal S _IN
, The transistor Q15 is turned on and the transistor Q16 is turned off. Immediately before the rising edge of the input signal S _IN , the transistor Q13 is turned on and the transistor Q14 is turned on.
Are held in the OFF state, the emitter of the transistor Q17 is held at a high level, and the emitter of the transistor Q18 is held at a low level.

At the rising edge of the input signal S _IN , both the states of the transistors Q11 and Q12 change. The transistor Q11 switches from the on state to the off state, and the transistor Q12 switches from the off state to the on state. Accordingly, the collector of the transistor Q11 switches from low level to high level, and the collector of the transistor Q12 switches from high level to low level. This state change occurs after a lapse of a predetermined delay time Δt ₁ from the rising edge of the input signal S _IN .
Is determined.

With the change in the state of the transistors Q11 and Q12, the state of the transistors Q13 and Q14 also changes.
That is, the transistor Q13 changes from the on state to the off state, and the transistor Q14 changes from the off state to the on state. Accordingly, the emitter of the transistor Q17 also switches from the high level to the low level. in this way,
From the rising edge of the input signal S _IN , a pulse signal S _OUT having a certain width is output from the emitter of the transistor Q17. Incidentally, the inverted signal / S _OUT of the pulse signal S _OUT from the emitter of the transistor Q18 is output.

FIG. 6 shows the edge detection circuit shown in FIG.
3 is a circuit diagram illustrating an example of a phase comparison circuit including an RS flip-flop, a delay circuit DL, a reset circuit 40, and an output circuit 50 illustrated in FIG. As shown, the edge detection circuits 10a, 10a constituting the phase comparison circuit
b has the same configuration as that of the edge detection circuit 10 shown in FIG. 5, and R is a component of the RS flip-flops 30a and 30b.
The S flip-flop has the same configuration as the RS flip-flop 30 shown in FIG.

In the reset circuit 40, the base of the transistor Q50 is connected to the inverted output terminal Qz of the RS flip-flop 30a, the collector is connected to the supply line of the power supply voltage V _CC , and the emitter is connected to the current source IS50. The base of the transistor Q51 is connected to the output terminal Q of the RS flip-flop 30a, a collector connected to the supply line of the power supply voltage V _CC, an emitter current source IS51
It is connected to the.

The emitters of the transistors Q52 and Q53 are connected to each other, and the connection point is connected to the current source IS52. The base of the transistor Q52 is the transistor Q
50, the collector of which is connected to the resistor R51.
_Is connected to the supply line of the power supply voltage V _CC via the. The base of the transistor Q53 is connected to the voltage source VS1, and the collector is connected to the supply line of the power supply voltage V _CC via the resistor R52.

The base of transistor Q54 is connected to the collector of transistor Q52, and the collector is connected to power supply voltage V
_The transistor Q54 and the current source IS5 are connected to the _CC supply line, and the emitter is connected to the current source IS53.
Reference numeral 3 denotes a buffer circuit comprising an emitter follower, which outputs a signal based on the collector voltage of the transistor Q52 to the emitter of the transistor Q54. Transistor Q
55 based is connected to the collector of the transistor Q53, a collector is connected to the supply line of the power supply voltage V _CC, an emitter is connected to a current source IS54, the transistors Q55 and a current source IS54 is a buffer circuit composed of an emitter follower It outputs a signal based on the collector voltage of the transistor Q53 to the emitter of the transistor Q55.

As described above, the transistor Q50 and the current source IS50 constitute an emitter follower, and a signal corresponding to the level of the inverted output terminal Qz of the RS flip-flop 30a is output to the emitter of the transistor Q50. Constitutes an emitter follower, and outputs a signal corresponding to the level of the output terminal Q of the RS flip-flop 30a to the emitter of the transistor Q51. As shown, the emitter of the transistor Q51 is connected to the output terminal of the up signal S _{Stay up-.}

In output circuit 60, transistor Q6
The base of 0 is connected to the inverted output terminal Qz of the RS flip-flop 30b, the collector is connected to the supply line of the power supply voltage V _CC , and the emitter is connected to the current source IS60. The base of the transistor Q61 is connected to the output terminal Q of the RS flip-flop 30b, the collector is connected to the supply line of the power supply voltage V _CC , and the emitter is connected to the current source IS61.

An emitter follower is formed by the transistor Q60 and the current source IS60, and outputs a signal corresponding to the level of the inverted output terminal Qz of the RS flip-flop 30b to the emitter of the transistor Q60. Transistor Q
61, an emitter follower is constituted by the current source IS61, and outputs a signal corresponding to the level of the output terminal Q of the RS flip-flop 30b to the emitter of the transistor Q61. As shown, the emitter of the transistor Q61 is connected to the output terminal of the down signal S _dw .

The emitters of transistors Q50 and Q60 are both connected to the base of transistor Q52. Therefore, when the output signal level of any one of the transistors Q50 and Q60 becomes higher than the voltage of the voltage source VS1, the transistor Q52 is turned on in the differential circuit formed by the transistors Q52 and Q53.
The transistor Q53 is turned off. In response,
The collector of the transistor Q52 is kept at a low level, and the collector of the transistor Q53 is kept at a high level. In other cases, that is, the transistor Q
When the output signal levels of the emitters of 50 and Q60 are both lower than the voltage of voltage source VS1, transistor Q5
2 is kept in the off state and the transistor Q53 is kept in the on state, so that the collector of the transistor Q52 is kept at the high level and the collector of the transistor Q53 is kept at the low level.

As described above, the transistors Q52 and Q53
Constitute a logical sum (OR) circuit for calculating the logical sum of the output signals of the emitters of the transistors Q50 and Q60. That is,
The reset circuit 40 allows the RS flip-flop 30
The logical sum of the output signals from the inverted output terminals Qz of a and 30b is obtained. The inverted signal of the logical sum signal and the logical sum signal are referred to as a reset signal S _rst and an inverted signal / S _rst of the reset signal, respectively, as the RS flip-flop 30.
a and 30b. At the rising edge of the reset signal _Srst , the RS flip-flops 30a, 30
0b is reset.

FIG. 6 shows a specific circuit configuration example of the phase comparison circuit. The operation of the phase comparison circuit shown in FIG. 6 is substantially the same as that of the phase comparison circuit shown in FIG. As shown, the edge detection circuit 10a supplies the reference signal S
_ref and its inverted signal / S _ref are input. The rising edge of the reference signal _Sref is detected by the edge detection circuit 10a, and a pulse signal _Sr having a constant width and its inverted signal / _Sr are generated in response to the detection, and are input to the RS flip-flop 30a. RS flip-flop 30a, the pulse signal S _r and is set by an inverted signal / S _r output terminal Q is input to the high level, the inverted output terminal Qz are respectively set to the low level.

The oscillation signal S _osc and its inverted signal / S _osc are input to the edge detection circuit 10b. The rising edge of the oscillation signal S _osc is detected by the edge detection circuit 10b, and the pulse signal S having a certain width is accordingly detected.
_o and its inverted signal / S _o are generated and input to the RS flip-flop 30b. RS flip-flop 3
0b, the pulse signals S _o and the set output terminal Q by an inverted signal / S _o is inputted to the high level, the inverted output terminal Qz are respectively set to the low level.

When the RS flip-flops 30a and 30b are both set, the inverted output terminals Qz of these flip-flops are both set to low level. In response, the reset circuit 40 operates, and the reset signal S
_rst and its inverted signal / S _rst are generated. In response to the reset signal, the RS flip-flops 30a, 30b
Are reset together.

By the phase comparator thus configured, an up signal S _up and a down signal S _dw having a predetermined width are generated and output according to the phase difference between the oscillation signal S _osc and the reference signal S _ref. You. In accordance with the up signal S _up and the down signal S _dw , for example, the frequency of the oscillation signal S _osc of the voltage controlled oscillation circuit (VCO) of the PLL circuit is controlled. Further, in the phase comparison circuit of this example, R
The number of gates through which signals pass through the S flip-flops 30a and 30b and the reset circuit 40 is small, and the signal delay time is short. On the other hand, since the reset signal is delayed by a predetermined time using the delay circuit DL having a variable delay time for delaying the reset signal, the up signal S _up and the down signal S _dw
Can be set to various values.

The delay circuit DL includes an npn transistor Q7
0, and Q71, and the voltage source E _0, the variable voltage supply circuit 60
, A resistance element R70, and current sources I ₀ and I ₁ .
The collector of the transistor Q70 is connected to the collector of the transistor Q52, the base of the transistor Q70 is connected to the output terminal of the variable voltage supply circuit 60, the emitter of the transistor Q70 is connected to a current source I _0. The collector of the transistor Q71 is connected to the collector of the transistor Q53, the base of the transistor Q71 is connected to a voltage source E _0, the emitter of the transistor Q71 is connected to a current source I _1. The magnitudes of the drive currents of the current sources I ₀ and I ₁ are equal. The emitters of the transistors Q70 and Q71 are connected via a resistor R70. By configuring the delay circuit DL in this way, several nS
A delay circuit having a delay time of about to several tens nS can be incorporated with a simple configuration.

The reset signal output to the collector of transistor Q52 is delayed by delay circuit DL, and a delayed reset signal _Srst is output from the emitter of transistor Q54. Reset signal outputted to the collector of the transistor Q53 is delayed by the delay circuit DL, the inverted signal / S _rst of the delayed reset signal is output from the emitter of the transistor Q55.

FIG. 7 is an explanatory diagram for explaining the operation of the delay circuit DL of FIG. 7, the voltage source △ E and the voltage source E ₁ connected in series to constitute a variable voltage supply circuit. The output voltage of the voltage source E ₁ and the voltage source E ₀ is equal. 7, the same components as those in FIG. 6 are denoted by the same reference numerals. Symbol CP is a comparator. FIG. 8 shows signal waveforms at points X, Y, Z, and W in the explanatory diagram of FIG.

FIG. 8A shows a signal waveform when the output voltage of voltage source ΔE is small. In FIG. 8A, when a signal that changes from the high level to the low level at time t1 is input to the point X, the transistors Q52 and Q52 of the differential pair
By Q53, the signal gradually changes from the high level to the low level at the point Y, and gradually changes from the low level to the high level at the point Z. The falling characteristics of the signal at the point Y include the capacitance between the resistance element R51 and the collector and base of the transistor Q52, the voltage source ΔE and the voltage source E _1.
Depends on the magnitude of the output voltage. Rising characteristics of the signal Z point is dependent on the magnitude of the capacitance and the voltage source output voltage E ₀ of the collector-base resistance element R52 and a transistor Q53. At time t2 when the potential at point Y and the potential at point Z match, the potential at point W changes from high level to low level. The time from time t1 to time t2 is △ Td
And

FIG. 8B shows a signal waveform when the output voltage of voltage source ΔE is large. In FIG. 8B, when a signal that changes from the high level to the low level at time t1 is input to the point X, the transistors Q52 and Q52 of the differential pair
By Q53, the signal gradually changes from the high level to the low level at the point Y, and gradually changes from the low level to the high level at the point Z. The falling characteristics of the signal at the point Y include the capacitance between the resistance element R51 and the collector and base of the transistor Q52, the voltage source ΔE and the voltage source E _1.
Depends on the magnitude of the output voltage. Rising characteristics of the signal Z point is dependent on the magnitude of the capacitance and the voltage source output voltage E ₀ of the collector-base resistance element R52 and a transistor Q53. At time t3 when the potential at point Y and the potential at point Z match, the potential at point W changes from high level to low level. The time from time t1 to time t3 is △ Td
And

By increasing the output voltage of voltage source ΔE, time ΔTd can be increased, and delay circuit DL
Delay time can be increased. In addition, the voltage source
By changing the output voltage of E, the time ΔTd can be changed, and the delay time of the delay circuit DL can be changed. Therefore, the delay time of the delay circuit DL can be set so as to minimize the noise component in the output signal of the PLL circuit using the delay time of the delay circuit DL. For example, the output signal of the PLL circuit may be analyzed by the frequency analysis circuit, and the output voltage of the voltage source ΔE may be adjusted and set so that the noise component is minimized.

FIG. 9 is an example of the variable voltage supply circuit 60 in FIG. The variable voltage supply circuit 60 includes a voltage source E ₁ ,.
E, a plurality of voltage dividing resistors R111 to R115 connected in series to both terminals of the voltage source #E, a selection circuit 101, and a designation unit 65. The output voltage of the voltage source E ₁ is 6
And the output voltage of the voltage source E ₀ . Connection point of voltage dividing resistors R111 and R112, connection point of voltage dividing resistors R112 and R113, connection point of voltage dividing resistors R113 and R114, voltage dividing resistor R
The input terminals A1, A2, A3, and A4 of the selection circuit 101 are connected to the connection point of 114 and R115, respectively. The control signal from the specifying means 65 is supplied to the control terminal B0 of the selection circuit 101. The output terminal A0 of the selection circuit 101 is connected to the base of the transistor Q70 in FIG.

The selection circuit 101 connects any one of the input terminals A1 to A4 to the output terminal A0 based on a control signal from the specifying means 65. The base of the transistor Q70 is the sum voltage of a voltage source △ output voltage of the output voltage divided voltage source E ₁ of E supplied. The specifying means 65 may be configured using a memory, or may be configured using a plurality of switches or DIP switches that supply digital signals. The input terminal that minimizes the noise component in the output signal of the PLL circuit among the input terminals A1 to A4 is inspected in advance, and the information of the control signal for selecting the input terminal is stored in the specifying unit 65. Then, the control circuit 101 causes the selection circuit 101 to select an input terminal having the minimum noise component in the output signal of the PLL circuit among the input terminals A1 to A4 according to the control signal from the specifying unit 65.

FIG. 10 is an example of the variable voltage supply circuit 60 of the delay circuit DL in FIG. Variable voltage supply circuit 60
It is provided with a selection circuit 101 and a plurality of voltage dividing resistors R101~R105 connected in series to both terminals of the voltage source E ₂ Toko designating means 65. Connection point between voltage dividing resistors R101 and R102, connection point between voltage dividing resistors R102 and R103, connection point between voltage dividing resistors R103 and R104, and voltage dividing resistors R104 and R1
05 are connected to the input terminals A1 and A1 of the selection circuit 101.
2, A3 and A4 are connected respectively. Selection circuit 101
Is supplied with a control signal from the specifying means 65. The output terminal A0 of the selection circuit 101 is
Of the transistor Q70.

The selection circuit 101 connects any one of the input terminals A1 to A4 to the output terminal A0 based on the control signal from the specifying means 65. The base of the transistor Q70, a voltage obtained by dividing the output voltage of the voltage source E ₂ minute is supplied. The specifying unit 65 may be configured using a memory, or may be configured using a plurality of switches or DIP switches. PLL among input terminals A1 to A4 in advance
The input terminal having the minimum noise component in the output signal of the circuit is inspected, and the information of the control signal for selecting the input terminal is stored in the specifying means 65. Then, the designation means 65
Of the input terminals A1 to A4
The selection circuit 101 selects an input terminal that minimizes a noise component in the output signal of the LL circuit.

The number of voltage dividing resistors may be five or more, and accordingly, the number of input terminals of the selection circuit 101 may be four or more. 6, the transistor Q54 and the current source IS53, which are buffer circuits, and the transistor Q55 and the current source IS54, which are buffer circuits.
May be provided separately from the reset circuit 40. FIG.
With respect to the phase comparison circuit described above, the transistor Q54 and the current source IS53 as a buffer circuit and the transistor Q55 and the current source IS54 as a buffer circuit may be incorporated in the delay circuit DL. The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

[0100]

According to the phase comparator of the present invention, the minimum pulse width of the phase difference signal output from the phase comparator is variable.
It can be set to various values. In the PLL circuit of the present invention, the minimum pulse width of the phase difference signal output from the phase comparison circuit of the PLL circuit is variable and can be set to various values. According to the PLL circuit of the present invention, the noise component in the output signal of the PLL circuit can be reduced by using the delay time of the delay circuit.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a PLL circuit according to the present invention.

FIG. 2 is a circuit diagram of a phase comparison circuit according to the present invention.

FIG. 3 is a waveform diagram illustrating an operation of the phase comparison circuit.

FIG. 4 is a circuit diagram illustrating a configuration example of an RS flip-flop.

FIG. 5 is a circuit diagram illustrating a configuration example of an edge detection circuit;

FIG. 6 is a circuit diagram illustrating a configuration example of a phase comparison circuit.

FIG. 7 is an explanatory diagram illustrating an operation of the phase comparison circuit in FIG. 6;

FIG. 8 is a waveform chart showing waveforms at respective points in the explanatory diagram of FIG. 7;

9 is a circuit diagram illustrating a configuration example of a variable voltage supply circuit 60 in FIG.

FIG. 10 is a circuit diagram showing one configuration example of a variable voltage supply circuit 60 in FIG. 6;

FIG. 11 is a circuit diagram illustrating an example of a phase comparison circuit.

FIG. 12 is a diagram showing an equivalent circuit of a NAND circuit.

FIG. 13 is a circuit diagram illustrating a configuration example of a NAND circuit.

FIG. 14 is a diagram showing an equivalent circuit of an RS flip-flop configured by a NAND circuit.

FIG. 15 is a circuit diagram illustrating a configuration example of an RS flip-flop.

FIG. 16 is a schematic block diagram of a conventional PLL circuit.

FIG. 17 is a waveform diagram illustrating an operation of the phase comparison circuit.

FIG. 18 is a diagram illustrating noise characteristics of a PLL circuit.

FIG. 19 is a diagram illustrating a truth table of an RS flip-flop;

[Explanation of symbols]

2 ... Nand circuit (NAND circuit), 10, 10a, 10
b: Edge detection circuit, 20a, 20b, 30, 30a,
30b RS flip-flop, 40 reset circuit,
50 output circuit, 60 variable voltage supply circuit, 65 designating means, 100, 200 phase comparison circuit, 101 selection circuit, 110 reference oscillation circuit, 120 charge pump circuit, 130 low-pass filter, 140 voltage Control oscillation circuit, 150, 160 ... frequency divider circuit, C ₀ ... capacitor,
DL: delay circuit, GND: ground potential (earth potential), V
_CC : Power supply voltage, ΔT: Minimum pulse width.

Claims (10)

[Claims] 1. A phase comparison circuit for outputting a signal corresponding to a phase difference between a first signal and a second signal, comprising: a first edge detection circuit for detecting a rising edge of the first signal; A second edge detection circuit for detecting a rising edge of the second signal; and a signal of one level supplied to a first output terminal of the phase comparison circuit in accordance with an output signal of the first edge detection circuit. A first flip-flop for supplying a signal of the other level to the first output terminal in response to a reset signal; and a signal of one level in response to an output signal of the second edge detection circuit, A second flip-flop that supplies a second output terminal of the comparison circuit and supplies a signal of the other level to the second output terminal in response to a reset signal; and outputs of the first and second flip-flops level Phase comparison circuit having a reset circuit for outputting said reset signal when said one of the levels, a delay circuit is a delay time variable delaying the reset signal. 2. The reset circuit according to claim 1, wherein said reset circuit comprises: an inverted output signal of said first flip-flop;
An OR circuit for calculating the OR of the inverted output signal of the flip-flop and an inverted signal of the output signal of the OR circuit as the reset signal to the reset terminals of the first and second flip-flops 2. The phase comparison circuit according to claim 1, further comprising a first inversion circuit. 3. A second inverting circuit for inverting and outputting an output signal of said first inverting circuit, and an output signal of said first edge detecting circuit together with an output signal of said second inverting circuit. A first AND circuit that supplies a signal obtained by calculating a logical product of the input signals to a set terminal of the first flip-flop; and a third circuit that inverts an output signal of the first inverting circuit and outputs the inverted signal.
And an output signal of the second edge detection circuit together with an output signal of the third inversion circuit, and a signal obtained by calculating a logical product of these input signals is set at the set terminal of the second flip-flop. 3. The phase comparison circuit according to claim 2, further comprising: a second AND circuit that supplies the second AND circuit. 4. A phase comparator for outputting a signal corresponding to a phase difference between a first signal and a second signal, and a voltage generator for generating a voltage signal having a level corresponding to a signal output from the phase comparator. A frequency generating circuit that outputs a signal having a frequency corresponding to a voltage signal of the voltage generating circuit to the phase comparing circuit as the first signal; and a phase comparing circuit that uses a reference signal having a constant frequency as the second signal. A phase locked loop circuit comprising: a reference frequency generation circuit that outputs a signal to the circuit; wherein the phase comparison circuit detects a rising edge of the first signal; and a second signal. A second edge detection circuit for detecting a rising edge of the first edge detection circuit, and a signal of one level is supplied to a first output terminal of the phase comparison circuit in response to an output signal of the first edge detection circuit, and reset. A first flip-flop for supplying a signal of the other level to the first output terminal in accordance with a signal, and a signal of one level in response to an output signal of the second edge detection circuit, A second flip-flop that supplies a signal of the other level to the second output terminal in response to a reset signal, and an output level of the first and second flip-flops, A phase locked loop circuit comprising: a reset circuit that outputs the reset signal when the level is one of the levels; and a delay circuit that delays the reset signal and has a variable delay time. 5. The phase locked loop circuit according to claim 4, wherein a delay time of said delay circuit is set to a value that minimizes a noise component in said first signal. 6. The reset circuit, comprising: an inverted output signal of the first flip-flop;
An OR circuit for calculating the OR of the inverted output signal of the flip-flop and an inverted signal of the output signal of the OR circuit as the reset signal to the reset terminals of the first and second flip-flops The phase-locked loop circuit according to claim 4, further comprising a first inverting circuit. 7. The phase comparison circuit according to claim 2, wherein said second comparison circuit inverts an output signal of said first inversion circuit and outputs the inverted signal.
An inversion circuit, and an output signal of the first edge detection circuit together with an output signal of the second inversion circuit, and a signal obtained by calculating a logical product of the input signals and a set terminal of the first flip-flop And a third AND circuit that inverts an output signal of the first inverting circuit and outputs the inverted signal.
And an output signal of the second edge detection circuit together with an output signal of the third inversion circuit, and a signal obtained by calculating a logical product of these input signals is set at the set terminal of the second flip-flop. 7. The phase-locked loop circuit according to claim 6, further comprising: a second AND circuit that supplies the second AND circuit. 8. The phase locked loop circuit according to claim 4, wherein said voltage generation circuit includes a capacitor and a charge pump circuit for controlling charging and discharging of said capacitor. 9. A frequency control circuit, comprising: a voltage control generation circuit; and a first frequency division circuit for supplying a frequency-divided signal obtained by dividing the output signal of the voltage control generation circuit to the phase comparison circuit as the first signal. The phase-locked loop circuit according to claim 4, further comprising a peripheral circuit. 10. A reference frequency generating circuit, comprising: a reference oscillation circuit; and a second frequency-divided signal obtained by dividing an output signal of the reference oscillation circuit, the second signal being supplied to the phase comparison circuit.
5. The phase-locked loop circuit according to claim 4, further comprising: a frequency dividing circuit.