CN110830035A

CN110830035A - Phase-locked loop and locking detection method and circuit thereof

Info

Publication number: CN110830035A
Application number: CN201911204646.0A
Authority: CN
Inventors: 何力
Original assignee: Hunan Goke Microelectronics Co Ltd
Current assignee: Hunan Goke Microelectronics Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-02-21
Anticipated expiration: 2039-11-29
Also published as: CN110830035B

Abstract

The application discloses phase-locked loop and locking detection method and circuit thereof, the locking detection circuit comprises: a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal; the pulse width conversion unit is connected with the phase identification unit and used for outputting a voltage pulse width signal corresponding to the pulse width and the phase difference under the action of the detection result signal; the judgment output unit is connected with the pulse width conversion unit and comprises a charge-discharge module and a voltage indication module; the charge-discharge module is used for switching charge-discharge states according to pulse widths of the voltage pulse width signals, and the voltage indicating module is used for generating level indicating signals corresponding to periodic charge-discharge average voltages of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indicating signals. The phase difference is indicated based on the average voltage of periodic charging and discharging, the misjudgment of the locking state caused by transient signal interference is effectively avoided, and the accuracy of locking detection is improved.

Description

Phase-locked loop and locking detection method and circuit thereof

Technical Field

The present disclosure relates to analog integrated circuits, and particularly to a phase-locked loop and a lock detection method and circuit thereof.

Background

A pll is an analog circuit commonly found in rf or digital-analog hybrid chips for generating an rf carrier signal or a clock signal in the chip. After the phase-locked loop circuit is powered on, a certain locking time is needed to enable the phase-locked loop to finish locking and then to output a stable carrier signal or a stable clock signal. Therefore, when the phase-locked loop circuit is applied, a lock detection circuit is used to detect whether the phase-locked loop has completed locking. The phase difference between the REF (reference clock) signal and the FBK (feedback clock) signal inside the pll circuit (the time interval between the rising edges of the two signals) is always smaller than a preset threshold (usually set to 1% of the period of the REF signal).

Referring to fig. 1, in the lock detection circuit of the phase locked loop disclosed in the prior art shown in fig. 1, the FBK signal and the REF signal are respectively sent to the input terminals of the D flip-flops D1 and D2, and are respectively sent to the clock terminals of the D flip-flops D2 and D1 after being delayed by the clock buffers BUF1 and BUF2 (the delay time is equal to a preset threshold). Therefore, when the REF signal leads the FBK signal, D2 outputs a high level, when the lead time length is less than a preset threshold value, D1 also outputs a high level, AND the high level is output after passing through an AND gate 1; when the FBK signal leads the REF signal, D1 outputs a high level, AND when the lead time is less than a preset threshold, D2 also outputs a high level, which is output after passing through AND gate AND 1. That is, when the phase difference between the FBK signal AND the REF signal is within a preset threshold, the AND gate AND1 outputs a high level.

However, in practical applications, when the phase-locked loop is not locked, the phase difference between the FBK signal and the REF signal may be instantaneously smaller than the threshold, and for this situation, the lock detection circuit shown in fig. 1 may also output a high level, which may cause a misjudgment on the lock state of the phase-locked loop, and cause a logic misprocessing in a subsequent receiving circuit.

In view of the above, it is an important need for those skilled in the art to provide a solution to the above technical problems.

Disclosure of Invention

The present application provides a phase-locked loop, a lock detection method and a lock detection circuit thereof, so as to effectively avoid misjudgment of a lock state caused by transient state interference and improve accuracy of lock detection.

In order to solve the above technical problem, in a first aspect, the present application discloses a lock detection circuit for a phase-locked loop, including:

a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal;

the pulse width conversion unit is connected with the phase identification unit and is used for outputting a voltage pulse width signal with the pulse width corresponding to the phase difference under the action of the detection result signal;

the judgment output unit connected with the pulse width conversion unit comprises a charge-discharge module and a voltage indication module; the charge-discharge module is used for switching charge-discharge states according to pulse widths of the voltage pulse width signals, and the voltage indicating module is used for generating level indicating signals corresponding to periodic charge-discharge average voltages of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indicating signals.

Optionally, the detection result signal includes a first control pulse width signal and a second control pulse width signal;

the phase identification unit is specifically configured to: outputting a first control pulse width signal having a pulse width corresponding to the magnitude of the phase difference when the REF signal leads the FBK signal; and outputting a second control pulse width signal having a pulse width corresponding to the magnitude of the phase difference when the FBK signal leads the REF signal.

Optionally, the voltage pulse width signal is at a high level during a period when the first control pulse width signal is at a high level or the second control pulse width signal is at a high level.

Optionally, the phase identifying unit includes a first D flip-flop, a second D flip-flop, and a nand gate;

a clock end of the first D flip-flop is used for receiving the REF signal, a positive output end is used for outputting the first control pulse width signal, and a negative output end is used for outputting a first inverted control pulse width signal;

the clock end of the second D flip-flop is used for receiving the FBK signal, the positive output end is used for outputting the second control pulse width signal, and the negative output end is used for outputting a second inverted control pulse width signal;

the input end of the first D trigger and the input end of the second D trigger are both connected with a power supply; the reset end of the first D flip-flop and the reset end of the second D flip-flop are both connected with the output end of the NAND gate; and two input ends of the NAND gate are respectively used for receiving the first control pulse width signal and the second control pulse width signal.

Optionally, the pulse width conversion unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the source electrode of the first PMOS tube is connected to a power supply, and the drain electrode of the first PMOS tube is connected to the source electrode of the third PMOS tube; the source electrode of the second PMOS tube is connected to a power supply, and the drain electrode of the second PMOS tube is connected to the source electrode of the fourth PMOS tube; the drain electrodes of the third PMOS tube, the fourth PMOS tube, the first NMOS tube and the second NMOS tube are connected with each other and are used as the output end of the pulse width conversion unit;

the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are all connected with one another; the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded;

the grid electrodes of the first PMOS tube and the first NMOS tube are used for receiving the first control pulse width signal; the grid electrodes of the fourth PMOS tube and the fourth NMOS tube are used for receiving the first inverse control pulse width signal; the grid electrodes of the second PMOS tube and the third NMOS tube are used for receiving the second control pulse width signal; and the grids of the third PMOS tube and the second NMOS tube are used for receiving the second inverse control pulse width signal.

Optionally, the charge and discharge module includes a fifth PMOS transistor, a fifth NMOS transistor, a ground resistor, and a first capacitor;

the grid electrodes of the fifth PMOS tube and the fifth NMOS tube are connected in parallel and are connected with the output end of the pulse width conversion unit; the drains of the fifth PMOS tube and the fifth NMOS tube are both connected with the first capacitor and are used as the output end of the charge-discharge module to be connected with the voltage indication module; the other end of the first capacitor is grounded; the source electrode of the fifth PMOS tube is connected to a power supply, and the source electrode of the fifth NMOS tube is connected to the grounding resistor.

Optionally, the voltage indication module includes a sixth PMOS transistor, a second capacitor, a current source, and an inverter;

the source electrode of the sixth PMOS tube is connected to a power supply, and the grid electrode of the sixth PMOS tube is connected with the output end of the charge-discharge module; the first end of the second capacitor is connected to a power supply; the output end of the current source is grounded; the drain electrode of the sixth PMOS tube, the second end of the second capacitor and the input end of the current source are all connected with each other and are connected with the input end of the phase inverter; and the output end of the phase inverter is used as the output end of the voltage indicating module and is used for outputting the level indicating signal.

In a second aspect, the present application also discloses a phase locked loop comprising any one of the lock detection circuits as described above.

In a third aspect, the present application further discloses a lock detection method for a phase-locked loop, including:

detecting the phase difference between the REF signal and the FBK signal and generating a detection result signal;

generating a voltage pulse width signal having a pulse width corresponding to the magnitude of the phase difference based on the detection result signal;

switching the charging and discharging state of a charging and discharging module according to the pulse width of the voltage pulse width signal;

and generating a level indicating signal corresponding to the periodic charge-discharge average voltage of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset value through the level indicating signal.

the detecting a phase difference between the REF signal and the FBK signal and generating a detection result signal includes: generating a first control pulse width signal having a pulse width corresponding to a magnitude of the phase difference when the REF signal leads the FBK signal; generating a second control pulse width signal having a pulse width corresponding to the magnitude of the phase difference when the FBK signal leads the REF signal; the voltage pulse width signal is at a high level during a period when the first control pulse width signal is at a high level or the second control pulse width signal is at a high level.

The application provides a lock detection circuit of phase-locked loop includes: a phase identification unit for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal; the pulse width conversion unit is connected with the phase identification unit and is used for outputting a voltage pulse width signal with the pulse width corresponding to the phase difference under the action of the detection result signal; the judgment output unit connected with the pulse width conversion unit comprises a charge-discharge module and a voltage indication module; the charge-discharge module is used for switching charge-discharge states according to pulse widths of the voltage pulse width signals, and the voltage indicating module is used for generating level indicating signals corresponding to periodic charge-discharge average voltages of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset threshold value or not by using the level indicating signals.

Therefore, the charging and discharging module is controlled to charge and discharge based on the phase detection results of the REF signal and the FBK signal, the phase difference is indicated based on the periodic charging and discharging average voltage, the locking state misjudgment when the phase difference of the REF signal and the FBK signal is instantaneously smaller than the preset threshold value is effectively avoided by utilizing the non-mutability of the average voltage, and the anti-interference performance of the instantaneous signal state and the accuracy of locking detection are improved. The phase-locked loop and the lock detection method thereof also have the beneficial effects.

Drawings

In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.

Fig. 1 is a circuit diagram of a lock detection circuit of a phase-locked loop in the prior art;

fig. 2 is a block diagram of a lock detection circuit of a phase-locked loop according to an embodiment of the present disclosure;

fig. 3 is a circuit configuration diagram of a phase evaluating unit disclosed in an embodiment of the present application;

fig. 4 is a circuit structure diagram of a pulse width conversion unit and a judgment output unit disclosed in the embodiment of the present application;

fig. 5 is a flowchart of a lock detection method for a phase-locked loop according to an embodiment of the present disclosure.

Detailed Description

The core of the application is to provide a phase-locked loop and a lock detection method and circuit thereof, so as to effectively avoid the misjudgment of the lock state caused by the interference of the transient state and improve the accuracy of the lock detection.

In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The lock detection circuit of the phase-locked loop is a circuit for detecting whether the phase-locked loop completes locking, and detects by judging whether the phase difference (the time interval of the rising edges of the REF (reference clock) signal and the FBK (feedback clock) signal inside the phase-locked loop circuit is always smaller than a preset threshold (usually set to 1% of the period of the REF signal of the reference clock). However, in practical applications, when the phase-locked loop is not locked, the phase difference between the FBK signal and the REF signal is momentarily smaller than the threshold, and for this situation, the lock detection circuit in the prior art also outputs a high level, which causes a misjudgment on the lock state of the phase-locked loop, and causes a subsequent receiving circuit to generate a logic misprocess. In view of this, the present application provides a phase-locked loop and a lock detection scheme thereof, which can effectively solve the above problems.

Referring to fig. 2, an embodiment of the present application discloses a lock detection circuit for a phase-locked loop. The lock detection circuit includes a phase identifying unit 10 for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal.

Specifically, the phase difference may be a phase difference that the REF signal leads the FBK signal or a phase difference that the FBK signal leads the REF signal, that is, as long as the phase difference between the two signals is continuously smaller than a preset threshold, it can be determined that the phase-locked loop has completed locking. Thus, as a specific embodiment, the detection result signal may include a first control pulse width signal a and a second control pulse width signal B, and the phase identifying unit 10 may be specifically configured to output the first control pulse width signal a having a pulse width corresponding to the magnitude of the phase difference when the REF signal leads the FBK signal; when the FBK signal leads the REF signal, a second control pulse width signal B having a pulse width corresponding to the magnitude of the phase difference is output.

Referring to fig. 3, the present embodiment discloses a circuit structure of a phase identifying unit 10. In this embodiment, the phase identifying unit 10 specifically includes a first D flip-flop DFF1, a second D flip-flop, and a NAND gate NAND 1;

a clock terminal of the first D flip-flop DFF1 is configured to receive the REF signal, a positive output terminal is configured to output a first control pulse width signal a, and a negative output terminal is configured to output a first inverted control pulse width signal An; the clock end of the second D trigger is used for receiving the FBK signal, the positive output end is used for outputting a second control pulse width signal B, and the negative output end is used for outputting a second inverted control pulse width signal Bn;

the input end of the first D flip-flop DFF1 and the input end of the second D flip-flop are both connected with a power supply; the reset end of the first D flip-flop DFF1 and the reset end of the second D flip-flop are both connected with the output end of the NAND gate 1; two input ends of the NAND gate NAND1 are respectively used for receiving the first control pulse width signal a and the second control pulse width signal B.

The phase identifying unit 10 identifies the magnitude of the phase difference between the REF signal and the FBK signal and determines the lead and lag relationship between the two. The specific working principle is as follows: if the phase of the REF signal is advanced by the FBK signal (i.e., the rising edge of the REF signal is advanced by the FBK), a outputs a high level and An outputs a low level under the action of the rising edge of the REF signal, B outputs a high level and Bn outputs a low level when the rising edge of the FBK signal comes, at this time, since A, B is all high level, the NAND gate NAND1 outputs a low level to reset the first D flip-flop DFF1 and the second D flip-flop DFF2, A, B is reset to a low level, and An and Bn are reset to a high level. The duration of the high level of a (low level of An) is such that the REF signal leads the phase difference of the FBK signal and the duration of the high level of B (low level of Bn) is negligible during the entire signal period.

Similarly, if the phase of the FBK signal leads the REF signal, the duration of the high level of the second control pulse width signal B (the low level of the second inverted control pulse width signal Bn) is the phase difference of the FBK signal leading the REF signal, and the duration of the high level of the first control pulse width signal a (the low level of the first inverted control pulse width signal An) is ignored.

As can be seen, the phase identifying unit 10 converts the phase difference of the REF signal leading the FBK signal into the high-level pulse width of the first control pulse width signal a (low-level pulse width of the first inverted control pulse width signal An), and converts the phase difference of the FBK signal leading the REF signal into the high-level pulse width of the second control pulse width signal B (low-level pulse width of the second inverted control pulse width signal Bn).

The lock detection circuit disclosed in the present application further includes a pulse width conversion unit 20 connected to the phase identification unit 10, and configured to output a voltage pulse width signal having a pulse width corresponding to the magnitude of the phase difference under the effect of the detection result signal.

Specifically, the pulse width conversion unit 20 functions to express the phase difference of the two signals in the form of the pulse width of the signal, regardless of whether the REF signal leads the FBK signal or the FBK signal leads the REF signal. That is, the voltage pulse width signal is at a high level during the period when the first control pulse width signal a is at a high level or the second control pulse width signal B is at a high level.

Referring to fig. 4, the embodiment of the present application discloses a specific circuit structure of the pulse width conversion unit 20. In this embodiment, the pulse width conversion unit 20 includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a first NMOS transistor Mn1, a second NMOS transistor Mn2, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn 4;

the source electrode of the first PMOS tube Mp1 is connected to a power supply, and the drain electrode is connected to the source electrode of the third PMOS tube Mp 3; the source electrode of the second PMOS tube Mp2 is connected to the power supply, and the drain electrode is connected to the source electrode of the fourth PMOS tube Mp 4; the drains of the third PMOS transistor Mp3, the fourth PMOS transistor Mp4, the first NMOS transistor Mn1, and the second NMOS transistor Mn2 are all connected to each other and serve as the output terminal of the pulse width conversion unit 20; the voltage of the node Vx is the voltage pulse width signal;

the source electrode of the first NMOS transistor Mn1, the source electrode of the second NMOS transistor Mn2, the drain electrode of the third NMOS transistor Mn3 and the drain electrode of the fourth NMOS transistor Mn4 are all connected with one another; the sources of the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4 are both grounded;

the gates of the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are both configured to receive a first control pulse width signal a; the gates of the fourth PMOS transistor Mp4 and the fourth NMOS transistor Mn4 are both configured to receive the first inverted control pulse width signal An; the gates of the second PMOS transistor Mp2 and the third NMOS transistor Mn3 are both configured to receive a second control pulse width signal B; the gates of the third PMOS transistor Mp3 and the second NMOS transistor Mn2 are both configured to receive the second inverted control pulse width signal Bn.

The pulse width conversion unit 20 can specifically convert the high-level pulse width of a and the high-level pulse width of B into the high-level pulse width of the output node Vx in a unified manner. The specific working principle is as follows: when A is high level, An is low level, B is low level and Bn is high level, the second PMOS tube Mp2 and the fourth PMOS tube Mp4 are conducted, the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are cut off, and the voltage of the output node Vx is pulled up to VDD; when B is high level, Bn is low level, A is low level and An is high level, the first PMOS tube Mp1 and the third PMOS tube Mp3 are conducted, the first NMOS tube Mn1 and the second NMOS tube Mn2 are cut off, and the voltage of the output node Vx is also pulled up to VDD; when the first D flip-flop DFF1 and the second D flip-flop DFF2 are both in a reset state, a and B are at a low level, An and Bn are at a high level, the second NMOS transistor Mn2 and the fourth NMOS transistor Mn4 are turned on, the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4 are turned off, and the voltage of the output node Vx is pulled down to a low level.

It can be seen that the high-level pulse width of a when the REF signal leads and the high-level pulse width of B when the FBK signal leads are both converted into the voltage pulse width signal of the Vx node having the same width as the pulse width, specifically, the magnitude of the phase difference between the REF signal and the FBK signal, by the pulse width conversion unit 20.

The locking detection circuit disclosed by the application further comprises a judgment output unit 30 connected with the pulse width conversion unit 20, and the judgment output unit comprises a charge-discharge module 301 and a voltage indication module 302; the charge and discharge module 301 is configured to switch a charge and discharge state according to a pulse width of the voltage pulse width signal, and the voltage indication module 302 is configured to generate a level indication signal corresponding to a periodic charge and discharge average voltage of the charge and discharge module 301, so as to indicate whether a phase difference is smaller than a preset value by using the level indication signal.

Among them, it is easily understood that the charge and discharge module 301 may be implemented based on a capacitor. Specifically, as described above, the pulse width of the voltage pulse width signal output by the pulse width conversion unit 20 is equal to the phase difference between the REF signal and the FBK signal, and the charge-discharge module 301 in the output unit 30 is determined to perform charge-discharge according to the high-low level state switching of the voltage pulse width signal, so that the pulse width of the voltage pulse width signal determines the magnitude of the periodic charge-discharge average voltage output by the charge-discharge module 301, that is, the magnitude of the phase difference between the REF signal and the FBK signal determines the magnitude of the periodic charge-discharge average voltage output by the charge-discharge module 301.

The level indication signal output by the voltage indication module 302 indicates the magnitude of the periodic charge-discharge average voltage, and by adjusting the circuit parameter setting of the voltage indication module 302, the level indication signal can be at a high level when the periodic charge-discharge average voltage is greater than a certain fixed value, and at a low level when the periodic charge-discharge average voltage is less than the certain fixed value, and the fixed value of the periodic charge-discharge average voltage corresponds to the preset threshold of the phase difference. Thus, the magnitude of the phase difference between the REF signal and the FBK signal can be indicated by the level indicating signal as the output result of the lock detection circuit.

As a specific embodiment, fig. 4 also discloses a circuit structure of the determination output unit 30 provided in the embodiment of the present application. In this embodiment, the charge-discharge module 301 includes a fifth PMOS transistor Mp5, a fifth NMOS transistor Mn5, a ground resistor R1, and a first capacitor C1; the gates of the fifth PMOS transistor Mp5 and the fifth NMOS transistor Mn5 are connected in parallel, and connected to the output terminal of the pulse width conversion unit 20; the drains of the fifth PMOS transistor Mp5 and the fifth NMOS transistor Mn5 are both connected to the first capacitor C1, and are connected to the voltage indication module 302 as the output terminal of the charge and discharge module 301; the other end of the first capacitor C1 is grounded; the source of the fifth PMOS transistor Mp5 is connected to the power supply, and the source of the fifth NMOS transistor Mn5 is connected to the ground resistor R1. The voltage of the node Vc is the periodic charge-discharge average voltage.

Meanwhile, in the present embodiment, the voltage indication module 302 includes a sixth PMOS transistor, a second capacitor C2, a current source, and an inverter INV 1; the source electrode of the sixth PMOS tube is connected to the power supply, and the grid electrode of the sixth PMOS tube is connected with the output end of the charge-discharge module 301; a first end of the second capacitor C2 is connected to the power supply; the output end of the current source is grounded; the drain of the sixth PMOS transistor, the second end of the second capacitor C2, and the input end of the current source are all connected to each other and to the input end of the inverter INV 1; an output end of the inverter INV1 serves as an output end of the voltage indicating module 302, and is used for outputting the level indicating signal LD _ OUT.

The specific operation principle of the judgment output unit 30 will be described below.

Setting the phase difference between the REF signal and the FBK signal as w, and setting a preset threshold for determining the phase difference of the phase-locked loop after locking to be 1% of the period of the REF signal, namely 1% Tref (Tref is the period of the REF signal).

The output node Vx of the pulse width conversion unit 20 outputs a pulse width of w width. When Vx is at a high level, the fifth NMOS transistor Mn5 turns on, and the charge stored in the upper plate of the first capacitor C1 is discharged to ground through the fifth NMOS transistor Mn5 and the ground resistor R1, and the voltage at the node Vc decreases. When Vx is at a low level, the fifth PMOS transistor Mp5 is turned on, and the voltage at the node Vc is pulled up to VDD quickly, ignoring the on-resistance of the fifth NMOS transistor Mp 5. Under the action of the periodic voltage pulse width signal at the node Vx, the balanced voltage at the Vc node is as follows: (ii) a

When the balanced voltage at the Vc node is applied to the gate of the sixth PMOS transistor Mp6, the drain current I3 of the sixth PMOS transistor Mp6 is:

wherein k is a constant determined by the size and process of Mp 6; vth3 is the threshold voltage of the sixth PMOS transistor Mp 6. It can be seen that the magnitude of the drain current I3 depends on the phase difference w.

Since the drain of the sixth PMOS transistor Mp6 is connected to the lower plate of the second capacitor C2 and the input terminal of the current source, and the current of the current source is IDC1, when I3> IDC1, the lower plate of the second capacitor C2 has net charge flowing in, then the voltage at the node Vd is stabilized at VDD (high level), and the level indicating signal output after passing through the inverter INV1 is low level; when I3 is not less than IDC1, net charge flows out of the lower plate of the second capacitor C2, then the voltage of the node Vd is stabilized at 0 (low level), and the level indicating signal output after passing through the inverter INV1 is high level.

When I3 is not greater than IDC1, it is inferred that w should satisfy:

by adjusting the size of IDC1, the right side of the inequality can be made equal to 1% Tref, i.e.

Therefore, when w is less than or equal to 1% Tref, I3 is less than or equal to IDC1, Vd is low level, and a level indication signal LD _ OUT finally output by the circuit is high level to indicate that the phase-locked loop completes locking, so that the function of detecting whether the phase-locked loop completes locking is realized.

It should be noted that the determination output unit 30 in the present application specifically indicates the magnitude of the phase difference based on the periodic charge-discharge average voltage of the charge-discharge module 301, and the average voltage is a voltage obtained by periodically switching the charge-discharge state for equalization and has no mutability, so that even if the phase difference between the REF signal and the FBK signal is only momentarily smaller than the preset threshold value and the phase-locked loop does not actually complete locking, the magnitude of the periodic charge-discharge average voltage does not change suddenly, and the determination output unit 30 does not output a high-level indication signal, which causes an erroneous determination of the locked state.

The lock detection circuit of the phase-locked loop disclosed by the embodiment of the application comprises: a phase identifying unit 10 for detecting a phase difference between the REF signal and the FBK signal and outputting a detection result signal; the pulse width conversion unit 20 is connected with the phase identification unit 10 and used for outputting a voltage pulse width signal corresponding to the pulse width and the phase difference under the action of the detection result signal; the judgment output unit 30 connected with the pulse width conversion unit 20 comprises a charge-discharge module 301 and a voltage indication module 302; the charging and discharging module 301 is configured to switch a charging and discharging state according to a pulse width of the voltage pulse width signal, and the voltage indicating module 302 is configured to generate a level indicating signal corresponding to a periodic charging and discharging average voltage of the charging and discharging module 301, so as to indicate whether a phase difference is smaller than a preset threshold value by using the level indicating signal.

Therefore, the lock detection circuit of the phase-locked loop disclosed by the embodiment of the application controls the charge and discharge module to charge and discharge based on the phase detection results of the REF signal and the FBK signal, further indicates the phase difference based on the periodic charge and discharge average voltage, and effectively avoids the misjudgment of the lock state when the phase difference of the REF signal and the FBK signal is instantaneously smaller than the preset threshold value by using the non-mutability of the average voltage, so that the anti-interference performance of the instantaneous signal state and the correctness of the lock detection are improved.

Further, the present application also discloses a phase locked loop comprising any one of the lock detection circuits as described above.

Referring to fig. 5, an embodiment of the present application further discloses a lock detection method for a phase-locked loop, which mainly includes:

s101: a phase difference between the REF signal and the FBK signal is detected, and a detection result signal is generated.

As an embodiment, the detection result signal may include a first control pulse width signal a and a second control pulse width signal B. Step S101 may specifically include: generating a first control pulse width signal A having a pulse width corresponding to the magnitude of the phase difference when the REF signal leads the FBK signal; when the FBK signal leads the REF signal, a second control pulse width signal B having a pulse width corresponding to the magnitude of the phase difference is generated.

S102: and generating a voltage pulse width signal having a pulse width corresponding to the magnitude of the phase difference based on the detection result signal.

Specifically, the voltage pulse width signal is at a high level during the period when the first control pulse width signal a is at a high level or the second control pulse width signal B is at a high level.

S103: and switching the charging and discharging states of the charging and discharging module according to the pulse width of the voltage pulse width signal.

S104: and generating a level indicating signal corresponding to the periodic charge-discharge average voltage of the charge-discharge module so as to indicate whether the phase difference is smaller than a preset value through the level indicating signal.

Therefore, the lock detection method of the phase-locked loop disclosed by the embodiment of the application controls the charge and discharge module to charge and discharge based on the phase detection results of the REF signal and the FBK signal, further indicates the phase difference based on the periodic charge and discharge average voltage, and effectively avoids the misjudgment of the lock state when the phase difference of the REF signal and the FBK signal is instantaneously smaller than the preset threshold value by using the non-mutability of the average voltage, so that the anti-interference performance of the instantaneous signal state and the correctness of the lock detection are improved.

For the details of the lock detection method of the phase-locked loop, reference may be made to the detailed description of the lock detection circuit of the phase-locked loop, which is not repeated herein.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the method corresponds to the circuit disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.

Claims

1. A lock detection circuit for a phase locked loop, comprising:

2. The lock detection circuit according to claim 1, wherein the detection result signal includes a first control pulse width signal and a second control pulse width signal;

3. The lock-in detection circuit according to claim 2, wherein the voltage pulse width signal is high during the period when the first control pulse width signal is high or the second control pulse width signal is high.

4. The lock detection circuit according to claim 3, wherein the phase evaluation unit includes a first D flip-flop, a second D flip-flop, a NAND gate;

5. The lock-in detection circuit according to claim 4, wherein the pulse width conversion unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

6. The lock-up detection circuit according to any one of claims 1 to 5, wherein the charge-discharge module comprises a fifth PMOS transistor, a fifth NMOS transistor, a ground resistor, and a first capacitor;

7. The lock-in detection circuit according to claim 6, wherein the voltage indication module comprises a sixth PMOS transistor, a second capacitor, a current source, and an inverter;

8. A phase locked loop comprising a lock detection circuit as claimed in any one of claims 1 to 7.

9. A lock detection method for a phase-locked loop, comprising:

10. The lock detection method according to claim 9, wherein the detection result signal includes a first control pulse width signal and a second control pulse width signal;