JP2006222524A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit employing resistors and capacitors that can reduce fluctuations in an oscillated frequency even when a power supply voltage is fluctuated. <P>SOLUTION: While a resistor circuit supplied with a first constant current generates a reference voltage, a capacitor circuit charged by a second constant current in proportion to the first constant current generates a comparison voltage in response to the charging voltage. When the comparison voltage exceeds the reference voltage, a detection signal is generated. A switch circuit turned on in response to the detection signal discharges electric charges in the capacitor circuit. The width of the detection signal is extended by a pulse width extension circuit at the same time. Then an oscillation pulse generating circuit generates an oscillation pulse on the basis of the extended pulse. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an oscillation circuit using a resistor and a capacitor, and more particularly to an internal oscillation circuit that is built in a semiconductor device and supplies an oscillation signal to other circuits in the semiconductor device.

  The CR oscillation circuit using the resistor R and the capacitor C has a simple configuration and does not require the use of a resonator such as a crystal resonator. For this reason, the CR oscillation circuit is widely used as an internal oscillation circuit for supplying a clock signal to various circuit elements (eg, CPU) in the semiconductor device.

For example, Patent Document 1 uses a transistor whose resistance value is controlled by voltage as a resistor of a CR oscillation circuit. Then, the resistance value of the transistor is controlled according to the mounting state of the external resistor. This discloses that the oscillation frequency of the CR oscillation circuit is controlled from the outside.
JP 2003-283307 A

  However, when other circuits are built in the same semiconductor device together with the oscillation circuit, fluctuations in the power supply voltage often occur. Moreover, when receiving a power supply voltage from an external battery, a voltage will fluctuate with charging / discharging. In the CR oscillation circuit of Patent Document 1, the oscillation frequency can be controlled from the outside as needed. However, when the power supply voltage varies, there is a problem that the oscillation frequency also varies.

  Therefore, an object of the present invention is to provide an oscillation circuit using a resistor and a capacitor that can reduce fluctuations in oscillation frequency even when the power supply voltage fluctuates.

An oscillation circuit according to claim 1 is a constant current source circuit for generating a first constant current and a second constant current proportional to the first constant current;
A resistor circuit for generating a first reference voltage by passing the first constant current;
A capacitor circuit that is charged with the second constant current and generates a comparison voltage according to a charging voltage;
A voltage comparison circuit that compares the comparison voltage with the first reference voltage and generates a first detection signal when the comparison voltage exceeds the first reference voltage;
A switch circuit which is turned on in response to the first detection signal and discharges the electric charge of the capacitor circuit;
A pulse width expansion circuit for generating an expansion pulse with an expanded width of the first detection signal;
And an oscillation pulse generation circuit that generates an oscillation pulse based on the extension pulse.

The oscillation circuit according to claim 2 is the oscillation circuit according to claim 1, wherein the resistance circuit further generates a second reference voltage lower than the first reference voltage,
The voltage comparison circuit further compares the comparison voltage with the second reference voltage and generates a second detection signal when the comparison voltage exceeds the second reference voltage;
The oscillation pulse generation circuit includes a flip-flop circuit that is set by the extension pulse and reset by the second detection signal.

  According to a third aspect of the present invention, in the oscillation circuit according to the second aspect, the flip-flop circuit is a reset priority type.

  An oscillation circuit according to a fourth aspect is the oscillation circuit according to the first aspect, wherein the oscillation pulse generation circuit includes a flip-flop circuit that divides the expansion pulse.

  The oscillation circuit according to claim 5 is the oscillation circuit according to any one of claims 1 to 4, wherein the pulse width expansion circuit is connected between at least one inverter, an output terminal of the inverter, and a predetermined potential point. It is characterized by having a capacitor.

  An oscillation circuit according to a sixth aspect is the oscillation circuit according to the fifth aspect, wherein the inverter is driven with a constant current.

  An oscillation circuit according to a seventh aspect is the oscillation circuit according to any one of the first to fourth aspects, wherein the switch circuit is supplied with the first detection signal via a delay circuit.

  An oscillation circuit according to an eighth aspect is the oscillation circuit according to the seventh aspect, wherein the delay circuit includes at least one inverter.

  The oscillation circuit according to claim 9 is the oscillation circuit according to any one of claims 1 to 4, wherein the constant current source circuit includes a first transistor for passing the first constant current, and the first transistor and a current mirror circuit. And a second transistor for flowing the second constant current.

  According to the present invention, the reference voltage is generated by the resistor circuit that flows the first constant current, and the comparison voltage is generated by the capacitor circuit that is charged by the second constant current. Thereby, even when the power supply voltage fluctuates, fluctuations in the oscillation frequency can be reduced.

  In addition, the width of the first detection signal output from the voltage comparison circuit is expanded by the pulse width expansion circuit. This pulse width expansion circuit includes an inverter driven by a constant current and a capacitor provided at the output terminal of the inverter. Thereby, even if the first detection signal chatters (intermittently) due to power ripple, high frequency noise, etc., it is possible to prevent pulse breakage of the oscillation output.

  Further, as the oscillation pulse generation circuit, a reset priority RS flip-flop circuit (FF circuit) that is set (S) by the expansion pulse and reset (R) by the second detection signal is used. Thereby, even when the power supply voltage fluctuation and the high frequency noise are large, the oscillation output can be output more stably. In addition, an oscillation output having a desired duty ratio can be obtained.

  Further, the circuit scale can be reduced by using a frequency dividing circuit that divides the expanded pulse as the oscillation pulse generating circuit.

  The first detection signal is supplied to the switch circuit via a delay circuit including an inverter. As a result, the duration of the first detection signal can be increased by the delay time of the delay circuit. Therefore, the oscillation output can be obtained more stably.

  Hereinafter, embodiments of the oscillation circuit of the present invention will be described with reference to the drawings. The oscillation circuit of the present invention is built in a semiconductor device. And it is used as an internal oscillation circuit for supplying a clock signal to various circuit elements (for example, CPU) in the semiconductor device.

  FIG. 1 is a diagram showing a configuration of an oscillation circuit according to a first embodiment of the present invention. In FIG. 1, a constant current source circuit 10 generates a first constant current I1 and a second constant current I2 that is proportional to the first constant current. The constant current source circuit 10 includes a first transistor 11 that is a P-type MOS transistor having a gate and a drain connected to each other, and a second transistor 21 that is a P-type MOS transistor having a gate connected to the gate of the first transistor 11. have. Since the first transistor 11 and the second transistor 21 have a current mirror configuration, the second constant current I2 is proportional to the first constant current I1. That is, I2 = k × I1, where k is a current mirror ratio and may be 1.

  The first constant current I1 flows through a resistor circuit composed of a series circuit of the resistor 12 (resistance value R1) and the resistor 13 (resistance value R2). Thus, the first reference voltage Vt1 (= I1 × (R1 + R2)) is generated in the series circuit of the resistor 12 and the resistor 13, and the second reference voltage Vt2 (= I1 × R2) is generated in the resistor 13. To do.

  When the switch circuit 23 is off, the second constant current I2 flows through the capacitor circuit 22 (capacitance C1), and charges are accumulated. When charging starts when the charge of the capacitor circuit 22 is zero, the charge voltage Vc of the capacitor circuit 22 is a voltage obtained by dividing the product of the second constant current I2 and time T by the capacitance C1. That is, Vc = I2 × T / C1. Further, when the switch circuit 23 is turned on, the charge of the capacitor circuit 22 is quickly discharged, and the charge voltage Vc becomes zero.

  FIG. 2 is a diagram illustrating a configuration example of the capacitor circuit 22. In FIG. 2, it is composed of a plurality of capacitor elements 22-1 to 22-4 and a plurality of severable elements (eg, fuses) 22-6 to 22-8. As shown in FIG. 2, the capacitor elements are connected in parallel and in series. The breakable elements (eg, fuses) 22-6 to 22-8 are connected in parallel or in series with the capacitor elements. The capacitance of the capacitor circuit 22 is trimmed by turning off one or more of the severable elements. When the capacitance of the capacitor circuit 22 is trimmed, the charging speed of the charging voltage Vc changes. That is, the oscillation frequency is changed.

  Returning to FIG. 1, in the first comparator 31, the voltage comparison circuit 30 compares the comparison voltage Vc, which is a charging voltage, with the first reference voltage Vt1, and when the comparison voltage Vc exceeds the first reference voltage Vt1, 1 detection signal Sdet1 is generated. Further, the voltage comparison circuit 30 compares the comparison voltage Vc with the second reference voltage Vt2 in the first comparator 31, and generates the second detection signal Sdet2 when the comparison voltage Vc exceeds the second reference voltage Vt2. These first and second comparators 31 and 32 are preferably constituted by differential amplifiers.

  Here, the oscillation period in the oscillation circuit of the present invention will be described. The first detection signal Sdet1 is generated from the first comparator 31 when the charging voltage Vc (= I2 × T / C1) of the capacitor circuit 22 exceeds the first reference voltage Vt1 (= I1 × (R1 + R2)). The switch circuit 23 is turned on in response to the first detection signal Sdet1, and the charging voltage Vc becomes zero voltage. That is, the charging time T becomes the oscillation cycle. This oscillation period T is expressed by the following equation (1).

I2 × T / C1 = I1 × (R1 + R2)
T = C1 × (R1 + R2) × I1 / I2 = C1 × (R1 + R2) × (1 / k) (1)
However, k = I2 / I1

  As shown in this equation (1), the oscillation period T is determined by the capacitance C1 of the capacitor circuit 22, the resistance values R1 and R2 of the resistors 12 and 13, and the current mirror ratio k of the constant current source circuit 10, and the power supply voltage Vcc Does not depend on the principle. Therefore, even when the power supply voltage Vcc fluctuates, the fluctuation of the oscillation period T (that is, the oscillation frequency) is suppressed.

  The first detection signal Sdet1 is supplied to the delay circuit 40, and is delayed by a predetermined delay time to turn on the switch circuit 23. The delay circuit 40 includes inverters 41 and 42 that are connected in series or connected in series (subordinate connection). Due to the delay circuit 40, a time delay occurs from the generation of the first detection signal Sdet1 to the ON of the switch circuit 23. As a result, the discharge of the charge of the capacitor circuit 22 is delayed, so that the time during which the first detection signal Sdet1 is generated is increased by the delay time. The delay time of the delay circuit 40 is preferably set according to the time for which the first detection signal Sdet1 is generated.

  Further, since an inverter is used for the delay circuit 40, it has a function of detecting the threshold value of the first detection signal Sdet1, and thus can be said to be a threshold value detection circuit for determining the level of the first detection signal Sdet1.

  Note that the delay circuit 40 need not be provided if the charge of the capacitor circuit 22 can be sufficiently discharged without delaying the first detection signal Sdet1.

  The pulse width extension circuit 50 generates an extended pulse in which the width of the first detection signal Sdet1 is extended (ie, extended). The pulse width expansion circuit 50 includes two inverters 51 and 52 connected in series, and a capacitor 53 connected between the output terminal of the preceding inverter 51 and the ground. The pre-stage inverter 51 is driven by the constant current I3 from the constant current source circuit 54. Therefore, the capacitor 53 is always charged to a predetermined voltage, and is quickly discharged when the first detection signal Sdet1 is generated. When the first detection signal Sdet1 is lost, the capacitor 53 is predetermined over time by the constant current I3. Charged to voltage.

  The pulse width of the first detection signal Sdet1 is expanded due to the difference between the time of discharging and charging the capacitor. Thereby, even if the width of the first detection signal Sdet1 is short, the subsequent circuit can be reliably operated.

  In addition, the first detection signal Sdet1 causes chattering (intermittent) when a power supply ripple occurs in the power supply voltage Vcc or high-frequency noise occurs depending on the operation state (eg, on / off) of other circuits. There is a case. However, in the present invention, since the width of the first detection signal Sdet1 is expanded, even if the first detection signal Sdet1 chatters, the pulse breakage of the oscillation output can be prevented.

  The RS type FF circuit 61 is an oscillation pulse generation circuit. In the RS type FF circuit 61, the expansion pulse from the pulse width expansion circuit 50 is input as the set signal SET, and the second detection signal Sdet2 is input as the reset signal RES. Then, the output signal Q of the RS type FF circuit 61 is output as an oscillation output OSC via the buffer circuit 71.

  The RS FF circuit 61 is desirably a reset priority type. Thereby, even when the power supply voltage fluctuation and the high frequency noise are large, the oscillation output can be output more stably.

  The reset signal RES is generated when the comparison voltage Vc exceeds the second reference voltage Vt2. Therefore, by adjusting the ratio of the second reference voltage Vt2 to the first reference voltage Vt1, the oscillation output OSC having a desired duty ratio can be obtained.

  Now, the operation of the first embodiment of the present invention configured as described above will be described with reference to the timing chart of FIG.

  First, when the comparison voltage Vc is lower than the second reference voltage Vt2, the second detection signal Sdet2, that is, the reset signal RES is not generated. At this time, the oscillation output OSC is at a high (H) level.

  When the comparison voltage Vc exceeds the second reference voltage Vt2 at time t1, the second comparator 32 generates the second detection signal Sdet2. Then, the RS type FF circuit 61 is reset by the reset signal RES, and the oscillation output OSC becomes a low (L) level. Even after time t1, the comparison voltage Vc continues to rise.

  When the comparison voltage Vc exceeds the first reference voltage Vt1 at time t2, the first detection signal Sdet1 is generated from the first comparator 31, and the switch circuit 23 is turned on. When the switch circuit 23 is turned on, the electric charge of the capacitor circuit 22 is discharged, and the comparison voltage Vc rapidly decreases toward the zero voltage. In the example of FIG. 1, since the delay circuit 40 is provided to delay the first detection signal Sdet1, the charge of the capacitor circuit 22 is discharged with a delay of the delay time. Accordingly, the first detection signal Sdet1 is continuously output according to the delay time of the delay circuit 40.

  When the first detection signal Sdet1 is generated at the time point t2, the output of the inverter 51 is inverted from the high level and becomes the low level. Thereby, since the electric charge charged in the capacitor 53 is rapidly discharged, the voltage Vm of the capacitor 53 decreases from a high voltage to a zero voltage in a short time. When the electric charge of the capacitor 53 is discharged, the output of the subsequent inverter 52 is inverted from the low level to the high level. Thereby, a set signal SET is generated.

  Then, when the first detection signal Sdet1 disappears in a short time from the time point t2 (that is, the width of the first detection signal Sdet1 is narrow), the capacitor 53 starts to be charged again. The capacitor 53 is charged with a constant current I3 via the inverter 51. Therefore, it takes a predetermined time for the capacitor 53 to be charged to a predetermined voltage. At the time t3 when the voltage Vm exceeds the threshold voltage of the inverter 52, the inverter 52 is inverted. As a result, since the set signal SET is output from the time point t2 to the time point t3, the first detection signal Sdet1 is expanded to the set signal SET.

  Now, at time t2, the comparison voltage Vc decreases based on the first detection signal Sdet1, and therefore the second detection signal Sdet2 (ie, the reset signal RES) is not generated. Then, on the condition that the reset signal RES is not generated, the RS type FF circuit 61 is set by the set signal SET. As a result, the oscillation output OSC becomes H level.

  Next, at time t4, the reset signal RES is generated, and the oscillation output OSC again becomes L level. In this way, the oscillation output OSC having the period T1 is output.

  FIG. 4 is a diagram showing the configuration of the oscillation circuit according to the second embodiment of the present invention. In the second embodiment of FIG. 4, the oscillation pulse generation circuit is constituted by a frequency division FF circuit 62 that divides the expansion pulse Ssp.

  In FIG. 4, a D-type FF circuit is used as the frequency dividing FF circuit 62, and the expansion pulse Ssp is input to the clock input terminal C, and the inverted output terminal Q ′ (where “′” is the upper line). Is connected to the data input terminal D. As a result, the state of the output terminal Q is inverted each time the extension pulse Ssp is input. The frequency dividing FF circuit 62 may be any FF circuit that performs a frequency dividing operation. For example, a T-type FF circuit may be used.

  In FIG. 4, since the second comparator 32 and the resistor 13 in FIG. 1 are unnecessary, the circuit configuration is simplified compared to FIG. However, in FIG. 4, the frequency of the oscillation output OSC is half of the frequency of the extension pulse Ssp. Therefore, the circuit of FIG. 4 is used according to the required frequency. In FIG. 4, other configurations are the same as those in FIG.

The figure which shows the structure of the oscillation circuit which concerns on 1st Example of this invention. FIG. 2 is a diagram illustrating a configuration example of the capacitor circuit 22. Timing chart for explaining the operation of FIG. The figure which shows the structure of the oscillation circuit which concerns on 2nd Example of this invention.

Explanation of symbols

10 constant current source circuit 11 first transistor 12, 13 resistor 21 second transistor 22 capacitor circuit 23 switch circuit 30 voltage comparison circuit 31 first comparator 32 second comparator 40 delay circuit 41, 42 inverter 50 pulse width expansion circuit 51, 52 Inverter 53 Capacitor 54 Constant current source circuit 61 RS type FF circuit 62 Frequency division FF circuit 71 Buffer circuit I1 First constant current I2 Second constant current Vt1 First reference voltage Vt2 Second reference voltage Vc Comparison voltage (charging) Voltage)
Sdet1 first detection signal Sdet2 second detection signal Vm voltage SET set signal RES reset signal Ssp expansion pulse OSC oscillation output

Claims (9)

A constant current source circuit for generating a first constant current and a second constant current proportional to the first constant current;
A resistor circuit for generating a first reference voltage by passing the first constant current;
A capacitor circuit that is charged with the second constant current and generates a comparison voltage according to a charging voltage;
A voltage comparison circuit that compares the comparison voltage with the first reference voltage and generates a first detection signal when the comparison voltage exceeds the first reference voltage;
A switch circuit which is turned on in response to the first detection signal and discharges the electric charge of the capacitor circuit;
A pulse width expansion circuit for generating an expansion pulse with an expanded width of the first detection signal;
And an oscillation pulse generation circuit for generating an oscillation pulse based on the extension pulse. The resistor circuit further generates a second reference voltage lower than the first reference voltage,
The voltage comparison circuit further compares the comparison voltage with the second reference voltage and generates a second detection signal when the comparison voltage exceeds the second reference voltage;
2. The oscillation circuit according to claim 1, wherein the oscillation pulse generation circuit includes a flip-flop circuit that is set by the extension pulse and reset by the second detection signal.   The oscillation circuit according to claim 2, wherein the flip-flop circuit is a reset priority type.   The oscillation circuit according to claim 1, wherein the oscillation pulse generation circuit includes a flip-flop circuit that divides the expansion pulse.   5. The oscillation according to claim 1, wherein the pulse width expansion circuit includes at least one inverter and a capacitor connected between the output terminal of the inverter and a predetermined potential point. circuit.   The oscillation circuit according to claim 5, wherein the inverter is driven with a constant current.   The oscillation circuit according to claim 1, wherein the switch circuit is supplied with the first detection signal via a delay circuit.   The oscillation circuit according to claim 7, wherein the delay circuit includes at least one inverter.   The constant current source circuit includes: a first transistor that flows the first constant current; and a second transistor that forms a current mirror circuit with the first transistor and flows the second constant current. The oscillation circuit according to claim 1.

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