JP2004056561A - Oscillation frequency correction circuit of ring oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically correct the oscillation frequency of a ring oscillator incorporated in a semiconductor integrated circuit without needing an external oscillator. <P>SOLUTION: An oscillation frequency correction circuit of the ring oscillator is provided with a delay circuit 2 interposed in an oscillation path of the ring oscillator 1 incorporated in the semiconductor integrated circuit, wherein a plurality of delay elements with delay quantity different from one another are connected in parallel; a frequency detection circuit 3 for receiving an output signal Pr of the ring oscillator 1 and converting the output signal Pr into a plurality of voltage level values obtained by segmentalizing the advance/delay of an oscillation frequency; a capacitor voltage latching circuit 4 for determining logical values according to whether the plurality of a voltage level value outputted by the frequency detection circuit 3 individually exceed a threshold and latching data bits of the determined logical value in each output signal Pr; and a selection circuit 5 for selecting one delay element in the delay circuit 2 as a component of the ring oscillator 1 on the basis of a combination of a plurality of data bits outputted by the capacitor voltage latching circuit 4. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation frequency correction circuit for correcting an oscillation frequency of a ring oscillator built in a semiconductor integrated circuit such as a microcomputer.
[0002]
[Prior art]
A ring oscillator built into a semiconductor integrated circuit is an oscillation circuit in which inverters are connected in series in an odd number of stages and the output of the last stage is fed back to the first stage. With a variation of 50% to 100%. Therefore, especially in a ring oscillator built in a microcomputer, it is necessary to correct the oscillation frequency.
[0003]
Therefore, in the conventional microcomputer, an oscillator having a small frequency change due to temperature change is connected so that the oscillation frequency can be measured, and the measured oscillation frequency of the external oscillator and the oscillation frequency of the ring oscillator measured separately are used. Thus, the oscillation frequency of the ring oscillator was corrected by software processing.
[0004]
[Problems to be solved by the invention]
As described above, in the conventional microcomputer, the oscillation frequency of the ring oscillator has to be corrected by software processing, and the correction processing itself is a load. In addition, there is a problem that power consumption increases during the correction process because the external oscillator performs high-speed operation.
[0005]
The present invention has been made in view of the above, and it is possible to automatically correct the oscillation frequency of a ring oscillator built in a semiconductor integrated circuit without requiring an external oscillator, and to suppress power consumption in the correction operation. It is an object of the present invention to obtain a ring oscillator oscillating frequency correction circuit that can be used.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an oscillation frequency correction circuit for a ring oscillator according to the present invention is a ring oscillator built in a semiconductor integrated circuit, wherein the delay circuit is interposed in an oscillation path of the ring oscillator, and A delay circuit in which a plurality of delay elements having different amounts are connected in parallel, and a frequency detection circuit that detects a change in the oscillation frequency of the ring oscillator, wherein one signal electrode is connected to a power supply, and the ring electrode is connected to a drive electrode. A transistor to which an output signal of the oscillator is applied, a resistor element provided between the other signal electrode of the transistor and ground, and a plurality of capacitor circuits connected in parallel to the resistor element and connected in series. A capacitor circuit comprising a capacitor and outputting a divided voltage signal indicating a voltage level value from each connection terminal. A logic value is determined based on whether or not a plurality of voltage level values output by the frequency detection circuit individually exceed a threshold value, and a data bit of the defined logic value is latched for each output signal of the ring oscillator. A latch circuit; and a selection circuit that selects one delay element in the delay circuit as a component of the ring oscillator based on a combination of a plurality of data bits output by the latch circuit.
[0007]
According to the present invention, a delay circuit in which a plurality of delay elements having different delay amounts are connected in parallel is provided in the oscillation path of the ring oscillator. In the frequency detection circuit, the transistor receives the output signal of the ring oscillator and alternately repeats a conductive state and a non-conductive state for a certain period. When the transistor is in a conductive state, the capacitor circuit charges a plurality of capacitors connected in series, and outputs a divided voltage signal indicating a voltage level value from each connection terminal. The level of each divided signal changes depending on whether the period during which the transistor is conducting is long or short, that is, whether the oscillation frequency of the ring oscillator is low or high. In the latch circuit, a logical value is determined based on whether a plurality of voltage level values output by the frequency detecting circuit individually exceed a threshold value, and a data bit of the determined logical value is latched for each output signal of the ring oscillator. In the selection circuit, one delay element in the delay circuit is selected as a component of the ring oscillator based on a combination of a plurality of data bits output from the latch circuit.
[0008]
An oscillation frequency correction circuit for a ring oscillator according to the next invention is a ring oscillator built in a semiconductor integrated circuit, wherein the drive voltage is generated by a drive voltage generation circuit connected to a power supply terminal of each component of the ring oscillator. A drive voltage generating circuit in which a plurality of different regulator circuits are connected in parallel, and a frequency detection circuit that detects a change in the oscillation frequency of the ring oscillator, one signal electrode is connected to a power supply, the drive electrode A transistor to which an output signal of the ring oscillator is applied, a resistance element provided between the other signal electrode of the transistor and ground, and a plurality of capacitor circuits connected in parallel to the resistance element and connected in series. Capacitor circuit consisting of capacitors and outputting a divided voltage signal indicating the voltage level value from each connection terminal A logic value is determined by whether a plurality of voltage level values output by the frequency detection circuit individually exceed a threshold value, and a data bit of the defined logic value is output for each output signal of the ring oscillator. And a selection circuit that selects one regulator circuit in the drive voltage generation circuit as a drive power supply for each component of the ring oscillator based on a combination of a plurality of data bits output by the latch circuit. It is characterized by having.
[0009]
According to the present invention, the power supply terminal of each component of the ring oscillator is not connected to the operation power supply of the semiconductor integrated circuit, but a drive voltage generation circuit in which a plurality of regulator circuits generating different drive voltages are connected in parallel. Connected to the circuit. In the frequency detection circuit, the transistor receives the output signal of the ring oscillator and alternately repeats a conductive state and a non-conductive state for a certain period. When the transistor is in a conductive state, the capacitor circuit charges a plurality of capacitors connected in series, and outputs a divided voltage signal indicating a voltage level value from each connection terminal. The level of each divided signal changes depending on whether the period during which the transistor is conducting is long or short, that is, whether the oscillation frequency of the ring oscillator is low or high. In the latch circuit, a logical value is determined based on whether a plurality of voltage level values output by the frequency detecting circuit individually exceed a threshold value, and a data bit of the determined logical value is latched for each output signal of the ring oscillator. In the selection circuit, one regulator circuit in the drive voltage generation circuit is selected as a drive power supply for each element of the ring oscillator based on a combination of a plurality of data bits output from the latch circuit.
[0010]
In the oscillation frequency correction circuit for a ring oscillator according to the next invention, in the above-mentioned invention, the latch circuit is configured so that the latch circuit is determined based on a signal obtained by performing a logical sum of an output signal of the ring oscillator and a binary enable signal. It is characterized by latching a data bit of a logical value.
[0011]
According to the present invention, in the above invention, in the latch circuit, the operation of latching the data bit of the predetermined logical value is performed based on a signal obtained by performing an OR operation of the output signal of the ring oscillator and the binary enable signal. Be done. That is, the latch circuit can control whether to update the latch data by manipulating the signal level of the enable signal.
[0012]
In the oscillation frequency correction circuit for a ring oscillator according to the next invention, in the above invention, in the frequency detection circuit, a logical sum of an output signal of the ring oscillator and a binary enable signal is obtained at a drive electrode of the transistor. A signal is applied.
[0013]
According to the present invention, in the above-described invention, in the frequency detection circuit, a signal obtained by performing a logical sum of the output signal of the ring oscillator and the binary enable signal is applied to the drive electrode of the transistor. That is, by manipulating the signal level of the enable signal, the transistor can be controlled so as to maintain the non-conducting state irrespective of the state of the output signal of the ring oscillator, so that no current flows through the resistance element.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of an oscillation frequency correction circuit for a ring oscillator according to the present invention will be described in detail with reference to the accompanying drawings.
[0015]
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of an oscillation frequency correction circuit of a ring oscillator according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a specific configuration example of the capacitor voltage latch circuit shown in FIG.
[0016]
In FIG. 1, the ring oscillator 1 is composed of, for example, five inverters, and a delay circuit 2 is provided in the middle of the oscillation path. The delay circuit 2 includes a plurality of delay elements (four delay elements 2a, 2b, 2c, and 2d in the illustrated example) connected in parallel. The four delay elements 2a, 2b, 2c, 2d) have different delay amounts from each other, are individually selected by selection signals Sa, Sb, Sc, Sd from the selection circuit 5, and are one of the components of the ring oscillator 1. It is supposed to be.
[0017]
The output signal Pr of the ring oscillator 1 is input to the frequency detection circuit 3 and the capacitor voltage latch circuit 4. The frequency detection circuit 3 includes a charging transistor Tp, a capacitor circuit 3b for generating a divided voltage signal, and a charge / discharge resistance element R.
[0018]
The transistor Tp is a P-channel transistor. The output signal Pr of the ring oscillator 1 is applied to the gate electrode, and the source electrode is connected to the power supply 3a. Between the drain electrode of the transistor Tp and the ground (ground), a capacitor circuit 3b and a resistance element R connected in parallel are provided.
[0019]
In the illustrated example, the capacitor circuit 3b includes four capacitors (capacitance elements) C connected in series. The four capacitors (capacitance elements) C have the same distance between the electrode plates, divide the potential difference between the drain electrode of the transistor Tp and the ground (ground) into four equal parts, and divide the voltage VoutA as a 3/4 voltage. And VoutB, which is a 1/2 voltage, and VoutC, which is a 1/4 voltage. These divided signals VoutA, VoutB, and VoutC are input to the capacitor voltage latch circuit 4, respectively.
[0020]
The capacitor voltage latch circuit 4 is provided for each of the divided signals VoutA, VoutB, and VoutC, and outputs the latch signals Aout, Bout, and Cout to the selection circuit 5, respectively. FIG. 2 shows a circuit that receives the divided signal VoutA and generates the latch signal Aout. The circuit that generates the latch signal Bout in response to the divided signal VoutB and the circuit that generates the latch signal Cout in response to the divided signal VoutC have the same configuration.
[0021]
2, the capacitor voltage latch circuit 4 includes inverters 21, 24, 27, transmission gates 22, 25, and data latch circuits 23, 26.
[0022]
Inverter 21 inverts and outputs to transmission gate 22 when voltage division signal VoutA from capacitor circuit 3b exceeds the threshold value. The output of the transmission gate 22 is input to a data latch circuit 23 configured by connecting the inverters 23a and 23b in antiparallel. The output of the data latch circuit 23 is input via the inverter 24 to the data latch circuit 26 configured by connecting the inverters 26a and 26b in anti-parallel. The latch signal Aout is output from the data latch circuit 26 to the selection circuit 5.
[0023]
The inverter 27 generates a bar (hereinafter, referred to as “Pr−”) of an inverted signal Pr obtained by inverting the output signal Pr of the ring oscillator 1. The output signal Pr is applied to the gate electrode of the P-channel transistor 22b of the transmission gate 22 and the gate electrode of the N-channel transistor 25a of the transmission gate 25. The inversion signal Pr− is applied to the gate electrode of the N-channel transistor 22a of the transmission gate 22 and the gate electrode of the P-channel transistor 25b of the transmission gate 25.
[0024]
That is, the transmission gates 22 and 25 control the data transfer timing to the data latch circuits 23 and 26 according to the output signal Pr of the ring oscillator 1.
[0025]
Returning to FIG. 1, the selection circuit 5 includes three-input NAND gate circuits 51, 52, 53, and 54, and inverters 55, 56, 57, 58, 59, and 60. One of the delay elements 2a, 2b, 2c, 2d is selected.
[0026]
The latch signals VoutA, VoutB, and VoutC are directly input to the NAND gate circuit 51, and output the selection signal Sa to the delay element 2a. That is, the selection signal Sa is generated when {VoutA, VoutB, VoutC} = {111}.
[0027]
The latch signals VoutA and VoutB are directly input to the NAND gate circuit 52, the latch signal VoutC is input via the inverter 55, and the selection signal Sb is output to the delay element 2b. That is, the selection signal Sb is generated when {VoutA, VoutB, VoutC} = {110}.
[0028]
The latch signal VoutA is directly input to the NAND gate circuit 53, the latch signals VoutB and VoutC are input via the inverters 56 and 57, and the selection signal Sc is output to the delay element 2c. That is, the selection signal Sc is generated when {VoutA, VoutB, VoutC} = {100}.
[0029]
The latch signals VoutA, VoutB, and VoutC are input to the NAND gate circuit 54 via the inverters 58, 59, and 60, and output the selection signal Sd to the delay element 2d. That is, the selection signal Sd is generated when {VoutA, VoutB, VoutC} = {000}.
[0030]
Next, the operation of the oscillation frequency correction circuit according to the first embodiment configured as described above will be described with reference to FIGS. FIG. 3 is a diagram illustrating a charge / discharge operation based on an output signal of the ring oscillator shown in FIG. FIG. 4 is a diagram illustrating the relationship between the oscillation frequency of the ring oscillator shown in FIG. 1 and the charge / discharge operation.
[0031]
First, a basic operation of the frequency detection circuit 3 will be described with reference to FIGS. As shown in FIG. 3A, the output signal Pr of the ring oscillator 1 is a pulse in which a high level (hereinafter referred to as “H level”) period and a low level (hereinafter referred to as “L level”) period are alternately repeated. Signal.
[0032]
In the frequency detection circuit 3, the P-channel transistor Tp is turned on during the period when the output signal Pr of the ring oscillator 1 is at the L level, and is turned off during the period when the output signal Pr is at the H level. When the transistor Tp is turned on, a charging current is supplied from the drain electrode of the transistor Tp to the capacitor circuit 3b, and the capacitor circuit 3b is charged. When the transistor Tp is turned off, the charge of the capacitor circuit 3b is discharged to the ground (ground) through the resistance element R.
[0033]
Accordingly, the terminal voltage of the capacitor circuit 3b composed of the four capacitors (capacitance elements) C connected in series, that is, the output signal Vc of the transistor Tp is, for example, a charge / discharge operation waveform as shown in FIG. It becomes.
[0034]
Here, when the transistor Tp is turned on, the output signal Vc of the transistor Tp, that is, the terminal voltage of the capacitor circuit 3b is changed according to the time constant determined by the resistance value of the resistance element R and the capacitance value of the capacitor circuit 3b. The voltage increases toward a voltage divided by the voltage at the transistor Tp and the voltage at the resistance element R. FIG. 3B shows a case where the voltage of the power supply 3a is stabilized at a voltage obtained by dividing the voltage of the transistor Tp and the voltage of the resistance element R after the increase, but actually, The terminal voltage (charge amount) of the capacitor circuit 3b is determined by the time constant determined by the resistance value of the resistance element R and the capacitance value of the capacitor circuit 3b, the width of the period during which the transistor Tp is in a conductive state, the driving capability of the transistor Tp Varies by.
[0035]
It is known that the oscillation frequency of the ring oscillator 1 fluctuates by about 50% to 100% due to a temperature change. When the temperature rises, the delay of the inverter constituting the ring oscillator increases, so that the oscillation frequency decreases. That is, the L-level period of the output signal Pr of the ring oscillator 1 increases.
[0036]
On the other hand, the driving capability of the transistor Tp decreases as the temperature increases. The fluctuation range of the driving ability of the transistor Tp due to the temperature change is about 60%. However, since the resistance value of the resistance element R increases by about 60% when the temperature rises, the fluctuation characteristics of the two cancel each other out, and the charging ability of the capacitor circuit 3b does not change. Therefore, the amount of charge charged in the capacitor circuit 3b is governed by the length of the period during which the output signal Pr of the ring oscillator 1 is at the L level.
[0037]
That is, the magnitudes of the divided signals VoutA, VoutB, and VoutC change, for example, as shown in FIG. 4, reflecting changes during a period when the output signal Pr of the ring oscillator 1 is at the L level. FIG. 4A shows a charge / discharge waveform when the oscillation frequency of the ring oscillator 1 is low, that is, when the L level period of the output signal Pr of the ring oscillator 1 is long. (B) shows the charge / discharge waveform when the oscillation frequency of the ring oscillator 1 is high, that is, when the L level period of the output signal Pr of the ring oscillator 1 is short.
[0038]
Next, the operation of the capacitor voltage latch circuit 4 will be described with reference to FIG. 2, the divided voltage signal VoutA is input to the transmission gate 22 via the inverter 21. In transmission gate 22, during the period when output signal Pr of ring oscillator 1 is at L level, inverted signal Pr- is at H level, and N-channel transistor 22a is conductive, so that the output value of inverter 21 is N-channel transistor 22a. Through the data latch circuit 23. Data of the data latch circuit 23 is input to the transmission gate 25 via the inverter 24.
[0039]
When the output signal Pr of the ring oscillator 1 rises to the H level, in the transmission gate 25, the N-channel transistor 25a is turned on, so that the output value of the inverter 24 is transmitted to the data latch circuit 26 via the N-channel transistor 25a. The latch signal Aout is held and output to the selection circuit 5.
[0040]
Here, in the inverter 21, if the divided voltage VoutA is at a level exceeding the threshold, the output is set to the L level, but if not, the output is set to the H level. When the inverter 21 changes the output to the L level, "0" is latched in the data latch circuits 23 and 26. When the output of the inverter 21 becomes H level, “1” is latched in the data latch circuits 23 and 26. That is, the value of the latch signal Aout output to the selection circuit 5 changes between “0” and “1” depending on the magnitude of the divided signal VoutA.
[0041]
This will be described with reference to FIG. In FIG. 4A, when the oscillation frequency of the ring oscillator is low, the L level period of the output signal Pr is long as shown in (1). Is charged. However, in FIG. 4B, when the oscillation frequency of the ring oscillator is high, the L level period of the output signal Pr is short as shown in (1), and therefore, as shown in (2), in the capacitor circuit 3b, , Charging becomes insufficient. In this case, the levels of the divided signals VoutA, VoutB, and VoutC are lower than those in the case of FIG. It should be noted that the division ratios of the divided signals VoutA, VoutB, and VoutC are the same in the case of FIG. 4A and the case of FIG. 4B.
[0042]
As described above, the capacitor voltage latch circuit 4 for each of the divided signals VoutA, VoutB, and VoutC can output the latch signals Aout, Bout, and Cout having values corresponding to the change in the oscillation frequency of the ring oscillator. In the capacitor circuit 3b, since the level becomes H level in order from the transistor Tp side, the combinations of the values of the latch signals Aout, Bout, and Cout are four kinds of {000} 100 {110} 111}.
[0043]
In the selection circuit 5, when the combination of the values of the latch signals Aout, Bout and Cout is {000}, the selection signal Sd is output from the NAND gate circuit 54, and the delay element 2d is selected. When the combination of the values of the latch signals Aout, Bout, and Cout is {100}, the selection signal Sc is output from the NAND gate circuit 53, and the delay element 2c is selected. When the combination of the values of the latch signals Aout, Bout, and Cout is {110}, the selection signal Sb is output from the NAND gate circuit 52, and the delay element 2b is selected. When the combination of the values of the latch signals Aout, Bout, and Cout is {111}, the selection signal Sa is output from the NAND gate circuit 51, and the delay element 2a is selected.
[0044]
As described above, one of the delay elements 2a, 2b, 2c, and 2d is connected as a component of the ring oscillator 1. As a result, the oscillation frequency of the ring oscillator 1 is controlled to increase or decrease by the selected delay element. The relationship between the oscillation frequency of the ring oscillator 1 and the delay elements 2a, 2b, 2c, 2d is specifically as follows.
[0045]
That is, if the L level period of the output signal Pr becomes shorter as the oscillation frequency of the ring oscillator 1 becomes higher, the capacitor circuit 3b shifts to insufficient charging. Therefore, the inverters are arranged in the order of the divided signals VoutC, VoutB, and VoutA. The threshold value of 21 cannot be exceeded. Therefore, the value taken into the data latch circuits 23 and 26 in the order of the divided signals VoutC, VoutB and VoutA is “1”. That is, the combinations of the values of the latch signals Cout, Bout, and Aout are {000}, {001}, {011}, and {111} from the earliest frequency. As a result, the selection signals output from the selection circuit 5 are output as Sd, Sc, Sb, and Sa in ascending order of frequency.
[0046]
Therefore, the delay elements 2a, 2b, 2c, and 2d are sequentially set to 2d, 2c, 2b, and 2a in descending order of the delay amount, so that a delay element with a large delay amount is selected as the frequency increases. Conversely, if the frequency decreases, a delay element having a small delay amount is selected. That is, the frequency fluctuation due to the temperature change is automatically suppressed to the minimum.
[0047]
As described above, according to the first embodiment, the frequency fluctuation due to the temperature of the ring oscillator is automatically detected, and the delay element to be connected can be switched according to the frequency. Can be corrected.
[0048]
Embodiment 2 FIG.
FIG. 5 is a circuit diagram showing a main configuration of the oscillation frequency correction circuit of the ring oscillator according to the second embodiment of the present invention. In a ring oscillator, the oscillation frequency tends to decrease as the operating voltage decreases. In the second embodiment, another configuration example of the circuit that corrects the oscillation frequency of the ring oscillator using this characteristic is shown.
[0049]
That is, as shown in FIG. 5, in the oscillation frequency correction circuit according to the second embodiment, the delay circuit 2 is omitted and the ring oscillator 1 is replaced with the configuration shown in the first embodiment (FIGS. 1 and 2). A drive voltage generation circuit 31 for controlling a power supply voltage of the inverter to be configured is provided. The drive voltage generation circuit 31 includes regulator circuits 31a, 31b, 31c, and 31d having different drive voltages. The regulator circuits 31a, 31b, 31c and 31d are connected in parallel, and one is selected by the selection signals Sa, Sb, Sc and Sd from the selection circuit 5 shown in FIG.
[0050]
As described above, in the second embodiment, the power supply end of the inverter included in the ring oscillator 1 is not directly connected to the operation power supply of the semiconductor integrated circuit, but is connected to the regulators 31a, 31b, 31c, and 31d. The drive voltage is controlled to increase or decrease.
[0051]
As described in the first embodiment, selection circuit 5 outputs selection signals as Sd, Sc, Sb, and Sa in descending order of the oscillation frequency of ring oscillator 1. Therefore, a regulator circuit whose drive voltage is reduced in the order of 31a, 31b, 31c, and 31d is used.
[0052]
With this configuration, when the oscillation frequency is the highest, the selection signal Sd is output. Therefore, the drive voltage is supplied to each inverter of the ring oscillator 1 from the regulator circuit 31d that outputs the lowest drive voltage, and the oscillation frequency is reduced. Correction for lowering is performed. Conversely, when the oscillation frequency is the lowest, the selection signal Sa is output. Therefore, the drive voltage is supplied to each inverter of the ring oscillator 1 from the regulator circuit 31a that outputs the highest drive voltage, and the correction to increase the oscillation frequency is performed. Is performed.
[0053]
Therefore, according to the second embodiment, similarly to the first embodiment, it is possible to automatically correct a frequency change due to a temperature change.
[0054]
Embodiment 3 FIG.
6 and 7 are circuit diagrams showing a main configuration of an oscillation frequency correction circuit of a ring oscillator according to Embodiment 3 of the present invention. In the third embodiment, a configuration example of a circuit that corrects an oscillation frequency while suppressing power consumption by adding a binary enable signal in the first or second embodiment is described. FIG. 6 is a circuit diagram in the case where an enable signal is applied to the frequency detection circuit shown in FIG. FIG. 7 is a circuit diagram when an enable signal is applied to the capacitor voltage latch circuit shown in FIG.
[0055]
That is, as shown in FIG. 6, in the oscillation frequency correction circuit according to the third embodiment, in the configuration shown in the first embodiment (FIGS. 1 and 2) or the second embodiment (FIG. 5), The OR gate circuit 33 is provided at the input stage of the transistor Tp in No. 3, and a signal obtained by performing a logical sum of the output signal Pr of the ring oscillator 1 and the enable signal E is applied to the gate electrode of the transistor Tp. .
[0056]
According to this configuration, when the enable signal E is at the H level, the transistor Tp is turned off because the H level is input to the gate electrode irrespective of the state of the output signal Pr of the ring oscillator 1.
[0057]
Therefore, according to this configuration, while the enable signal E is at the H level, no current flows from the transistor Tp to the ground (ground) via the resistance element R, so that power consumption can be suppressed.
[0058]
As shown in FIG. 7, in the oscillation frequency correction circuit according to the third embodiment, the capacitor voltage latch in the configuration shown in the first embodiment (FIGS. 1 and 2) or the second embodiment (FIG. 5) is used. A capacitor voltage latch circuit 35 is provided instead of the circuit 4.
[0059]
In the capacitor voltage latch circuit 35, an OR gate circuit 36 is provided at the input stage of the inverter 27 of the capacitor voltage latch circuit 4 shown in FIG. 2, and the inverter 27 has the output signal Pr of the ring oscillator 1 and the enable signal E A signal obtained by taking a logical sum is input.
[0060]
Therefore, the signal PrE, which is the logical sum of the output signal Pr of the ring oscillator 1 and the enable signal E, is provided between the gate electrode of the N-channel transistor 22a of the transmission gate 22 and the gate electrode of the P-channel transistor 25b of the transmission gate 25. The inverted signal PrE- is applied.
[0061]
As a result, while the enable signal E is at the H level, the N-channel transistor 22a of the transmission gate 22 maintains the non-conductive state, and the P-channel transistor 25b of the transmission gate 25 is in the conductive state. The latched data is retained, whereby the data latch circuit 26 captures and retains data of the same content. As a result, the selected delay element or regulator circuit remains unchanged.
[0062]
That is, while the enable signal E is at the H level, the state of the ring oscillator 1 is maintained, and while the enable signal E is at the L level, the frequency is corrected for each output signal Pr of the ring oscillator 1.
[0063]
As described above, according to the third embodiment, in the first or second embodiment, by switching the enable signal between the H level and the L level, the two objects of the suppression of the power consumption and the correction of the oscillation frequency are achieved. Can be achieved effectively. Further, when the operation by the enable signal is performed only by the capacitor voltage latch circuit, it is possible to select whether the correction of the transmission frequency is performed constantly or intermittently.
[0064]
【The invention's effect】
As described above, according to the present invention, the delay circuit in which the plurality of delay elements having different delay amounts are connected in parallel is provided in the oscillation path of the ring oscillator. In the frequency detection circuit, the transistor receives the output signal of the ring oscillator and alternately repeats a conductive state and a non-conductive state for a certain period. When the transistor is in a conductive state, the capacitor circuit charges a plurality of capacitors connected in series, and outputs a divided voltage signal indicating a voltage level value from each connection terminal. The level of each divided signal changes depending on whether the period during which the transistor is conducting is long or short, that is, whether the oscillation frequency of the ring oscillator is low or high. In the latch circuit, a logical value is determined based on whether a plurality of voltage level values output by the frequency detecting circuit individually exceed a threshold value, and a data bit of the determined logical value is latched for each output signal of the ring oscillator. In the selection circuit, one delay element in the delay circuit is selected as a component of the ring oscillator based on a combination of a plurality of data bits output from the latch circuit. Therefore, the oscillation frequency of the ring oscillator built in the semiconductor integrated circuit can be automatically corrected without requiring an external oscillator.
[0065]
According to the next invention, the power supply terminal of each component of the ring oscillator is not connected to the operation power supply of the semiconductor integrated circuit, but a drive voltage in which a plurality of regulator circuits that generate different drive voltages are connected in parallel. Connected to the generator circuit. In the frequency detection circuit, the transistor receives the output signal of the ring oscillator and alternately repeats a conductive state and a non-conductive state for a certain period. When the transistor is in a conductive state, the capacitor circuit charges a plurality of capacitors connected in series, and outputs a divided voltage signal indicating a voltage level value from each connection terminal. The level of each divided signal changes depending on whether the period during which the transistor is conducting is long or short, that is, whether the oscillation frequency of the ring oscillator is low or high. In the latch circuit, a logical value is determined based on whether a plurality of voltage level values output by the frequency detecting circuit individually exceed a threshold value, and a data bit of the determined logical value is latched for each output signal of the ring oscillator. In the selection circuit, one regulator circuit in the drive voltage generation circuit is selected as a drive power supply for each element of the ring oscillator based on a combination of a plurality of data bits output from the latch circuit. Therefore, the oscillation frequency of the ring oscillator built in the semiconductor integrated circuit can be automatically corrected without requiring an external oscillator.
[0066]
According to the next invention, in the above invention, in the latch circuit, the operation of latching the data bit of the predetermined logic value based on a signal obtained by performing an OR operation of the output signal of the ring oscillator and the binary enable signal is performed. Done. In other words, the latch circuit can control whether or not to update the latch data by manipulating the signal level of the enable signal. Therefore, it is possible to select whether to perform the oscillation frequency correction constantly or intermittently. it can.
[0067]
According to the next invention, in the above invention, in the frequency detection circuit, a signal obtained by performing a logical sum of the output signal of the ring oscillator and the binary enable signal is applied to the drive electrode of the transistor. That is, by manipulating the signal level of the enable signal, the transistor can be controlled so as to maintain the non-conducting state irrespective of the state of the output signal of the ring oscillator, so that no current flows through the resistance element. Therefore, power consumption can be suppressed. In the latch circuit, the state of the ring oscillator is maintained when the operation for suppressing power consumption is performed by the frequency detection circuit, and the transmission frequency of the ring oscillator is corrected when the operation for suppressing power consumption is not performed. Since the operation can be performed, the oscillation frequency can be corrected while suppressing power consumption.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an oscillation frequency correction circuit of a ring oscillator according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific configuration example of the capacitor voltage latch circuit shown in FIG.
FIG. 3 is a diagram illustrating a charge / discharge operation based on an output signal of the ring oscillator shown in FIG.
FIG. 4 is a diagram illustrating a relationship between an oscillation frequency and a charge / discharge operation of the ring oscillator shown in FIG.
FIG. 5 is a circuit diagram showing a main configuration of an oscillation frequency correction circuit of a ring oscillator according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram (a circuit diagram in a case where an enable signal is applied to the frequency detection circuit shown in FIG. 1) showing a main configuration of the oscillation frequency correction circuit of the ring oscillator according to the third embodiment of the present invention;
FIG. 7 is a circuit diagram (a circuit diagram in a case where an enable signal is applied to the capacitor voltage latch circuit shown in FIG. 2) showing a main configuration of an oscillation frequency correction circuit of a ring oscillator according to a third embodiment of the present invention; .
[Explanation of symbols]
Reference Signs List 1 ring oscillator, 2 delay circuit, 2a, 2b, 2c, 2d delay element, 3 frequency detection circuit, Tp charging transistor, R charging / discharging resistor element, 3b capacitor circuit for generating divided voltage signal, C series connection Capacitors (capacitance elements), 4, 35 capacitor voltage latch circuits, 5 selection circuits, 21, 24, 27, 55-60 inverters, 22, 25 transmission gates, 23, 26 data latch circuits, 31 drive voltage generation circuits, 31a, 31b, 31c, 31d Regulator circuit, 33, 36 OR gate circuit, 51-54 NAND gate circuit, Pr ring oscillator output signal, Vc charging transistor output signal, VoutA, VoutB, VoutC voltage dividing signal, Sa, Sb, Sb, Sd selection signal, E enable signal.

Claims (4)

In a ring oscillator built in a semiconductor integrated circuit,
A delay circuit interposed in the oscillation path of the ring oscillator, wherein a plurality of delay elements having different delay amounts are connected in parallel,
A frequency detection circuit that detects a change in the oscillation frequency of the ring oscillator, wherein one of the signal electrodes is connected to a power supply, and a drive electrode receives the output signal of the ring oscillator, and the other signal of the transistor A resistor element provided between an electrode and the ground, and a capacitor circuit connected in parallel to the resistor element, comprising a plurality of capacitors connected in series, and outputting a divided voltage signal indicating a voltage level value from each connection terminal. A frequency detection circuit including a capacitor circuit that performs
A latch circuit that determines a logical value based on whether a plurality of voltage level values output by the frequency detection circuit individually exceeds a threshold, and latches a data bit of the defined logical value for each output signal of the ring oscillator,
A selection circuit that selects one delay element in the delay circuit as a constituent element of the ring oscillator based on a combination of a plurality of data bits output by the latch circuit;
An oscillation frequency correction circuit for a ring oscillator, comprising: In a ring oscillator built in a semiconductor integrated circuit,
A drive voltage generation circuit connected to a power supply terminal of each component of the ring oscillator, and a drive voltage generation circuit in which a plurality of regulator circuits different in drive voltage to be generated are connected in parallel;
A frequency detection circuit that detects a change in the oscillation frequency of the ring oscillator, wherein one of the signal electrodes is connected to a power supply, and a drive electrode receives the output signal of the ring oscillator, and the other signal of the transistor A resistor element provided between an electrode and the ground, and a capacitor circuit connected in parallel to the resistor element, comprising a plurality of capacitors connected in series, and outputting a divided voltage signal indicating a voltage level value from each connection terminal. A frequency detection circuit including a capacitor circuit that performs
A latch circuit that determines a logical value based on whether a plurality of voltage level values output by the frequency detection circuit individually exceeds a threshold, and latches a data bit of the defined logical value for each output signal of the ring oscillator,
A selection circuit that selects one regulator circuit in the drive voltage generation circuit as a drive power supply for each component of the ring oscillator based on a combination of a plurality of data bits output by the latch circuit;
An oscillation frequency correction circuit for a ring oscillator, comprising: 3. The latch circuit according to claim 1, wherein the latch circuit latches the data bit having the predetermined logical value based on a signal obtained by performing an OR operation on an output signal of the ring oscillator and a binary enable signal. 4. An oscillation frequency correction circuit for the ring oscillator described. 4. The ring oscillator according to claim 3, wherein in the frequency detection circuit, a signal obtained by performing a logical sum of an output signal of the ring oscillator and a binary enable signal is applied to a drive electrode of the transistor. Oscillation frequency correction circuit.

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