JP4829724B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to an oscillation circuit that can be used for clock generation or the like in a semiconductor integrated circuit, and more particularly to an oscillation circuit whose oscillation frequency does not vary even when a power supply voltage varies.

  Conventionally, in a semiconductor integrated circuit, an oscillation circuit that oscillates at a predetermined cycle (frequency) using a time for charging a capacitor with a predetermined current has been used. In such an oscillation circuit, conventionally, suppression of oscillation cycle (frequency) fluctuation due to fluctuation of power supply voltage, that is, improvement of frequency stability has been recognized as a problem. For example, Patent Document 1 discloses an oscillation circuit that generates a constant current and a constant voltage that do not depend on a power supply voltage, and uses the constant current and the constant voltage to improve stability.

FIG. 4 shows an oscillation circuit described in Patent Document 1. In the oscillation circuit 140 shown in FIG. 4, a constant current independent of the power supply voltage is generated by the MOS transistors T3 and T4. This constant current also flows through the MOS transistors T7 and T8 via the MOS transistors T1 and T2 constituting the current mirror circuit. As a result, the capacitors C1 and C2 are charged with a constant current. Further, by causing the same constant current to flow through the resistor R, a constant voltage V _RSYS is generated and supplied to the comparators CP1 and CP2. The comparators CP1 and CP2 can oscillate at a constant cycle by comparing the voltages of the nodes A and B of the capacitors C1 and C2 that are alternately charged with a constant current with the constant voltage V _RSYS. it can.
JP-A-11-120882

  The circuit described in Patent Document 1 requires a circuit that generates a constant current and a constant voltage, which makes it difficult to set transistor dimensions. Furthermore, due to the limit of the operation speed of the comparator, there is a limit to the frequency at which oscillation is possible, depending on the application.

  An object of the present invention is to solve the conventional problems as described above and to provide an oscillation circuit that is easy to design while having high frequency stability. Furthermore, an additional purpose is to provide an oscillation circuit that can oscillate even at a high frequency.

  In order to solve the above problem, an oscillation circuit according to a first embodiment of the present invention includes a ground wiring, a power supply wiring to which a power supply voltage is supplied with reference to the potential of the ground wiring, and a first capacitor. A first current proportional to the power supply voltage is supplied to the other terminal of the first capacitive element having one terminal connected to one of the ground wiring or the power supply wiring, and the first capacitive element is A first charging / discharging circuit having a first current source for charging and having a discharging means for discharging the other terminal of the first capacitive element to one potential of the ground wiring or the power wiring; The second capacitor element has a capacity k times the capacity of 1 and one terminal connected to one of the ground wiring or the power wiring, and the other terminal has -k times the first current. Supplying a second current to the second capacitor element; With a second current source for discharging, and a second charging and discharging circuit having a charging means for charging the other terminal of the second capacitor to the other potential of the ground wiring or power supply wiring. And a first monitor element that monitors the voltage of the other terminal of the first capacitive element, and a second monitor element that monitors the voltage of the other terminal of the second capacitive element, The voltage of the other terminal of the first capacitive element reaches a threshold voltage having the same sign as the power supply voltage and a small absolute value with reference to the potential of the ground wiring by charging with the first current source. When the first monitoring element monitors that, the charging by the first current source is stopped to start discharging by the discharging means, and the second capacitance by the second current source is started. The discharge of the element was started, and the second monitor element monitored that the voltage at the other terminal of the second capacitive element reached the threshold voltage due to the discharge by the second current source. Before A control circuit for generating a control signal that stops discharging by the second current source and starts charging by the charging means, and starts charging the first capacitive element by the first current source; It is characterized by that.

  Here, k = 1 is preferable.

  The first and second monitor elements have an input threshold voltage equal to the threshold voltage, and an input terminal is connected to the other terminal of the first and second capacitive elements. The first and second buffers, or the first and second inverters, wherein the control circuit is further connected to outputs of the first and second monitor elements, and the first capacitive element An output of the first monitor element when the first monitor element monitors that the voltage of the other terminal of the first node has reached the threshold voltage by charging with the first current source; Output of the second monitoring element when the second monitoring element monitors that the voltage at the other terminal of the second capacitive element has reached the threshold voltage due to the discharge by the second current source And latch the front Generating a control signal, it is preferable to have a latching element.

  Furthermore, it is preferable to further include a filter that removes a noise component from an external power supply and supplies the power supply voltage to the power supply wiring.

  The oscillation circuit of the present invention can be easily designed while obtaining high frequency stability. In addition, by using an element capable of high-speed operation as a monitor element, it is possible to oscillate at a high frequency.

  FIG. 1 is a circuit diagram showing an example of an embodiment of an oscillation circuit of the present invention.

  The semiconductor integrated circuit 10 of FIG. 1 includes a current generation circuit 12, a charge / discharge circuit 14, and a control circuit 16. These circuits receive a ground potential supplied to a ground wiring (indicated by a symbol ▽ in the figure), and supply power voltage to a power wiring (indicated by a T character in the figure) with reference to the ground potential. oscvdd is supplied to operate.

  The current generation circuit 12 includes resistance elements r0, r1, and r2, an amplifier Amp, and a PMOS transistor mp0. The resistance elements r1 and r2 are connected in series between the power supply line and the ground line, generate a voltage V0 proportional to the power supply voltage oscvdd by resistance division, and supply the voltage V0 to the inverting input terminal of the amplifier Amp. The source of the PMOS transistor mp0 is connected to the power supply wiring, the output of the amplifier Amp is supplied to the gate, the source is connected to the positive phase input terminal of the amplifier Amp, and is connected to the ground wiring through the resistance element r0. ing. Thereby, a current i proportional to the voltage V0, that is, proportional to the power supply voltage oscvd flows through the PMOS transistor mp0.

  The current generation circuit 12 also has a PMOS transistor mp0 and a gate connected in common, a source connected to a power supply wiring, a PMOS transistor mp1, a PMOS transistor mp1 connected in series, and a source connected to a ground wiring. A diode-connected NMOS transistor mn0 is included. mp1 has the same dimensions (gate length and gate width) as mp0, and the same current i as mp0 flows through mp1 and mn0.

  The charge / discharge circuit 14 includes a first capacitor c_b, a PMOS transistor mp_b, a first charge / discharge circuit including an NMOS transistor mn2, a second capacitor c_u, an NMOS transistor mn_u, and a PMOS transistor mp2. And a second charge / discharge circuit.

  One terminal of each of the first capacitor element c_b and the second capacitor element c_u is connected to the ground wiring. The first capacitor c_b and the second capacitor c_u have the same capacitor C.

  The gate of the PMOS transistor mp_b is connected in common with the gate of the PMOS transistor mp0, the source is connected to the power supply wiring, and the drain is connected to the other terminal (first node n_bellow) of the first capacitor c_b. The PMOS transistor mp_b has a current I determined by a ratio of dimensions of the current i and the PMOS transistors mp_b and mp0 (for example, both gate lengths are the same and the gate width of mp_b is α times the gate width of mp0 , I = α · i) flows. Accordingly, the PMOS transistor mp_b functions as a first current source that supplies a current I to the other terminal of the first capacitor c_b. The drain of the NMOS transistor mn2 is connected to the other terminal of the first capacitor c_b, the source is connected to the ground wiring, and the signal Q is input to the gate. The NMOS transistor mn2 constitutes a switch that is turned ON / OFF according to the level of the signal Q.

  When the signal Q is at the “L” level, the NMOS transistor mn2 is turned OFF, and the first capacitor c_b is charged with the current I supplied from the first current source (PMOS transistor mp_b). When the signal Q becomes “H” level, the NMOS transistor mn2 is turned ON, and the other terminal of the first capacitor c_b is connected to the ground wiring. Accordingly, charging of the first capacitor c_b by the first current source is stopped, and the first capacitor c_b is discharged until the first node n_below becomes the potential of the ground wiring. That is, the switch including the NMOS transistor mn2 functions as a discharging unit that discharges the other terminal of the first capacitor c_b to the potential of the ground wiring.

  Note that the supply of the current I from the first current source is continued even during the period in which the NMOS transistor mn2 is ON. However, since the current I flows to the ground wiring through the switch including the NMOS transistor mn2, charging of the first capacitor c_b by the first current source is stopped.

  The gate of the NMOS transistor mn_u is commonly connected to the gate of the NMOS transistor mn0, the source is connected to the ground wiring, and the drain is connected to the other terminal (second node n_upper) of the second capacitor element c_u. The NMOS transistor mn_u has a current I determined by a ratio of dimensions of the current i and the NMOS transistors mn_u and mn0 (for example, the gate length of both is the same and the gate width of mn_u is α times the gate width of mn0). , I = α · i) flows. Thereby, the NMOS transistor mn_u functions as a second current source that supplies the current −I to the other terminal of the second capacitor c_u. The drain of the PMOS transistor mp2 is connected to the other terminal of the second capacitor c_u, the source is connected to the power supply wiring, and the signal Q is input to the gate. The PMOS transistor mp2 constitutes a switch that is turned ON / OFF according to the level of the signal Q.

  When the signal Q is at “H” level, the PMOS transistor mp2 is turned off, and the second capacitor c_u is discharged with the current −I supplied from the second current source (NMOS transistor mn_u). When the signal Q becomes “L” level, the PMOS transistor mpn2 is turned on, and the other terminal of the second capacitor c_u is connected to the power supply wiring. Accordingly, the discharge of the second capacitor c_u by the second current source is stopped, and the second capacitor c_u is charged until the second node n_upper becomes the potential of the power supply wiring. That is, the switch including the PMOS transistor mp2 functions as a charging unit that charges the other terminal of the second capacitor c_u to the potential of the power supply wiring.

  Note that the supply of the current −I from the second current source is continued even during the period in which the PMOS transistor mp2 is ON. However, since the current −I flows to the power supply line through the switch including the PMOS transistor mp2, the discharge of the second capacitor c_u by the second current source is stopped.

  The control circuit 16 includes a first buffer Buff_b whose input terminal is connected to the other terminal of the first capacitor c_b, and a second buffer whose input terminal is connected to the other terminal of the second capacitor c_u. Buff_u. These buffers operate as monitor elements that monitor the voltage at the other terminal of the corresponding capacitive element. Although not shown, these buffers Buff_b and Buff_u are also connected to the power supply wiring and the ground wiring, and operate by receiving the supply of the power supply voltage oscvdd. An input threshold voltage for determining whether the voltage at the input terminal is “L” level or “H” level is lower than the power supply voltage oscvdd (strictly, with reference to the potential of the ground wiring, Threshold voltage Vth having the same sign as power supply voltage oscvdd and a small absolute value).

  Accordingly, the first capacitor c_b is charged by the current I supplied from the first current source (PMOS transistor mp_b), and the voltage of the first node n_below reaches the threshold voltage of the first buffer Buff_b. When this is monitored (when the power supply voltage oscvdd is positive), the output of the first buffer Buff_b changes from the “L” level to the “H” level. In addition, the second capacitor element c_u is discharged with the current supplied from the second current source (NMOS transistor mn_u), and the voltage of the second node n_upper reaches the threshold voltage of the second buffer Buff_u. (When the power supply voltage oscvdd is positive), the output of the second buffer Buff_u changes from the “H” level to the “L” level.

  The first and second buffers are generally used to configure a digital logic circuit, and can operate at high speed. By using such an element capable of high-speed operation as a monitor element, an oscillation circuit that oscillates at a high oscillation frequency can be obtained. In addition, since it is not necessary to consider the response characteristics of the monitor element, the design of the oscillation circuit is easy.

  The control circuit 16 also has a latch 19 composed of two 2-input NAND gates 17 and 18. The outputs of the first and second buffers are input to this latch. That is, the output of the first buffer Buff_b is supplied to the first input terminal of the first NAND gate 17, the output of the second buffer Buff_u is supplied to the first input terminal of the second NAND gate 18, The outputs of the first and second NAND gates are connected to the second input terminal of the other NAND gate, respectively. However, only the first input terminal of the first NAND gate 17 is negative logic. Then, the output of the first NAND gate becomes the output of the latch 19, and the signal Q is output.

  The first buffer Buff_b monitors that the voltage of the first node n_below of the first capacitor c_b has reached the threshold voltage due to charging by the first current source, and the output of the first buffer Buff_b is The latch 19 latches this output (“H” level) when it changes to “H” level. In addition, the second buffer Buff_u monitors that the voltage of the second node n_upper of the second capacitor c_u has reached the threshold voltage due to the discharge by the second current source, and the second buffer Buff_u When the output changes to the “L” level, the latch 19 latches this output (“L” level).

  The output Q of the latch 19 becomes a control signal supplied to the charging / discharging circuit 14 and also becomes an output of the oscillation circuit 10.

  Next, the operation of the oscillation circuit 10 will be further described with reference to FIG.

  FIG. 2 is a waveform diagram showing waveforms of the second node n_upper, the first node n_below, and the output Q. Here, it is assumed that the threshold voltage of the first buffer Buff_b and the threshold voltage of the second buffer Buff_u are the same.

  First, it is assumed that the signal Q is at “L” level, the PMOS transistor mp2 is turned on, and the second node n_upper is at the power supply voltage oscvdd. In this state, the first buffer Buff_b monitors that the first capacitor element c_b is charged by the current I supplied from the PMOS transistor mp_b and the voltage of the first node n_belo reaches the threshold voltage. Assume that the signal Q changes to the “H” level. Then, in the second charge / discharge circuit, the PMOS transistor mp2 is turned off, and the discharge of the second capacitor element c_u by the current −I supplied from the NMOS transistor mn_u is started.

  On the other hand, in the first charging circuit, the NMOS transistor mn2 is turned on by the change of the signal Q to the “H” level. For this reason, the charging of the first capacitor c_b by the current I supplied from the PMOS transistor mp_b is stopped. Thereafter, the first capacitor element c_b is discharged by the NMOS transistor mn2, and after a predetermined time determined by the capacitance of the first capacitor element c_b and the ON resistance of the NMOS transistor mn2, the first node n_below is effectively Then, it reaches the potential (0 V) of the ground wiring.

  This time, the second buffer Buff_u monitors that the second capacitor c_u is discharged by the current −I supplied from the NMOS transistor mn_u and the voltage of the second node n_upper reaches the threshold voltage. At this point, the signal Q changes to “L” level. Then, in the first charge / discharge circuit, the NMOS transistor mn2 is turned OFF, and charging of the first capacitor element c_b by the current I supplied from the PMOS transistor mp_b is started.

  On the other hand, in the second charge / discharge circuit, the PMOS transistor mp2 is turned on by the change of the signal Q to the “L” level. For this reason, the discharge of the second capacitor element c_u by the current −I supplied from the NMOS transistor mn_u stops. Thereafter, the second capacitor element c_u is charged by the PMOS transistor mp2, and after a predetermined time determined by the capacitance of the second capacitor element c_u and the ON resistance of the PMOS transistor mp2, the second node n_upper is effectively Then, the potential of the power supply wiring (power supply voltage ossvdd) is reached.

  Hereinafter, similarly, the oscillation of the first capacitor element c_b and the discharge of the second capacitor element c_u are repeated to continue the oscillation.

Here, the oscillation period of the oscillation circuit 10 is determined by the following factors. However, the predetermined time determined by the capacitance of the first capacitive element c_b and the ON resistance of the NMOS transistor mn2 and the predetermined time determined by the capacitance of the second capacitive element c_u and the ON resistance of the PMOS transistor mp2 are respectively NMOS It is assumed that the time is not longer than the time during which the second capacitor c_u is discharged by the transistor mn_u and the time during which the first capacitor c_b is charged by the PMOS transistor mp_b. That is, when the signal Q becomes “L” level and charging of the first capacitor c_b by the PMOS transistor mp_b is started, the potential of the first node n_bellow is effectively the potential of the ground wiring. When the signal Q becomes “H” level and discharge by the NMOS transistor mn_u is started, the potential of the second node n_upper is effectively the potential of the power supply wiring.
Current: I = (oscvdd × (Rr1 / (Rr1 + Rr2)) / Rr0) × α
= Oscvdd / (β × Rr0)
Capacity: C
Threshold voltage: Vth
Charging time of the first capacitor element: Tb = C × Vth / I
Discharge time of the second capacitor element: Tu = C × (oscvdd−Vth) / I
Oscillation period: Tc = Tb + Tu = C × oscvdd / I = β × C × Rr0 (1)
From the above equation (1), it can be seen that the oscillation period of the oscillation circuit 10 of this embodiment does not depend on the power supply voltage oscvdd or the threshold voltage Vth. That is, the oscillation circuit 10 of this embodiment has high stability in which the oscillation frequency (period) does not vary even when the power supply voltage oscvdd varies. In the above equation (1) and the derivation equation, Rr0 represents the resistance value of the resistance element r0, Rr1 represents the resistance value of the resistance element r1, and Rr2 represents the resistance value of the resistance element r2. Further, β = (1 + r2 / r1) / α.

  As shown from the process of deriving the above equation (1), the current I changes in proportion to the power supply voltage oscvdd. On the other hand, the oscillation period, which is the sum of the charge time and the discharge time, is determined by the ratio of the charge amount C × oscvdd and the current I, but the charge amount also changes in proportion to the power supply voltage oscvdd. Therefore, as a result, the oscillation frequency (period) does not depend on the power supply voltage oscvdd. Therefore, unlike the conventional oscillation circuit disclosed in Patent Document 1, the oscillation circuit of the present invention achieves high stability without the need for a circuit that generates a constant current or a constant voltage that does not depend on the power supply voltage. be able to.

  The threshold voltage Vth changes depending on characteristics such as the threshold voltage of the transistors constituting the first and second buffers, and also changes due to fluctuations in the power supply voltage oscvdd. However, by configuring the first and second buffers using transistors having the same characteristics formed in the same semiconductor integrated circuit, it is easy to have threshold voltages that are effectively equal to each other. It is. As shown from the equation (1), if the threshold voltage of the first buffer and the threshold voltage of the second buffer are equal to each other, even if the value fluctuates due to the fluctuation of oscvdd, the oscillation circuit 10 The oscillation frequency (oscillation period) is kept constant.

  Thus, the oscillation circuit 10 of this embodiment can be easily designed while obtaining high frequency stability. In addition, by using an element capable of high-speed operation as a monitor element, it is possible to oscillate at a high frequency.

  Next, an example of a filter used for power supply in the oscillation circuit 10 according to the embodiment of the present invention shown in FIG. 1 will be described.

  FIG. 3 shows an example of a filter using an NMOS transistor connected in a source follower. In the filter 20, an external power supply VDD is supplied to the drain, and an NMOS transistor mn_f whose gate is connected to the midpoint between the resistance element r_f and the capacitance element c_f connected in series between the VDD and the ground wiring. Consists of. Then, the power supply voltage oscvdd supplied to the power supply wiring is output from the source of the NMOS transistor mn_f.

  As described above, the oscillation frequency (cycle) of the oscillation circuit 10 in FIG. 1 does not depend on the power supply voltage oscvdd. However, when the noise of the power supply voltage oscvdd is large and the fluctuation of the power supply voltage oscvdd occurs at a period similar to the oscillation period of the oscillation circuit 10, the oscillation period of the oscillation circuit 10 also varies. In order to suppress the influence of such noise, it is preferable to provide a filter 20 as shown in FIG. 3, for example. Thereby, the noise tolerance of the oscillation circuit 10 as a whole including the filter 20 can be improved.

  The filter 20 shown in FIG. 3 has a simple configuration and a large noise removal effect. However, the power supply voltage oscvdd that can be supplied is lower than the voltage of the external power supply VDD. In addition, the amount of the voltage drop varies depending on the variation in the threshold voltage of the NMOS transistor mn_f. However, since the oscillation circuit 10 of the present embodiment shown in FIG. 1 has an oscillation frequency (period) that does not depend on the power supply voltage oscvdd, it is possible to increase noise resistance by using such a filter 20. .

  The embodiment of the present invention has been described in detail above. It goes without saying that the present invention is not limited to the specific examples described above, and various modifications and improvements are possible.

  For example, in the above embodiment, one terminal of the first and second capacitive elements is connected to the ground wiring. However, one terminal of the first and second capacitor elements can be connected to a power supply wiring, for example. In this case, the first capacitor c_b is charged by connecting the other terminal to the ground wiring when the signal Q is at “H” level, and the current supplied from the PMOS transistor mp_b when the signal Q is at “L” level. I is discharged. The second capacitor c_u is discharged when the signal Q is at “L” level and the other terminal is connected to the power supply wiring, and is supplied from the NMOS transistor mn_u when the signal Q is at “H” level. It is charged with.

  In the above-described embodiment, the first and second capacitive elements have the same capacitance and are charged or discharged by supplying currents having the same absolute value. However, the capacitance of one capacitive element can be made larger (for example, k times) than the capacitance of the other capacitive element. In this case, the absolute value of the current that charges or discharges the capacitive element having k times the capacity is set to k times the absolute value of the current that discharges or charges the other capacitive element. Thereby, the oscillation period is determined by the equation (1). That is, as in the case of the above embodiment, it does not depend on the power supply voltage oscvdd and the threshold voltage Vth.

  However, from the viewpoint of ease of design, it is preferable that the first capacitor element and the second capacitor element have the same size and shape and have the same capacitance including parasitic capacitance components. Thereby, the current of the first current source and the current of the second current source can be made the same, and an oscillation circuit having high stability whose oscillation cycle does not depend on the power supply voltage oscvdd can be easily designed. Can do.

  In the above embodiment, a buffer is used as the monitor element. Similarly, an inverter can be used as a monitor element. In addition, various elements can be used as monitor elements, but at least in order to increase the oscillation frequency, elements such as buffers and inverters that can operate at high speed can be used as monitor elements. preferable.

It is a circuit diagram showing an example of a 1st embodiment of an oscillation circuit of the present invention. It is a wave form diagram which shows an example of the voltage waveform in the oscillation circuit of this invention. It is a circuit diagram which shows an example of the filter used for power supply in the oscillation circuit of this invention. It is a circuit diagram which shows an example of the conventional oscillation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,140 Oscillator 12 Current generator 14 Charge / discharge circuit 16 Control circuit 17, 18 2-input NAND gate 19 Latch 20 Filter

Claims (4)

A ground wiring and a power wiring to which a power supply voltage is supplied with reference to the potential of the ground wiring;
A first current proportional to the power supply voltage is supplied to the other terminal of the first capacitive element having a first capacitor and having one terminal connected to one of the ground wiring or the power supply wiring. A first current source for charging the first capacitive element, and a discharging means for discharging the other terminal of the first capacitive element to one potential of the ground wiring or the power wiring. A charge / discharge circuit;
The second capacitor element has a capacitance k times the first capacitance, and one terminal is connected to one of the ground wiring and the power supply wiring, and the other terminal has −k of the first current. A second current source for supplying a second current that is doubled to discharge the second capacitor element, and the other terminal of the second capacitor element is set to the other potential of the ground wiring or the power supply wiring. A second charging / discharging circuit having charging means for charging up to
A first monitor element that monitors the voltage of the other terminal of the first capacitive element; and a second monitor element that monitors the voltage of the other terminal of the second capacitive element, That the voltage of the other terminal of the capacitor element has reached a threshold voltage having the same sign as the power supply voltage and a small absolute value with reference to the potential of the ground wiring by charging with the first current source. When the first monitoring element monitors, the charging by the first current source is stopped to start the discharging by the discharging means, and the discharging of the second capacitive element by the second current source When the second monitor element monitors that the voltage of the other terminal of the second capacitor element has reached the threshold voltage due to the discharge by the second current source, Said second current source And a control circuit for generating a control signal for stopping charging by the charging means and starting charging by the charging means, and starting charging of the first capacitor element by the first current source. Oscillator circuit.   The oscillation circuit according to claim 1, wherein k = 1. The first and second monitor elements have an input threshold voltage equal to the threshold voltage, and first and second input terminals connected to the other terminals of the first and second capacitive elements. A second buffer or first and second inverters;
The control circuit is further connected to outputs of the first and second monitor elements, and the voltage of the other terminal of the first capacitive element is set to the threshold voltage by charging by the first current source. The output of the first monitor element and the voltage at the other terminal of the second capacitive element at the time when the first monitor element monitors the arrival of the voltage are detected by the discharge by the second current source. And a latch element that latches the output of the second monitor element at the time when the second monitor element monitors that the threshold voltage has been reached, and generates the control signal. The oscillation circuit according to claim 1 or 2.   4. The oscillation circuit according to claim 1, further comprising a filter that removes a noise component from an external power supply and supplies the power supply voltage to the power supply wiring.

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