JP3656576B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit that compares a phase of an input signal and outputs a signal having a predetermined pulse width.
[0002]
[Prior art]
Conventionally, various pulse circuits and semiconductor integrated circuits have been proposed in order to output a signal having a desired duty ratio with respect to an input pulse signal having an arbitrary duty cycle (duty ratio). The outline of a conventional circuit will be described below.
[0003]
FIG. 17 shows the configuration of a pulse signal generation circuit disclosed in Japanese Patent Application Laid-Open No. 60-217722. This pulse signal generation circuit includes delay paths L1 and L2 having different delay times t1 and t2, respectively, a delay loop that delays an input signal only by the delay path L1, and a delay path L0 in which the delay paths L1 and L2 are connected in series. To form a delay loop for delaying the input signal. The logic circuit 101 receives a signal transmitted through these two delay loops, and inputs the output to the delay path L0.
[0004]
In the circuit having the above configuration, an oscillation operation is performed while interfering signals circulating in two delay loops having different delay times, and the duty ratio of the output pulse signal is controlled by manipulating these two delay times. ing.
[0005]
In addition, the semiconductor integrated circuit described in Japanese Patent Laid-Open No. 63-237610 obtains a multiplied signal as an output by performing a logical operation on an input signal and a delayed signal using an exclusive OR circuit. At this time, in order to set this output as a fixed duty value, the changing direction of the delay amount is designated. That is, in this semiconductor integrated circuit, the positive pulse width and negative pulse width of the output multiplied signal are detected as voltages, and based on this, the delay amount is switched so that the pulse width of the output signal becomes a predetermined value. The duty ratio is adjusted.
[0006]
However, among the conventional circuit configurations described above, the circuit described in Japanese Patent Laid-Open No. 60-217722 has a lower limit of the operating frequency, and the circuit described in Japanese Patent Laid-Open No. 63-237610 is an input circuit. There is a problem that only the output signal obtained by multiplying the signal can be obtained or the duty ratio of the output signal does not become 50% except when the duty ratio of the input signal is 50%.
[0007]
Furthermore, as common to these conventional circuits, if the circuit operation is stable and is stopped for a time longer than the period of the input signal and then input is restarted, the circuit cannot follow the input signal. There is also a problem.
[0008]
Therefore, as a semiconductor integrated circuit that copes with these problems, a circuit that generates a signal having a desired duty ratio, particularly a circuit that outputs a pulse signal having a duty ratio of 50% has been proposed.
[0009]
[Problems to be solved by the invention]
However, in the circuit according to the above-described prior art, in general, when an input signal is multiplied or a signal to be compared is generated and a pulse width is compared, for example, when the signal is stopped, control cannot be performed immediately. There is.
[0010]
Further, the conventional circuit having the above-described configuration has a problem in that it cannot follow even if a deviation occurs due to the accuracy of the signal to be compared, the change of the input signal, the change due to the temperature or the power supply fluctuation.
[0011]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of accurately performing phase comparison of input signals.
[0012]
Another object of the present invention is to provide a semiconductor integrated circuit capable of outputting a signal having a desired duty ratio (for example, a duty of 50%) from an arbitrary input signal.
[0013]
[Means for Solving the Problems]
  To achieve the above object, the present invention provides delay control means for applying a predetermined delay to an input signal, the input signal as a first input signal, and the delayed signal as a second input signal. First phase control means, and second phase control means using the input signal as a first input signal and the delayed signal as a second input signal.The first phase control means detects the rising edge of the first input signal, detects the falling edge of the second input signal, and sets the phases of the first and second input signals. Further, the second phase control means detects the falling edge of the first input signal and detects the rising edge of the second input signal. Compare input signal phasesAnd providing a semiconductor integrated circuit for outputting the comparison result as a phase comparison result between the first and second input signals.In the present invention, when the second phase control means determines that there is no phase difference between the first and second input signals, the input signal is a pulse signal having a duty ratio of 50%. Judge that there is.
[0014]
  Preferably, the first and second phase control means are configured by a phase comparison circuit that compares the phases of the first and second input signals, and the phase comparison circuit outputs a phase advance as the phase comparison result. Output signal or phase delay signal. Preferably, the delay control means delays the input signal by a predetermined time.
[0015]
  Preferably, the delay control means delays the input signal according to a delay amount selected from a plurality of preset delay amounts.
[0016]
  The present invention further includes means for performing a logical operation based on the phase advance signal and the phase delay signal as the phase comparison result and outputting a pulse width control signal including a pulse delay control signal and a pulse width conversion control signal. The delay control means varies the delay amount based on the pulse delay control signal.Preferably, the delay amount is equal to or less than ½ of the period of the input signal.
[0017]
Further, pulse width conversion means for changing and outputting the pulse width of the input signal is provided, and the signal after the pulse width is changed is set as the first input signal. Preferably, the pulse width conversion means receives the pulse width conversion control signal constituting the pulse width control signal and changes the pulse width of the input signal.
[0018]
Preferably, the pulse width conversion means variably delays the pulse width of the input signal and outputs a pulse signal having a duty ratio of 50%.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, regarding the pulse width conversion circuit (pulse width conversion unit) as the semiconductor integrated circuit according to the present embodiment, (1) a pulse width detection unit, (2) a pulse width control unit, and (3) these The description will be divided into a pulse width conversion unit including a detection unit and a control unit.
[0020]
(1) Pulse width detector
FIG. 1 is a block diagram showing a configuration of a pulse width comparison circuit functioning as a pulse width detection unit in the pulse width conversion circuit according to the embodiment of the present invention. The circuit shown in the figure is based on, for example, a delayed output signal output by delaying an input signal by an arbitrary delay amount, and a rising edge of the input signal and a rising edge of the signal output after being delayed. The operation of comparing and outputting the phase with the falling edge and comparing the phase of the falling edge of the input signal with the rising edge of the delayed output signal are executed.
[0021]
The pulse width comparison circuit 10 shown in FIG. 1 includes two phase comparators functioning as a phase control circuit, that is, a phase comparator A (2) and a phase comparator B (3), and one delay control circuit. (Delay gate) 1 is constituted. The input terminal 4 for inputting the input signal S11 is connected to the input terminal of the delay control circuit 1, and one of the two input terminals of each of the phase comparators A and B (2, 3) (hereinafter referred to as “input”). Is appropriately connected to a “signal input terminal”.
[0022]
The delay control circuit 1 receives a delay selection signal, which will be described later, and applies a predetermined amount of delay to the input signal S11 (hereinafter, the delayed signal is also referred to as a “delay signal”). The output terminal of the delay control circuit 1 is connected to a terminal different from the above (hereinafter referred to as “delay signal input terminal” as appropriate) among the two input terminals of each of the phase comparators A and B (2, 3). ing.
[0023]
Of these two phase comparators 2 and 3, the phase comparator A (2) receives the input signal S 11 and the delay signal delayed by the delay control circuit 1. Then, the phase comparator A (2) detects the rising edge of the input signal S11 and detects the falling edge of the delay signal.
[0024]
As a result, the phase comparator A (2) compares the phases of both the input signals, and the result is shown in FIG. 1 with the UP signal (S13) and DOWN at the output terminals 5 and 6, respectively. It outputs as a signal (S14).
[0025]
On the other hand, the phase comparator B (3) detects the falling edge of the input signal S11, detects the rising edge of the signal delayed by the delay control circuit 1, and compares the phases. The comparison result is output as an UP signal (S15) and a DOWN signal (S16) to the output terminals 7 and 8, respectively.
[0026]
FIG. 2 is a block diagram illustrating a configuration example of the delay control circuit 1. As shown in the figure, the delay control circuit 1 has a plurality of delay selection circuits 21a and 21b connected in series in order to obtain a desired delay amount. These delay selection circuits are individually selected by a counter 25 that receives control signals (specifically, a set signal (SET2) and a phase detection signal (DET2), which will be described later) as delay selection signals. Is done.
[0027]
Note that the delay amounts of the individual delay selection circuits 21a and 21b may be the same or different. For example, when the delay amount of the delay selection circuit 21a is “d”, the delay amount of the delay selection circuit 21b may be set to 2d that is twice as much, 3d that is three times that, or the like. The delay control circuit 1 is a variable delay line and does not depend on the clock cycle.
[0028]
FIG. 3 is a block diagram showing a configuration of the delay selection circuit 21. As shown in the figure, the delay selection circuit includes a buffer circuit 31 and a selector 32. The selector 32 receives the selection signal SEL from the counter 25 of the delay control circuit 1 shown in FIG. 2 and outputs (OUT) the input signal (IN) as it is, or outputs the input signal via the buffer circuit 31. Operates to select either route. Note that the delay amount d described above can be set by the storage capacity of the buffer circuit 31.
[0029]
The pulse width comparison circuit 10 uses the phase comparators A and B (2, 3) described above and the delay control circuit 1 that makes the delay amount variable, so that two phase comparators can simultaneously detect the phase of the input signal. By detecting the coincidence state, it is determined whether the duty ratio of the input signal is 50%. Hereinafter, the determination method will be described in detail.
[0030]
4 to 9 are waveforms showing the operation timing of the pulse width comparison circuit of the pulse width conversion circuit according to the present embodiment. 4 and 5 show operation waveforms when the pulse width t1 at the high level (logic high) of the input signal is wider than the width t2 at the low level (logic low) (t1> t2). FIGS. 6 and 7 show operation waveforms when the pulse width at the high level of the input signal matches the pulse width at the low level (t1 = t2).
[0031]
FIGS. 8 and 9 show operation waveforms when the pulse width t1 at the high level of the input signal is narrower than the low level width t2 (when the pulse width is in a relationship of t1 <t2). That is, FIGS. 4 to 9 show a case where the delay amount in the delay control circuit 1 described above is gradually increased so that one of the two inputs to the phase comparator is gradually delayed from the same phase as the input signal. 2 is an input waveform of the phase comparator in FIG.
[0032]
The phase comparator A (2) in FIG. 1 receives the rising edge (indicated by an upward arrow in the figure) of the input signal (same as the signal S11 in FIG. 1) shown in FIG. Detects a falling edge (indicated by a downward arrow in the figure) of the delayed signal (the signal shown in FIG. 2B, which is the output signal of the delay control circuit 1 and indicates the signal S12 in FIG. 1). Compare them.
[0033]
Further, the phase comparator B (3) has a falling edge (indicated by a downward arrow in the figure) of the input signal (the signal S11) shown in FIG. A rising edge (indicated by an upward arrow in the figure) of a signal (the above-described signal S12) obtained by delaying the input signal is detected and compared.
[0034]
In the phase comparator A (2) and the phase comparator B (3), UP signals S13 and S15, which are signals indicating the comparison results of the input signals, are output from the output terminals 5 and 7, respectively. DOWN signals S14 and S16 are output from terminals 6 and 8, respectively. The UP signal is a signal indicating phase advance, and the DOWN signal is a signal indicating phase delay.
[0035]
These UP signal and DOWN signal are input to a pulse width control circuit that determines whether or not the phase difference between the input signal and the delay signal is minimized. Specific configuration and operation of this pulse width control circuit Will be described later.
[0036]
The delay control circuit 1 is a delay amount change control signal (that is, the delay selection shown in FIG. 1) executed by the pulse width control circuit, which will be described later, based on the UP signal and the DOWN signal output from the phase comparators A and B. Signal) is selected, the delay selection circuits 21a, 21b and the like according to this delay selection signal are selected. As a result, a predetermined amount of delay occurs in the input signal, and the phase difference between the signals input to the phase comparator A (2) and the phase comparator B (3) becomes small. As shown in FIG. In the device A (2), the phases match.
[0037]
That is, when the signal having the relationship of t1> t2 described above is input with respect to the pulse width, the phase comparator A (2) receives the input signal (S11) and the delayed signal (S12) obtained by delaying the phase. When a predetermined delay is applied, first, it is determined whether the phase of the rising edge of the input signal matches that of the falling edge of the delay signal.
[0038]
When the phases of the rising edge and the falling edge of these signals coincide with each other (see FIG. 4), the UP signal and the DOWN signal that are output from the phase comparator A (2) show the same state. This indicates that there is no phase difference between the two inputs to the phase comparator A (2).
[0039]
At this time, since the phase comparator B (3) sees the phases of the falling edge of the input signal and the rising edge of the delay signal, the phase difference θ shown in FIG. 5 is generated between the two signals. That is, the phase comparator B (3) outputs the UP signal and determines the phase advance. This means that the pulse width at the high level of the input signal is different from the pulse width at the low level. Therefore, in the state shown in FIGS. 4 and 5, it is detected that the pulse width of the input signal is wide at the high level.
[0040]
Similarly, in the case of the pulse waveform shown in FIG. 6, the delay control circuit 1 also includes a delay related to the change in the delay amount executed by the pulse width control circuit based on the UP signal and the DOWN signal output from the phase comparators A and B. Receives a selection signal. Then, by the delay control of the delay control circuit 1, the phase difference between the signals input to the phase comparator A (2) and the phase comparator B (3) is reduced, and as shown in FIG. In (2), the phases match.
[0041]
That is, since the input signal shown in FIG. 6 has a relationship of t1 = t2 with respect to the pulse width, the phase comparator A (2) has the input signal (S11) and the signal (S12) obtained by delaying the phase. When the delay control circuit 1 applies a predetermined delay as a result of the phase comparison, the coincidence of the phases of the rising edge of the input signal and the falling edge of the delay signal is determined.
[0042]
On the other hand, the phase comparator B (3) that looks at the phase of the falling edge of the input signal and the rising edge of the delay signal also determines the coincidence of the phases of both signals, as shown in FIG. Therefore, in this case, both the phase comparators A and B indicate that the UP signal and the DOWN signal are in the same state, and the pulse width at the high level is the same as the pulse width at the low level (both pulse widths are the same). Detection is made.
[0043]
As shown in FIG. 8, even when a signal having a relationship of pulse width t1 <t2 is input, the delay control circuit 1 is output from the phase comparators A and B by the pulse width control circuit. A delay selection signal generated based on the UP signal and the DOWN signal is input. When the delay control circuit 1 controls the change of the delay amount by the delay selection signal, the phase difference between the signals input to the phase comparator A (2) and the phase comparator B (3) becomes small. . Here, as shown in FIG. 9, the phase is matched in the phase comparison circuit B (3).
[0044]
More specifically, when a signal having a pulse width having the relationship of t1 <t2 is input, the phase of the input signal (S11) is compared with the signal (S12) obtained by delaying the phase, and the delay is performed. When a predetermined delay is applied to the input signal by the control circuit 1, the phase comparison circuit B (3) first determines the coincidence of the phase between the falling edge of the input signal and the rising edge of the delay signal. (See FIG. 9).
[0045]
At this time, since the phase comparator A (2) sees the phases of the rising edge of the input signal and the falling edge of the delay signal, it determines the phase advance based on the phase difference θ shown in FIG. Therefore, it is detected that the pulse waveform of the input signal in this case has a wider pulse width at the low level than that at the high level.
[0046]
(2) Pulse width controller
Hereinafter, control of the pulse width in the present embodiment will be described. FIG. 10 is a block diagram showing a configuration of the pulse width control unit 50. As described above, the pulse width control unit 50 includes the pulse width control circuit 55 that determines whether or not the phase difference between the input signal and the delay signal is minimized based on the UP signal / DOWN signal. Therefore, the pulse width control circuit 55 has a configuration in which the output from the pulse width comparison circuit 10 (see FIG. 1) is input.
[0047]
As shown in FIG. 10, the pulse width control circuit 55 is based on the four charge pumps 51 to 54 that receive the UP signal and the DOWN signal (S13 to S16) and the output signals from these charge pumps. The phase difference detector 56 detects the phase difference. Hereinafter, the pulse width control operation including the detection of the phase difference will be described.
[0048]
The UP signal (S13), DOWN signal (S14), UP signal (S15), and DOWN signal (S16) output from the pulse width comparison circuit 10 are input to the charge pumps 51 to 54. Each of these charge pumps 51 to 54 has, for example, the configuration shown in FIG. That is, each charge pump includes a MOS transistor (p-type) 61 that is turned on / off by an UP signal / DOWN signal, a MOS transistor (n-type) 63 that receives a clear signal (CLR), and a connection point between these MOS transistors 61 and 63. It has the capacitor | condenser 64 connected to M (output terminal).
[0049]
For example, when the CLR signal becomes logic high at a certain timing, the MOS transistor (p-type) 62 is turned off, and the MOS transistor (n-type) 63 is turned on, the charge accumulated in the capacitor 64 is transferred to the MOS transistor. 63 is discharged. When the CLR signal becomes logic low after a predetermined time has elapsed, the MOS transistor 62 is turned on and the MOS transistor 63 is turned off.
[0050]
When the logic low UP signal / DOWN signal is input at the next timing, the MOS transistor 61 is turned on, so that the capacitor is connected via the MOS transistor 61 and the MOS transistor 62 already turned on. Charging to 64 is started. As a result, the potential at the output terminal (OUT) gradually increases.
[0051]
When the UP signal / DOWN signal becomes logic high at a certain timing following this, the MOS transistor 61 is turned off, and charging of the capacitor 64 is stopped. As long as this logic state is maintained, the output terminal is held at the voltage when charging is stopped. Further, when the logic low UP signal / DOWN signal is applied to the MOS transistor 61 at the next timing, the capacitor 64 is further charged, and the output voltage further rises.
[0052]
In this way, the output voltage continues to rise every time the UP signal / DOWN signal becomes logic low, and if a logic high CLR signal is input at a certain timing, the output voltage is reduced due to the discharge of the accumulated charge of the capacitor 64. Again, it becomes 0 volts. Here, it is assumed that the CLR signal is repeatedly input at a predetermined interval.
[0053]
Therefore, specific operations of the charge pumps 51 to 54 will be described. First, the input to the charge pumps 51 to 54, that is, the output signal of the pulse width comparison circuit 10 will be described. Here, it is assumed that there is a relationship shown in FIGS. 4 and 5 between the input signals to the phase comparators A and B in the pulse width comparison circuit 10 and the delayed signals. In this case, since there is no phase difference between the two inputs of the phase comparator A, the UP signal and the DOWN signal output therefrom show the same state. Therefore, the state of the output (S13, S14) from the phase comparator A continues to be in a logic high state as shown in FIG. 12, for example.
[0054]
On the other hand, a phase difference θ is generated in the input signal to the phase comparator B as shown in FIG. Therefore, as shown in FIG. 12, the phase comparator B outputs an UP signal having a predetermined pulse width as a signal S15, and the DOWN signal (signal S16) continues to be in a logic high state.
[0055]
When the UP signal / DOWN signal (signals S13 to S16 in FIG. 12) corresponding to the input signal having the relationship shown in FIGS. 4 and 5 is input to the charge pumps 51 to 54, the above-described MOS transistors in the charge pump are connected. The logic state of the output signals S33 to S36 of the charge pump sequentially becomes “0010” (binary) by the on / off operation and charging / discharging of the capacitor arranged at the output terminal.
[0056]
FIG. 13 shows a circuit configuration example of the phase difference detector 56 in the pulse width control circuit 55. The phase difference detector 56 shown in the figure includes NOR gates 71 to 73, an exclusive NOR (Ex-NOR) gate 74, an up / down (U / D) switch 75, and a selector 79. The output signal S33 from the charge pump 51 described above is input to one input terminal of the NOR gate 71 and the selector 79, and the output signal S34 of the charge pump 52 is input to the other input terminal of the NOR gate 71. Is done.
[0057]
Similarly, the signal S35 from the charge pump 53 is input to one input terminal of the NOR gate 72 and also input to the selector 79. The output signal S36 of the charge pump 54 is input to the other input terminal of the NOR gate 72.
[0058]
The output of the NOR gate 71 is directly used as a control input (pulse width detection signal: DET1) S212 to a pulse width conversion circuit, which will be described later, via the output terminal 81 of the phase difference detector 56, and a U / D switcher. 75, and is input to one input terminal of each of the NOR gate 73 and the Ex-NOR gate 74. The output (S213) of the NOR gate 72 is input to the other input terminals of the NOR gate 73 and the Ex-NOR gate 74. The output of the Ex-NOR gate 74 is output from the phase difference detector 56 to the pulse width conversion circuit via the output terminal 83 as the set signal (SET1) S211 for the pulse width conversion circuit.
[0059]
The output from the NOR gate 73 becomes a set signal (SET2) S201 for the delay control circuit 1 and is output to the delay control circuit 1 via the output terminal 84. The output signal S33 from the charge pump 51 or the signal S35 from the charge pump 53 is selected by a selector 79 controlled by an up / down switch 75. The selected signal is output to the delay control circuit 1 via the output terminal 82 as a phase advance / phase lag detection signal (DET2) S202.
[0060]
FIG. 14 is a block diagram showing a specific configuration of the up / down (U / D) switch 75. The switch 75 includes a switch unit 85 that switches a switch by the set signal (SET1) S211 and a flip-flop (FF) 86. As will be described later, the set signal S211 to the pulse width conversion circuit becomes “0” when phase coincidence is detected in either of the phase comparators A and B, and the switch 75 outputs the pulse width at this time. The state of the detection signal (DET1) S212 is held by the FF 86 and is output as a selection signal S203 to the selector 79.
[0061]
Therefore, the operation of the phase difference detector 56 will be described. As described above, if the phase comparators A and B of the pulse width comparison circuit 10 detect the phase advance or phase lag of the input signal, the output signals S33 to S36 of the corresponding charge pumps 51 to 54 are “1”. "become. For example, when there is the relationship shown in FIGS. 4 and 5 between the input signals to the phase comparators A and B and the delay signal, the logic states of the output signals S33 to S36 of the charge pump are “0010”. . Therefore, when signals (S33 to S36) having this logical state are input to the phase difference detector 56, the pulse width detection signal (DET1) S212 is “1”, and the set signals (SET1) S211 and (SET2) S201. Are both “0”.
[0062]
When the relationship shown in FIGS. 8 and 9 exists between the input signal and the delay signal, the logic state of the output signals S33 to S36 of the charge pump is “1000”, so that the signal S212 is “0”. The signals S211 and S201 are both “0”.
[0063]
Thus, the fact that the set signal (SET2) S201 is “0” means that at least one of the phase comparators A and B is in phase. The fact that the set signal S211 is “0” indicates that one of the phase comparators A and B is in phase. In response to this signal, the switch 75 outputs the selection signal S203 to the selector 79, so that the charge pump output of the phase comparator that is in phase is selected. A phase advance / phase lag detection signal (DET2) S202 is output.
[0064]
Further, the pulse width detection signal DET1 (S212) being “1” means that the pulse width at the high level of the input signal is wider than the pulse width at the low level, and conversely, S212 is “0”. This indicates that the low level pulse width is wider than the high level pulse width.
[0065]
When the phases of the input signal and the delay signal match (see FIGS. 6 and 7), all the output signals S33 to S36 of the charge pump become “0”. At this time, since the outputs (S212, S213) of the NOR gates 71 and 72 are both “1”, the output of the Ex-NOR gate 74 is also “1”. Therefore, the set signal (SET1) S211 for the pulse width conversion circuit described later is “1”, unlike the case where the phases do not match.
[0066]
The pulse width control circuit 55 according to the present embodiment determines that the phase is matched in at least one of the phase comparators A and B when the set signal (SET2) S201 is “0”, and the phase advance / Delay is controlled by the phase delay detection signal (DET2) S202. Here, the amount of delay in the delay control circuit 1 is reduced by following the phase with the smaller phase difference between the input signal and the delay signal by the signal DET2 (S202). Therefore, the phase difference detector 56 operates so as to select the phase lead / phase lag in phase (0: phase advance, 1: phase lag).
[0067]
Note that the delay control circuit 1 according to the present embodiment, as can be seen from FIGS. 4 and 5, etc., has the above phase as long as it has a delay amount within a half of the cycle of the input signal. You can compare.
[0068]
(3) Pulse width converter
The pulse width conversion operation in this embodiment will be described below. FIG. 15 is a block diagram showing the overall configuration of the pulse width conversion unit 90 according to the present embodiment. As shown in the figure, the pulse width conversion unit 90 includes a pulse width control unit 50 (see FIGS. 10 and 13) including a pulse width comparison circuit 10 (see FIG. 1) and a pulse width conversion circuit 91. . FIG. 16 is a circuit diagram showing an example of the internal configuration of the pulse width conversion circuit 91.
[0069]
As shown in FIG. 15, the pulse width conversion circuit 91 is supplied with a control signal from the pulse width control circuit 55 constituting the pulse width control unit 50 (more specifically, the phase difference detector 56 shown in FIG. 13). The output set signal (SET1) S211 and pulse width detection signal (DET1) S212 are input. For example, if there is a phase match in one of the phase comparators A and B, the set signal S211 becomes “0”, so the pulse width conversion circuit 91 determines the phase match based on this signal. .
[0070]
At the same time, as described above, the pulse width conversion circuit 91 determines whether DET1 (S212) indicating the width of the high-level or low-level pulse width is “0” or “1”. Control the pulse width. Hereinafter, a specific pulse width conversion operation will be described.
[0071]
The variable delay circuit 93 of the pulse width conversion circuit 91 shown in FIG. 16 performs delay control on the signal (pulse signal having a predetermined cycle and duty ratio) input from the input terminal 92. Here, the counter 98 receives the control signals (the signals S211 and S212 described above) output from the pulse width control circuit 55, and sends a signal corresponding to the logic state to the variable delay circuit 93, whereby the variable delay circuit 93 is transmitted. The delay amount is set at. The signal S301 delayed according to the delay amount is ANDed with the above input signal in the AND gate 94. As a result, an output signal S302 is obtained in which the pulse width at the high level of the signal is narrowed by the delay amount.
[0072]
At the same time, the delayed signal S301 is logically ORed together with the input signal in the OR gate 95. By performing the logical sum operation, a signal in which the high-level pulse width is widened by the delay amount is obtained as the signal S303.
[0073]
Therefore, the selector 96 of the pulse width conversion circuit 91 selects either the signal S302 after the logical product or the signal S303 after the logical sum in accordance with the selection signal (SEL) from the counter 98, and outputs it to the output terminal. Send to 97. That is, when the set signal S211 is “0”, the pulse width conversion circuit 91 can determine the coincidence of the phase in either of the phase comparators A and B, and at the same time, based on DET1 (S212), the high level / The selector 96 is controlled based on the result of judging whether the low level pulse width is wide or narrow.
[0074]
If the above delay control is continuously performed for a predetermined time, and it is detected that SET2 (S201) is "0" and SET1 (S211) is "1", the output of the pulse width conversion circuit 91 ( As the signal S11), a signal having the same pulse width at the high level and the pulse width at the low level is obtained. In other words, with this delay control, a pulse signal with a duty ratio of 50 percent can be obtained from the pulse width conversion circuit according to the present embodiment.
[0075]
Therefore, if another circuit is connected to the output side of the pulse width conversion unit 90 (“pulse width detection signal” in FIG. 15), the circuit performs a predetermined operation in response to a pulse signal having a duty ratio of 50%. It becomes possible.
[0076]
As described above, according to the present embodiment, an input signal and a delayed signal are generated, and the rising edge and the falling edge of each signal are set to two phase comparators A, Compared with B, based on the phase difference detected by the other comparator at the time when the phase is matched by one comparator, the pulse width of the high level and the low level of the input pulse signal Which pulse width is wide or whether the pulse widths of both levels coincide with each other is determined. At this time, since the input pulse signal is input to the same delay control circuit (delay gate) at the same timing, process fluctuations caused by the manufacturing process of the circuit element, operating environment (for example, supplied) The phase comparison can be performed with high accuracy regardless of the power source or the like, and the circuit is symmetrically configured, so that there is no influence by variations in transistor characteristics such as PMOS and NMOS.
[0077]
In particular, if the phase is matched in at least one of the two phase comparators A and B, the coincidence / mismatch of the low level and the high level pulse width can be determined, so that the pulse width can be detected in a short time. it can.
[0078]
Further, according to the present embodiment, a phase comparison between an arbitrary pulse signal (pulse signal having a predetermined cycle and duty ratio) and a signal gradually delayed from the position in phase with the input arbitrary pulse signal is performed. Pulse width detection is performed based on the obtained phase advance signal and phase lag signal, and the pulse width conversion circuit is controlled based on the result to convert the pulse width of the input pulse signal. Thus, it is possible to obtain a signal (pulse signal having a duty ratio of 50 percent) in which the pulse width at the high level is equal to the pulse width at the low level.
[0079]
At this time, since the delay control circuit can perform phase comparison if it has a delay amount within a half cycle of the input signal, coupled with the fact that such phase comparison can be performed in a short time, it is not affected by noise or the like. The effect is that phase comparison can be performed.
[0080]
Note that the control signal as a delay selection signal to the delay control circuit 1 does not necessarily need to be set signal (SET2) and phase detection signal (DET2), and the counter 25 is increased (UP) in one direction. Alternatively, it is possible to determine whether the duty ratio of the input signal is 50% by going down (DOWN).
[0081]
Also, the input waveform of the phase comparator shown in FIGS. 4 to 9 is a waveform when one of the two inputs to the phase comparator is gradually delayed from the same phase as the input signal for convenience of explanation. However, it is obvious that it is not always necessary to start from the state in phase with the input signal.
[0082]
Further, in the pulse width conversion unit 90 shown in FIG. 15 of the above embodiment, even if some circuit is mounted on the elliptical dotted line portion C at the output end of the pulse width conversion circuit 91, the pulse width conversion control is basically performed. Therefore, the presence / absence of a circuit in the dotted line portion C is irrelevant to the pulse width conversion.
[0083]
【The invention's effect】
As described above, according to the present invention, two phase control means and one delay control means are provided, an input signal is delayed by this delay control means, and the phase between both signals is delayed by one phase control means. When the phase match is determined, the other phase control means determines the phase difference between the two signals and outputs the phase comparison result. That is, one phase control means detects the rising edge of the input signal and detects the falling edge of the delay signal, and the other phase control means detects the falling edge of the input signal and the rising edge of the delay signal. By operating to detect edges, input signals can be input to a single delay control means at the same timing, and high-accuracy phase comparison is possible regardless of process variations and operating environment of the means in the semiconductor integrated circuit. It can be performed.
[0084]
In addition, there is provided means for performing a predetermined logical operation based on the phase advance signal as the phase comparison result and the phase delay signal and outputting a pulse width control signal, and based on the pulse width control signal, the delay control means Since the delay amount is variable, the phase comparison result in the other phase control means is detected and output in a state where there is no phase difference in one of the phase control means. Can be detected.
[0085]
Further, it comprises pulse width conversion means for changing and outputting the pulse width of the input signal, and the conversion means receives the pulse width conversion signal based on the phase comparison result by the two phase control means and receives the pulse width of the input signal. By operating so as to change, it is possible to easily generate a pulse signal having an equal pulse width at the high level and a pulse width at the low level (duty ratio of 50 percent) for any input signal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a pulse width comparison circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a delay control circuit.
FIG. 3 is a block diagram showing a configuration of a delay selection circuit.
FIG. 4 is a diagram showing a first operation timing waveform (part 1) in the pulse width comparison circuit;
FIG. 5 is a diagram showing a first operation timing waveform (part 2) in the pulse width comparison circuit;
FIG. 6 is a diagram showing a second operation timing waveform (part 1) in the pulse width comparison circuit;
FIG. 7 is a diagram showing a second operation timing waveform (part 2) in the pulse width comparison circuit;
FIG. 8 is a diagram showing a third operation timing waveform (part 1) in the pulse width comparison circuit;
FIG. 9 is a diagram showing a third operation timing waveform (part 2) in the pulse width comparison circuit;
FIG. 10 is a block diagram showing a configuration of a pulse width control unit according to the embodiment of the present invention.
FIG. 11 is a diagram illustrating a configuration example of a charge pump.
12 is a diagram illustrating an example of an output state (logic state) of a phase comparator A. FIG.
FIG. 13 is a diagram showing a circuit configuration of a phase difference detector in a pulse width control circuit.
FIG. 14 is a block diagram showing a specific configuration of an up / down (U / D) switch.
FIG. 15 is a block diagram showing an overall configuration of a pulse width conversion unit according to the embodiment.
FIG. 16 is a circuit diagram showing an example of an internal configuration of a pulse width conversion circuit.
FIG. 17 is a diagram showing a configuration of a conventional pulse signal generation circuit.
[Explanation of symbols]
1 Delay control circuit
2,3 phase comparator
10 Pulse width comparison circuit
21a, 21b Delay selection circuit
31 Buffer circuit
32, 79, 96 selector
50 Pulse width controller
51-54 Charge pump
55 Pulse width control circuit
56 Phase detector
61 MOS transistor (p-type)
63 MOS transistor (n-type)
64 capacitors
73 NOR gate
74 Ex-NOR gate
75 Up / down switcher
86 Flip Flop (FF)
90 Pulse width converter
91 Pulse width conversion circuit
93 Variable delay circuit
98 counter

Claims (11)

Delay control means for applying a predetermined delay to the input signal;
First phase control means using the input signal as a first input signal and the delayed signal as a second input signal;
A second phase control means using the input signal as a first input signal and the delayed signal as a second input signal;
The first phase control means detects a rising edge of the first input signal and detects a falling edge of the second input signal, and detects the phase of the first and second input signals. And the second phase control means detects the falling edge of the first input signal and detects the rising edge of the second input signal. A semiconductor integrated circuit characterized in that the phases of two input signals are compared and the comparison result is output as a phase comparison result between the first and second input signals . When it is determined by the second phase control means that there is no phase difference between the first and second input signals, the input signal is determined to be a pulse signal having a duty ratio of 50%. The semiconductor integrated circuit according to claim 1 . 3. The semiconductor integrated circuit according to claim 2 , wherein the first and second phase control means comprise a phase comparison circuit that compares the phases of the first and second input signals. 4. The semiconductor integrated circuit according to claim 3 , wherein the phase comparison circuit outputs a phase advance signal or a phase delay signal as the phase comparison result. It said delay control means, a semiconductor integrated circuit according to any one of claims 1 4, characterized in that delaying the input signal by a predetermined time. It said delay control means, a semiconductor integrated circuit according to any one of claims 1 4, characterized in that delaying the input signal according to the delay amount selected from a plurality of delay amount set in advance. The delay control further comprises means for performing a logical operation based on the phase advance signal and the phase delay signal as the phase comparison result and outputting a pulse width control signal including a pulse delay control signal and a pulse width conversion control signal. 7. The semiconductor integrated circuit according to claim 6 , wherein the means selects the delay amount based on the pulse delay control signal. 8. The semiconductor integrated circuit according to claim 7 , wherein the delay amount is equal to or less than half of the period of the input signal. Further comprising a pulse width converting means changes to output a pulse width of the input signal, any one of claims 1 to 8, a signal obtained by changing the pulse width, characterized in that said first input signal 2. A semiconductor integrated circuit according to item 1 . 10. The semiconductor integrated circuit according to claim 9, wherein the pulse width conversion means changes the pulse width of the input signal based on the pulse width conversion control signal. The pulse width converting means, said pulse width of the pulse width the input signal a conversion control signal based and variable delay, according to claim 10, wherein the duty ratio and outputs the 50% of the pulse signal Semiconductor integrated circuit.

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