JP3394466B2 - External load capacitance detection circuit and feedback signal generation method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external load capacitance of a semiconductor drive circuit, and more particularly to an external load capacitance detection circuit and a feedback signal generation method in the external load capacitance detection circuit.

[0002]

2. Description of the Related Art Recent semiconductor circuits are required to have a high operating speed and a low supply voltage. In particular, a wide range of adaptability is required for fluctuations in the load connected to the semiconductor circuit.

As the operating speed of the semiconductor circuit becomes faster and the supply voltage becomes lower, the semiconductor circuit needs to maintain the optimum driving capability even if the external load connected to the driving circuit changes. . Generally, the operation delay of the drive circuit is
Although it is often desired to be small, it is necessary to increase the semiconductor drive capability of the drive circuit for that purpose. However, in that case, there is a problem in that noise is likely to occur during operation and the through current increases. Therefore, it is desirable to keep the operation delay of the drive circuit at its optimum value.
When the external load changes significantly, the designer has to consider and consider these matters considerably. Further, as a result of the drive circuit being required to have wide versatility, the drive circuit is required to suppress fluctuation due to a load connected to the outside thereof. These requirements make the design of semiconductor circuits difficult.

6 and 7 are diagrams showing the configuration of a conventional example of a drive circuit. FIG. 8 is a diagram for explaining the operation of FIG. Figure 6
The diagram showing the configuration of the above is a configuration diagram of the output buffer circuit disclosed in Japanese Patent Laid-Open No. 9-186577. The output buffer circuit was developed as a means for obtaining an optimum driving capability even when the size of the external load changes. The output buffer circuit disclosed in Japanese Patent Application Laid-Open No. 9-186577 describes that an output signal is fed back and the driving capability is controlled from the output delay time.

Japanese Unexamined Patent Publication No. 6-334499 shown in FIGS.
The publication discloses a trigger circuit for detecting a slew rate state. The trigger circuit measures the transition time between the set levels of the signal to be measured, and controls the rising edge of the trigger according to the time width.

[0006]

However, JP-A-9-1
The output buffer circuit disclosed in Japanese Patent No. 86577 has the following problems. In general, the output buffer circuit has a dull output waveform in a high load state, and it is difficult to quickly detect a potential change when the output level starts to change. In Japanese Patent Laid-Open No. 9-186577, in such a case, by switching the size of the transistor in the output stage,
The drive capability of the output buffer circuit is increased so that the output waveform is not dulled until the potential change rate of the output waveform is detected. However, in such a control method, the driving capability of the output buffer circuit at the initial stage is excessive, and noise is likely to occur.

Further, since the external output signal of the output buffer circuit is fed back as it is, extra through current increases.

Further, the trigger circuit disclosed in Japanese Patent Laid-Open No. 6-334499 has the following problems.
When operating the trigger circuit at a low voltage, it is difficult to set a plurality of determination voltages of different levels. Also,
Since a delay time is involved in detecting each of the different levels, it is difficult to use it in a device that controls the operation during the output change.

An object of the present invention is to provide an external load capacitance detection circuit and a feedback signal generation method therefor, which detects a potential change of an output signal at an early stage when the output signal starts to change regardless of the size of the external load. is there.

[0010]

An external load capacitance detection circuit according to the present invention is an external load capacitance detection circuit for detecting an external load capacitance driven by an output of an external load drive circuit which changes according to an input signal. A buffer circuit that operates in parallel with the external load drive circuit by inputting the input signal, and a coupling capacitance for adding and outputting the output of the external load drive circuit to the buffer circuit output,
A feedback signal generation circuit provided in parallel with the external load drive circuit with respect to the external load capacitance, a delay element for inputting the input signal, delaying the output by a predetermined time, and outputting the input signal, the delay element output and the feedback generation And a comparison circuit which inputs the circuit output, compares them when the delay element output changes, and outputs the magnitude relationship.

An external load capacitance detection circuit according to another aspect of the present invention is an external load capacitance detection circuit for detecting an external load capacitance driven by an output of an external load drive circuit which changes according to an input signal. The external load capacitance is composed of a buffer circuit that receives an input signal and operates in parallel with the external load drive circuit, and a coupling capacitance for adding and outputting the output of the external load drive circuit to the output of the buffer circuit. A feedback signal generating circuit provided in parallel with the external load driving circuit, a plurality of delay elements for inputting the input signal, delaying each by a different predetermined time and outputting the delayed signal, and corresponding to the plurality of delay elements. A plurality of delay elements are provided, each delay element output and the feedback generation circuit output are input, and when the delay element output changes, these are compared, And having a comparator circuit for outputting a magnitude relation.

An external load capacitance detecting method according to the present invention is an external load capacitance detecting method for detecting an external load capacitance driven by an output of an external load drive circuit which changes according to an input signal, wherein the input signal is input. A buffer circuit that operates in parallel with the external load drive circuit and a coupling capacitor for adding the output of the external load drive circuit to the output of the buffer circuit and outputting the result. A feedback signal generation circuit provided in parallel with the external load drive circuit is provided, the input signal is input, delayed for a predetermined time and output, and the output of the feedback generation circuit and the delay output change at the time when the delay output changes. Characterized by comparing relationships.

An external load capacitance detecting method according to another aspect of the present invention is an external load capacitance detecting method for detecting an external load capacitance driven by an output of an external load drive circuit which changes according to an input signal. The external load capacitance is composed of a buffer circuit that receives an input signal and operates in parallel with the external load drive circuit, and a coupling capacitance for adding and outputting the output of the external load drive circuit to the output of the buffer circuit. A feedback signal generating circuit provided in parallel with the external load driving circuit, the input signal is input, and the input signal is delayed by different predetermined times, and each delay output and the feedback generating circuit output are delayed by the delay output. It is characterized by comparing the magnitude relationship at the time of change.

[0014]

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Referring to the drawings, an embodiment of the present invention shows an external load drive circuit 1
1, an input terminal 12 to which the internal signal IN is connected, an output terminal 13 to which the external load CL is connected, and an external load capacitance detection circuit 10 of the present invention connected in parallel to the external load drive circuit 11. Has been done.

The external load capacitance detection circuit 10 includes a feedback circuit including a buffer circuit 1 operating in parallel with the external load drive circuit 11 and a coupling capacitance (CC) 2 connected to an output terminal 13 of the external load drive circuit 11. It comprises a signal generating circuit 20, a delay circuit 3 connected to the input terminal 12 and having a constant delay time, and a comparison circuit 4 which receives the feedback signal of the feedback signal generating circuit 20 and the output signal of the delay circuit 3 as inputs. There is.

In the feedback signal generation circuit 20, the buffer circuit 1 and the coupling capacitor 2 are connected, and the feedback signal from the connection point is connected to the comparison circuit 4. The internal signal IN is connected to the input terminal of the delay circuit 3.

The first input terminal of the comparison circuit 4 is connected to the connection point between the buffer circuit 1 and the coupling capacitor 2, and the second input terminal
The input terminal of is connected to the output terminal of the delay circuit 3. The comparison circuit 4 compares the feedback signal from the connection point between the buffer circuit 1 and the coupling capacitor 2 with the signal delayed from the delay circuit 3 for a certain period of time, and outputs the magnitude relationship as a preset signal.

Here, after the internal signal IN is input,
It is assumed that the time until the output of the external load drive circuit 11 starts to change is equal to the time until the output of the buffer circuit 1 starts to change, and the delay time TpdS is designed to be equal.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a waveform diagram showing the operation at each point in FIG. 1 when the internal signal IN changes from'L 'to'H'. VTH shown in the figure is the input threshold voltage of the comparison circuit 4, b2 is the output signal of the buffer circuit 1, d is the output signal of the delay circuit 3, and b2 'is the coupling capacitance (CC) 2 and the output of the buffer circuit 1. The output signal of the buffer circuit 1 when connected between the low potential power supplies is shown.

After the internal signal IN changes from "L" to "H" and the time TpdS elapses, the output signal OUT of the external load drive circuit 11 and the output signal b2 of the buffer circuit 1 change from "L" to "H". Begins to change.

External load drive circuit 11 and buffer circuit 1
Needs to charge the external load CL and the coupling capacitance CC, respectively, and therefore changes more gently than the internal signal IN.

The input parasitic capacitance of the comparator 4 is CHin, the drive current of the external load drive circuit 11 is IB1, the buffer circuit 1
If the drive current of is constant at IB2 and CHin << CC << CL CC / IB2 << CL / IB1, the voltage Vb1t of the output signal OUT of the external load drive circuit 11 at the time t after the start of charging,
The voltage Vb2t of the output signal b2 of the buffer circuit 1 can be expressed as follows.

Vb1t = t × IB1 / CL Vb2t = t × IB2 / CC + Vb1t (where t × IB2 / CC is a buffer circuit when the coupling capacitance CC is connected between the output of the buffer circuit 1 and the low potential power supply) 1 from the start of charging of the output signal b2 '
It can be replaced with the voltage Vb2′t at the time when the time has elapsed. That is, the output signal b2 of the buffer circuit 1 is the output signal OU
T is added to increase the speed of change.

FIG. 3 shows the relationship between the output signal OUT of the external load drive circuit 11 with respect to the change of the external load CL and the delay time Tpd until the output signal b2 of the buffer circuit 1 changes to the input threshold voltage VTH of the comparison circuit 4. Indicates.

The output signal d of the delay circuit 3 is the internal signal IN.
Changes from'L 'to'H' and then changes from'L 'to'H' after a preset time elapses.

The output signal Cont of the comparator 4 changes at the time when the output signal d of the delay circuit 3 changes from'L 'to'H'.
"H" when the output signal b2 of the buffer circuit 1 is "L"
When the output signal b2 of the buffer circuit 1 is "H", "L" is output.

FIG. 4 is a block diagram of another embodiment of the present invention. In the figure, this embodiment has an external load drive circuit 11,
The input terminal 12 to which the internal signal IN is connected, and the external load C
Output terminal 13 to which L is connected and external load drive circuit 1
1. External load capacitance detection circuit 3 of the present invention connected in parallel to 1
It is composed of 0 and 0.

The external load capacitance detection circuit 30 includes a feedback circuit including a buffer circuit 1 operating in parallel with the external load drive circuit 11 and a coupling capacitance (CC) 2 connected to an output terminal 13 of the external load drive circuit 11. The signal generating circuit 20, a plurality of delay circuits 31 to 3n connected to the input terminal 12 and having a constant delay time, the feedback signal of the feedback signal generating circuit 20, and the delay circuits 31 to 3n.
It is composed of a plurality of comparison circuits 41 to 4n to which the output signal of 4 is input.

In the feedback signal generation circuit 20, the buffer circuit 1 and the coupling capacitor 2 are connected, and the feedback signal from the connection point is commonly used by the comparison circuits 41 to 41.
4n. The internal signal IN is commonly connected to the input terminals of the delay circuits 31 to 3n. Delay circuit 31-
3n is composed of delay elements having respective different delay times.

The first input terminals of the comparison circuits 41 to 4n are connected to the connection point between the output terminal of the buffer circuit 1 and the coupling capacitor 2, and the second input terminals are connected to the output terminals of the delay circuits 31 to 3n. Has been done. The comparison circuits 41 to 4n compare the feedback signal from the connection point between the buffer circuit 1 and the coupling capacitor 2 with the signals from the delay circuits 31 to 3n which are delayed by different times, and the magnitude relation thereof is preset. Output as a signal.

Next, a method of generating a feedback signal in the external load capacitance detection circuit connected in parallel with the external load drive circuit of the present invention will be described with reference to the drawings. FIG. 5 is a flowchart showing a method of generating a feedback signal in the external load capacitance detection circuit.

As shown in the figure, the operation flow of this embodiment is such that an output signal of a buffer circuit which receives the same internal signal as the external load drive circuit and an output signal of a coupling capacitor connected to the output of the external load drive circuit. A generation step (S10) of making a feedback signal, and a comparison step (S) of comparing an internal signal with an output signal through a delay element having a constant delay time and a feedback signal and outputting a magnitude relation thereof.
20) and.

In the generating step (S10), the same internal signal as the external load drive circuit is applied to the buffer circuit as an input signal (S11), the output of the external load drive circuit is output through the coupling capacitor (S12), and the buffer is output. The output of the circuit and the output via the coupling capacitance are connected to generate a feedback signal (S13). Comparison step (S2
0) gives an internal signal to a delay element having a preset delay time (S21), compares the feedback signal with the output signal of the delay element (S22), and as a result of comparison, if the feedback is early, Is set to "H", and if it is slow, it is determined to be "L", and the output of "H" is sent at the timing of the signal change of the earlier one (S23). The reverse may also be possible.

[0036]

EXAMPLE A delay time TpdB1 from the change of the internal signal IN to the output signal OUT of the external load drive circuit 11 becoming VTH and the output signal b2 of the buffer circuit 1 being VTH.
The delay time TpdB2 until it becomes is as follows.

TpdB1 = Vb1t × CL / IB1 + TpdS TpdB2 = Vb2t / (IB2 / CC + IB1 / C
L) As a specific numerical example, power supply voltage VDD = 3V, VTH = VDD / 2 = 1.5V IB1 = 25.0 mA, IB2 = 0.1 mA, CC =
When 0.5 pF and TpdS = 2.0 nS, when CL = 100 pF, TpdB1 = 8.0 nS, TpdB2 = 5.3 nS, and when CL = 200 pF, TpdB1 = 14.0 nS and TpdB2 = 6.6 nS. .

[0038]

According to the present invention, by adding the output signal of the buffer circuit operating in parallel to the output signal OUT of the external load drive circuit to form a feedback signal, the initial stage in which the output signal OUT starts to change. Therefore, there is an effect that the potential change can be detected.

That is, the external load capacitance detection circuit of the present invention detects the potential change at the initial stage when the output signal OUT starts to change, regardless of the size of the external load, and thus the degree of freedom of the control method is increased. Increase. As a result, if the external load capacitance detection circuit is used to control the driving force of the external load drive circuit,
The initial driving force can be reduced. Therefore, when the driving force of the external load driving circuit is insufficient, by adding it as a driving element, it is possible to avoid generation of noise due to excessive driving force.

Further, there is an effect that the bluntness of the feedback signal is reduced and the generation of extra through current due to the input of the intermediate potential can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation at each point in FIG. 1 when the internal signal IN changes from'L 'to'H'.

FIG. 3 is a diagram showing a relationship between an output signal OUT of an external load drive circuit and a delay time Tpd until an input threshold voltage VTH of a comparison circuit of an output signal b2 of a buffer circuit with respect to a change of an external load CL. .

FIG. 4 is a configuration diagram of another embodiment of the present invention.

FIG. 5 is a flowchart showing a method of generating a feedback signal in the external load capacitance detection circuit.

FIG. 6 is a diagram showing a configuration of a first conventional example.

FIG. 7 is a diagram showing a configuration of a second conventional example.

FIG. 8 is a diagram for explaining the operation of FIG.

[Explanation of symbols]

1 buffer circuit 2 coupling capacity 3 delay circuit 4 Comparison circuit 10 External load capacitance detection circuit 11-part load drive circuit 12 input terminals 13 output terminals 20 Feedback signal generation circuit

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Claims (4)

(57) [Claims] 1. An external load capacitance detection circuit for detecting an external load capacitance driven by an output of an external load drive circuit, which changes according to an input signal, the input signal being input to the external load drive circuit. A buffer circuit that operates in parallel and a coupling capacitor for adding the output of the external load drive circuit to the output of the buffer circuit and outputting the buffer circuit are provided in parallel with the external load drive circuit with respect to the external load capacitance. A feedback signal generating circuit, a delay element for inputting the input signal, delaying for a predetermined time and outputting, and inputting the delay element output and the feedback generating circuit output, at the time when the delay element output changes An external load capacitance detection circuit comprising: a comparison circuit that compares these and outputs the magnitude relation. 2. An external load capacitance detection circuit for detecting an external load capacitance driven by an output of an external load drive circuit, which changes according to an input signal, the input signal being input to the external load drive circuit. A buffer circuit that operates in parallel and a coupling capacitor for adding the output of the external load drive circuit to the output of the buffer circuit and outputting the result are provided in parallel with the external load drive circuit with respect to the external load capacitance. Feedback signal generating circuit, a plurality of delay elements for inputting the input signal, delaying different predetermined times for output, and a plurality of delay elements corresponding to the plurality of delay elements, each delay element output and the feedback Input the output of the generator circuit,
An external load capacitance detection circuit, comprising: a comparison circuit that compares the delay element outputs when the delay element outputs change and outputs the magnitude relationship. 3. An external load capacitance detection method for detecting an external load capacitance driven by an output of an external load drive circuit, which changes according to an input signal, the input signal being input to the external load drive circuit. A buffer circuit that operates in parallel and a coupling capacitor for adding the output of the external load drive circuit to the output of the buffer circuit and outputting the buffer circuit are provided in parallel with the external load drive circuit with respect to the external load capacitance. A feedback signal generating circuit provided, inputting the input signal, delaying it for a predetermined time, and outputting it.
A method for detecting an external load capacitance, comprising comparing the output of the feedback generating circuit and the magnitude relationship thereof at the time when the delay output changes. 4. An external load capacitance detection method for detecting an external load capacitance driven by an output of an external load drive circuit which changes according to an input signal, the input signal being input to the external load drive circuit. A buffer circuit that operates in parallel and a coupling capacitor for adding the output of the external load drive circuit to the output of the buffer circuit and outputting the buffer circuit are provided in parallel with the external load drive circuit with respect to the external load capacitance. A feedback signal generating circuit is provided, the input signal is input, each is delayed for a different predetermined time, and each delay output and the output of the feedback generating circuit are compared in magnitude relation at the time when the delay output changes. An external load capacity detection method characterized by