JP2000269796A - External load capacitance detection circuit and method for generating feedback signal thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an external load capacitance detection circuit that detects the change in a level at an initial stage, when an output signal starts changing independently of the scale of an external load. SOLUTION: This external load capacitance detection circuit is designed to be an external load capacitance detection circuit 10 that is connected in parallel with an external load drive circuit 11, is provided iwht a buffer circuit 1 receiving the same internal signal as that of the external load drive circuit 11, and a comparator that compares a feedback signal via a connecting point between the buffer circuit 1 and a coupling capacitor 2 connected to an output of the external load drive circuit 11 with an output signal of a delay element receiving the internal signal and provides an output denoting their magnitude relation. The comparator 4 detects an output change in the external load drive circuit 11 in an initial stage of the output change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an external load capacitance of a semiconductor drive circuit, and more particularly to an external load capacitance detection circuit and a method of generating a feedback signal in the external load capacitance detection circuit.

[0002]

2. Description of the Related Art Recent semiconductor circuits are required to have higher operating speeds and lower supply voltages. In particular, a wide range of adaptability is required for fluctuations in the load connected to the semiconductor circuit.

As the operating speed of a semiconductor circuit increases and the supply voltage decreases, the semiconductor circuit needs to maintain an optimum driving capability even when an external load connected to the driving circuit changes. . Generally, the operation delay of the drive circuit is
Although it is often desired to be small, it is necessary to increase the driving capability of the driving circuit for driving the semiconductor. However, in that case, there are problems such as easy generation of noise at the time of operation and increase of a through current. Therefore, it is desirable that the operation delay of the drive circuit be kept at its optimum value.
In the case where the external load changes greatly, consideration and consideration for these become a considerable load for the designer. Furthermore, as a result of the need for a wide versatility of the drive circuit, the drive circuit is required to suppress fluctuation due to a load connected to the outside. These requirements make the design of semiconductor circuits difficult.

FIGS. 6 and 7 are diagrams showing the configuration of a conventional example of a driving circuit. FIG. 8 is a diagram for explaining the operation of FIG. FIG.
FIG. 1 shows the configuration of the output buffer circuit disclosed in Japanese Patent Application Laid-Open No. 9-186577. The output buffer circuit has been developed as a means for obtaining an optimum driving capability even if the magnitude of the external load changes. It is described that the output buffer circuit disclosed in Japanese Patent Application Laid-Open No. 9-186577 feeds back an output signal and controls the driving capability from the output delay time.

Japanese Patent Laid-Open No. 6-334499 shown in FIGS.
The publication discloses a trigger circuit for detecting a slew rate state. The trigger circuit measures a transition time between set levels of a signal to be measured, and controls the rise of the trigger according to the time width.

[0006]

SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open No. 9-1
The output buffer circuit disclosed in JP-A-86577 has the following problems. In general, the output buffer circuit has a dull output waveform in a high-load state, and it is difficult to quickly capture a potential change when the output level starts to change. According to Japanese Patent Application Laid-Open No. 9-186577, in such a case, by switching the size of the transistor in the output stage,
The drive capability of the output buffer circuit is enhanced so that the output waveform is controlled so as not to be dull until the potential change rate of the output waveform is detected. However, in such a control method, the initial output buffer circuit has an excessive driving capability, which often causes noise.

Further, since the external output signal of the output buffer circuit is fed back as it is, an extra through current increases.

Further, the trigger circuit disclosed in Japanese Patent Laid-Open No. 6-334499 has the following problems.
When operating the trigger circuit at a low voltage, it is difficult to set a plurality of determination voltages of different levels. Also,
Since the detection of each different level involves a delay time, it is difficult to use it for a device that controls the operation during the output change.

SUMMARY OF THE INVENTION An object of the present invention is to provide an external load capacitance detecting circuit for detecting a potential change at an initial stage when an output signal starts to change regardless of the size of an external load, and a feedback signal generating method thereof. is there.

[0010]

An external load capacitance detecting circuit according to the present invention is an external load capacitance detecting circuit connected in parallel with an external load driving circuit, and detects a rising signal connected in parallel with the external load driving circuit. And a comparing means for outputting a magnitude relationship between the feedback signal generated by the feedback signal generating means and the input signal delayed via the delay element.

The feedback signal generating means includes a buffer circuit having the same internal signal as the external load driving circuit as an input signal, and a coupling capacitor connected between the output of the external load driving circuit and the output of the buffer circuit. And a feedback signal is obtained via a connection point between the buffer circuit and the coupling capacitor.

The comparing means for outputting the magnitude relation is a delay element for receiving an internal signal and adding a predetermined delay time to output a signal, an output signal of the feedback signal generating means and an output of the delay element. And a comparator for comparing a signal with a signal to output a magnitude relationship between the signals and detecting an output change of the external load driving circuit at an initial stage.

The method for generating a feedback signal in the external load capacitance detecting circuit according to the present invention includes: a buffer circuit having the same internal signal as an external load driving circuit as an input signal;
A feedback signal generating step including a coupling capacitor connected between an output of the external load driving circuit and an output of the buffer circuit, wherein a feedback signal is obtained via a connection point between the buffer circuit and the coupling capacitor; and an input of an internal signal. A delay element that adds a preset delay time and outputs a signal, and a comparator that compares an output signal of the feedback signal generation unit and an output signal of the delay element and outputs a magnitude relationship thereof, A comparing step of outputting a magnitude relationship for detecting an output change of the external load driving circuit at an initial stage.

According to the method of generating a feedback signal in the external load capacitance detecting circuit of the present invention, the same internal signal as that of the external load driving circuit is supplied to the buffer circuit as an input signal, and the output of the external load driving circuit is output via the coupling capacitance. ,
The output of the buffer circuit and the output via the coupling capacitor are connected to generate a feedback signal, an internal signal is applied to a delay element having a preset delay time, the feedback signal is compared with the output signal of the delay element, As a result of the comparison, a predetermined state indicating a slow speed is transmitted.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, an embodiment of the present invention is an external load driving circuit 1.
1; an input terminal 12 to which an internal signal IN is connected; an output terminal 13 to which an external load CL is connected; and an external load capacitance detection circuit 10 of the present invention connected in parallel to the external load drive circuit 11. Have been.

The external load capacitance detecting circuit 10 includes a feedback circuit including a buffer circuit 1 operating in parallel with the external load driving circuit 11 and a coupling capacitance (CC) 2 connected to an output terminal 13 of the external load driving circuit 11. It comprises a signal generation circuit 20, a delay circuit 3 having a fixed delay time connected to the input terminal 12, and a comparison circuit 4 which receives as input the feedback signal of the feedback signal generation circuit 20 and the output signal of the delay circuit 3. I have.

In the feedback signal generation circuit 20, the buffer circuit 1 and the coupling capacitor 2 are connected, and a feedback signal from the connection point is connected to the comparison circuit 4. An internal signal IN is connected to an input terminal of the delay circuit 3.

A first input terminal of the comparison circuit 4 is connected to a connection point between the buffer circuit 1 and the coupling capacitor 2, and the second input terminal
Is connected to the output terminal of the delay circuit 3. The comparison circuit 4 compares a feedback signal from a connection point between the buffer circuit 1 and the coupling capacitor 2 with a signal delayed for a predetermined time from the delay circuit 3 and outputs a magnitude relationship as a preset signal.

Here, after the internal signal IN is input,
It is assumed that the time until the output of the external load drive circuit 11 starts to change and the time until the output of the buffer circuit 1 starts to change are equal, and the delay time TpdS is designed to be equal.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a waveform diagram showing an operation at each point in FIG. 1 when the internal signal IN changes from “L” to “H”. VTH shown in the figure is an input threshold voltage of the comparison circuit 4, b2 is an output signal of the buffer circuit 1, d is an output signal of the delay circuit 3, and b2 'is a coupling capacitance (CC) 2 is an output signal of the buffer circuit 1. 7 shows an output signal of the buffer circuit 1 when connected between low-potential power supplies.

After a lapse of time TpdS after the internal signal IN changes from “L” to “H”, the output signal OUT of the external load driving circuit 11 and the output signal b2 of the buffer circuit 1 change from “L” to “H”. Start to change.

External load driving circuit 11 and buffer circuit 1
Have to be charged with the external load CL and the coupling capacitance CC, respectively, and thus change more gently than the internal signal IN.

The input parasitic capacitance of the comparator 4 is CHin, the driving current of the external load driving circuit 11 is IB1, and the buffer circuit 1 is
Is constant at IB2 and CHin << CC << CL CC / IB2 << CL / IB1, assuming that the voltage Vb1t of the output signal OUT of the external load driving circuit 11 at the time point t has elapsed since the start of charging,
Voltage Vb2t of output signal b2 of buffer circuit 1 can be expressed as follows.

Vb1t = t × IB1 / CL Vb2t = t × IB2 / CC + Vb1t (where t × IB2 / CC is a buffer circuit when the coupling capacitor CC is connected between the output of the buffer circuit 1 and the low potential power supply) 1 from the start of charging of the output signal b2 '
It can be replaced with the voltage Vb2't at the time when the elapsed time. That is, the output signal b2 of the buffer circuit 1 is the output signal OU
T is added and the change speed increases.

FIG. 3 shows the relationship between the output signal OUT of the external load driving circuit 11 and the delay time Tpd until the output signal b2 of the buffer circuit 1 changes to the input threshold voltage VTH of the comparison circuit 4 with respect to the change of the external load CL. Is shown.

The output signal d of the delay circuit 3 is the internal signal IN
Changes from 'L' to 'H' after a predetermined time elapses after 'changes from' L 'to' H '.

The output signal Cont of the comparator 4 changes when the output signal d of the delay circuit 3 changes from “L” to “H”.
"H" when the output signal b2 of the buffer circuit 1 is "L"
And outputs “L” when the output signal b2 of the buffer circuit 1 is “H”.

FIG. 4 is a block diagram of another embodiment of the present invention. In the figure, the present embodiment has an external load driving circuit 11;
An input terminal 12 to which the internal signal IN is connected and an external load C
L and the external load driving circuit 1
External load capacitance detection circuit 3 of the present invention connected in parallel to 1
0.

The external load capacitance detecting circuit 30 includes a feedback circuit including a buffer circuit 1 operating in parallel with the external load driving circuit 11 and a coupling capacitance (CC) 2 connected to an output terminal 13 of the external load driving circuit 11. A signal generation circuit 20, a plurality of delay circuits 31 to 3n connected to the input terminal 12 and having a fixed delay time, a feedback signal of the feedback signal generation circuit 20, and delay circuits 31 to 3n
, And a plurality of comparison circuits 41 to 4n to which the output signals of the above are input.

The feedback signal generation circuit 20 is connected to the buffer circuit 1 and the coupling capacitor 2, and the feedback signals from the connection point are shared by the comparison circuits 41-41.
4n. The internal signals IN are commonly connected to the input terminals of the delay circuits 31 to 3n. Delay circuits 31-
3n is composed of delay elements having different delay times determined respectively.

The first input terminals of the comparison circuits 41 to 4n are connected to the connection point between the output terminal of the buffer circuit 1 and the coupling capacitor 2, and the second input terminals are connected to the output terminals of the delay circuits 31 to 3n. Have been. The comparison circuits 41 to 4n compare the feedback signal from the connection point between the buffer circuit 1 and the coupling capacitor 2 with the signals delayed by different times from the delay circuits 31 to 3n, and their magnitude relations are set in advance. Output as a signal.

Next, a method of generating a feedback signal in the external load capacitance detecting circuit connected in parallel with the external load driving circuit of the present invention will be described with reference to the drawings. FIG. 5 is a flowchart showing a feedback signal generation method in the external load capacitance detection circuit.

As shown in the figure, the operation flow of the present embodiment is based on the assumption that the output signal of a buffer circuit which receives the same internal signal as the external load driving circuit and the coupling capacitance connected to the output of the external load driving circuit. A generating step (S10) as a feedback signal, and a comparing step (S10) of comparing an output signal through a delay element having a fixed delay time with an internal signal and a feedback signal to output a magnitude relation therebetween.
20).

In the generation step (S10), the same internal signal as that of the external load driving circuit is supplied to the buffer circuit as an input signal (S11), and the output of the external load driving circuit is output via a coupling capacitor (S12). The output of the circuit and the output via the coupling capacitor are connected to generate a feedback signal (S13). Comparison step (S2
0) gives the internal signal to the delay element having a preset delay time (S21), compares the feedback signal with the output signal of the delay element (S22), and as a result of the comparison, if the feedback is earlier, Is determined to be "H", and if it is late, it is determined to be "L", and the output of "H" is transmitted at the timing of the earlier signal change (S23). Alternatively, the reverse may be applied.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A delay time TpdB1 from the time when an internal signal IN changes to the time when an output signal OUT of the external load driving circuit 11 becomes VTH, and the output signal b2 of the buffer circuit 1 is VTH.
The delay time TpdB2 until becomes as follows.

TpdB1 = Vb1t × CL / IB1 + TpdS TpdB2 = Vb2t / (IB2 / CC + IB1 / C
L) As specific numerical examples, power supply voltage VDD = 3V, VTH = VDD / 2 = 1.5V IB1 = 25.0mA, IB2 = 0.1mA, CC =
When 0.5 pF and TpdS = 2.0 nS, when CL = 100 pF, TpdB1 = 8.0 nS, TpdB2 = 5.3 nS, and when CL = 200 pF, TpdB1 = 14.0 nS and TpdB2 = 6.6 nS. .

[0038]

According to the present invention, the output signal OUT of the external load driving circuit is added to the output signal of the buffer circuit operating in parallel to make the output signal a feedback signal. Thus, there is an effect that the potential change can be detected.

That is, the external load capacitance detecting circuit of the present invention detects the potential change at the initial stage when the output signal OUT starts to change irrespective of the size of the external load, thereby increasing the degree of freedom of the control method. Increase. As a result, if the external load capacitance detection circuit is used for driving force control of the external load drive circuit,
The initial driving force can be reduced. Therefore, when the driving force of the external load driving circuit is insufficient, noise generation due to excessive driving force can be avoided by adding a driving element.

Further, there is an effect that the dullness of the feedback signal is reduced, and the generation of an unnecessary through current due to the input of the intermediate potential can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation at each point in FIG. 1 when an internal signal IN changes from “L” to “H”.

FIG. 3 is a diagram illustrating a relationship between an output signal OUT of an external load driving circuit and a delay time Tpd until the output signal b2 of a buffer circuit changes to an input threshold voltage VTH of a comparison circuit with respect to a change in an external load CL; .

FIG. 4 is a configuration diagram of another embodiment of the present invention.

FIG. 5 is a flowchart illustrating a method of generating a feedback signal in an external load capacitance detection circuit.

FIG. 6 is a diagram showing a configuration of a first conventional example.

FIG. 7 is a diagram showing a configuration of a second conventional example.

FIG. 8 is a diagram illustrating the operation of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 buffer circuit 2 coupling capacitance 3 delay circuit 4 comparison circuit 10 external load capacitance detection circuit 11 partial load drive circuit 12 input terminal 13 output terminal 20 feedback signal generation circuit

Claims (6)

[Claims] 1. An external load capacitance detecting circuit connected in parallel with an external load driving circuit, comprising: a feedback signal generating means for detecting a rising signal connected in parallel with the external load driving circuit; An external load capacitance detection circuit comprising comparison means for outputting a magnitude relationship between a feedback signal and an input signal delayed via a delay element. 2. The buffer circuit according to claim 1, wherein the feedback signal generating means is connected to a buffer circuit which receives the same internal signal as an external load driving circuit as an input signal, and is connected between an output of the external load driving circuit and an output of the buffer circuit. The external load capacitance detection circuit according to claim 1, further comprising a coupling capacitance, wherein the feedback signal is obtained through a connection point between the buffer circuit and the coupling capacitance. 3. A comparing device for outputting the magnitude relationship, a delay element for receiving the internal signal, adding a preset delay time and outputting a signal, and an output signal of the feedback signal generating device. 2. The external load capacitor according to claim 1, further comprising: a comparator that compares the output signal of the delay element with the output signal of the delay element and outputs a magnitude relationship between the output signal and the output change of the external load drive circuit. Detection circuit. 4. A plurality of delay elements for inputting the internal signal, adding a predetermined delay time and outputting a signal, wherein the comparison means for outputting the magnitude relationship outputs a signal, and an output signal of the feedback signal generation means. And a plurality of comparators for comparing the output signals corresponding to the plurality of delay elements and outputting a magnitude relationship between the output signals, and detecting an output change of the external load drive circuit in a plurality of stages. The external load capacitance detection circuit according to claim 1. 5. A method for generating a feedback signal in an external load capacitance detecting circuit connected in parallel with an external load driving circuit, comprising: a buffer circuit that receives, as an input signal, the same internal signal as the external load driving circuit; A feedback signal generation step comprising: a coupling capacitor connected between an output of a circuit and an output of the buffer circuit, wherein the feedback signal is obtained through a connection point between the buffer circuit and the coupling capacitor; And a comparator that outputs a signal with a predetermined delay time added thereto, and a comparator that compares the output signal of the feedback signal generation means with the output signal of the delay element and outputs a magnitude relationship therebetween. A comparison step of outputting the magnitude relationship for detecting an output change of the external load driving circuit at an initial stage. A feedback signal generation method in the external load capacitance detection circuit; and a flop. 6. A method for generating a feedback signal in an external load capacitance detecting circuit connected in parallel with an external load driving circuit, wherein the same internal signal as that of the external load driving circuit is supplied to the buffer circuit as an input signal. An output of the circuit is output through a coupling capacitor, an output of the buffer circuit is connected to an output of the coupling capacitor to generate a feedback signal, and the internal signal is output to a delay element having a predetermined delay time. And comparing the feedback signal with an output signal of the delay element, and transmitting a predetermined state indicating a delay as a result of the comparison, in the external load capacitance detection circuit.