CN1787645A - System for clock recovery of multi media system - Google Patents
System for clock recovery of multi media system Download PDFInfo
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- CN1787645A CN1787645A CN 200510115783 CN200510115783A CN1787645A CN 1787645 A CN1787645 A CN 1787645A CN 200510115783 CN200510115783 CN 200510115783 CN 200510115783 A CN200510115783 A CN 200510115783A CN 1787645 A CN1787645 A CN 1787645A
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Abstract
This invention provides a clock resuming system for realizing synchronous process to video/audio signals of the digital multimedia system, which is placed inside of a video/audio decode module of the system including an automatic frequency control device with a phase-lock ring module and a counting module and the counting module sets the frequency dividing parameters of a feedback frequency divider and an input divider according to the ratio of frequencies of output signals and input signals so as to realize synchronization of local clock and the system clock of a decode module.
Description
Technical field
The present invention relates to the video/audio process field, particularly the Synchronous Processing of video/audio.
Technical background
Clock recovery system is applied to many fields, is example with the digital multimedia system.As shown in Figure 1, this digital multimedia system comprises video/audio coding module E, and video/audio decoder module D1 carries out the storage or the transmission of data between this two module.In described coding module E, the sampling rate of video and audio coder is different, has each other and maybe may not have fixing relativeness.A unified system clock is arranged in described coding module E, produce the timestamp DTS that is representing the video/audio decoding, the timestamp PTS that is representing video/audio to reproduce according to this system clock, and at coded sample system-timing reference value SCR constantly.In order in video/audio decoder module D1, can exactly video/audio signal to be decoded and to reproduce, require the local clock STC of described decoder module and the system-timing reference value SCR of described coding module to keep synchronously, otherwise decoding and recovery time all will be followed the local clock generation entanglement of decoder module D1.As a rule keep the local clock STC of decoder module D1 and coding module E system-timing reference value SCR be to realize synchronously by a clock recovery system that is positioned at decoder module D1 inside.
Figure 2 shows that the structure T1 of traditional clock recovery system, when described decoder module D1 received the SCR value for the first time, this SCR numerical value was written into the initial value of a counter CO as local clock STC.Because may be different at different sampling instant system-timing reference value SCR, so the local clock STC of decoder module D1 also will adjust thereupon, causes the mistake of video/audio signal to be reproduced to prevent in the decoder module buffer generation overflow or underflow.Therefore, when a new system-timing reference value SCR arrives described decoder module D1, subtracter S by described clock recovery system T1 inside compares described system clock letter reference value SCR and local clock STC, and obtain an error amount, this error amount is controlled by a low pass filter filtering L and to a voltage controlled oscillator VCO, to improve or to reduce the output signal frequency of this VCO, the output of this VCO simultaneously is used to drive described counter CO, thereby the local clock STC of the quickening or the decoder module that slows down reaches unanimity itself and system-timing reference value SCR.
In the clock recovery system T1 of aforementioned conventional, need to adopt VCO that the local clock STC of decoder module is regulated, thereby local clock STC and system-timing reference value SCR are kept synchronously.Yet voltage controlled oscillator VCO is an external equipment to the SOC chip, and the SOC chip need send control signal it is controlled, and this just needs to increase the number of SOC chip pin, thereby causes the increase of cost.In addition, the market price of voltage controlled oscillator is generally also than higher, and therefore adopting the clock recovery system of traditional structure is disadvantageous for reducing system cost.
Summary of the invention
The objective of the invention is guaranteeing to reduce system cost under the normal prerequisite of chip sequential working.For achieving the above object, the present invention has put down in writing following technical scheme:
A kind of automatic frequency control apparatus comprises a phase-locked loop module, this phase-locked loop module is by an input frequency divider, a feedback divider and a phase-locked loop constitute, one input signal is connected to the input of described phase-locked loop by described input frequency divider, and the output signal of this phase-locked loop turns back to the input of this phase-locked loop by described feedback divider.This automatic frequency control apparatus also comprises a computing module, and described computing module is set the frequency division parameter of described feedback divider and described input frequency divider according to the ratio of needed output signal frequency and described frequency input signal.Described computing module is when setting the frequency division parameter of described input frequency divider and described feedback divider, value in the integer range that frequency division parameter allowed of these two frequency dividers makes described feedback divider frequency division parameter and the most approaching needed output signal frequency of ratio of described input frequency divider frequency division parameter and the ratio of described frequency input signal.
Technical solution of the present invention has also been put down in writing a kind of clock recovery system and has been comprised aforesaid automatic frequency control apparatus, this clock recovery system is with the clock signal of system that obtains from the outside input signal as described automatic frequency control apparatus, thereby realizes the control to the local clock signal frequency.Described computing module in the described automatic frequency control apparatus is when setting the frequency division parameter of described input frequency divider and described feedback divider, value in the integer range that frequency division parameter allowed of these two frequency dividers, the ratio that makes described feedback divider frequency division parameter and described input frequency divider frequency division parameter be the ratio of local clock signal frequency and the described system external timing signal frequency of approaching required output.
Put down in writing a kind of digital multimedia system in the technical solution of the present invention in addition and comprised central processing unit, video/audio coding module, video/audio decoder module, in described video/audio decoder module, has the clock recovery system that the front is put down in writing, this multimedia system has a total system clock, with the input signal of this system clock, thereby realize the synchronous of decoder module local clock and system clock as aforementioned automatic frequency control apparatus.Described computing module in the described automatic frequency control apparatus is when setting the frequency division parameter of described input frequency divider and described feedback divider, value in the integer range that frequency division parameter allowed of these two frequency dividers, the ratio that makes described feedback divider frequency division parameter and described input frequency divider frequency division parameter be the ratio of decoder module local clock signal frequency and the described clock signal of system frequency of approaching required output.
The present invention has further put down in writing a kind of auto frequency control method, be used for a kind of automatic frequency control apparatus, this device comprises one by importing a phase-locked loop module and the computing module that frequency divider, phase-locked loop and feedback divider are formed, and described method comprises: the step that an input signal is connected to the input of described phase-locked loop by described input frequency divider; The output signal of described phase-locked loop is turned back to the step of the input of described phase-locked loop by described feedback divider; This auto frequency control method also comprises: described computing module is set the step of the frequency division parameter of described feedback divider and described input frequency divider according to the ratio of needed output signal frequency and described frequency input signal.
Because the clock recovery system that the present invention write down, do not adopt voltage controlled oscillator VCO to realize control and adjusting to local clock as traditional clock recovery system, and just adopted a simple automatic frequency control system, thereby greatly reduce the cost of system; Simultaneously,, reduced the number of pins of SOC chip, reduced the cost of system equally because saved the such external equipment of VCO.
Description of drawings
Fig. 1 is the schematic diagram of digital multimedia system of the present invention;
Fig. 2 is the schematic diagram of traditional clock recovery system of the present invention;
Fig. 3 is the schematic diagram of automatic frequency control system of the present invention;
Fig. 4 is the schematic diagram of clock recovery system of the present invention;
Fig. 5 is a kind of digital multimedia system of using clock recovery system of the present invention.
Embodiment
The present invention has adopted a kind of novel clock recovery system for realizing aforesaid goal of the invention.This system no longer utilizes voltage controlled oscillator VCO to realize control to local clock, the employing that replaces a kind of simple automatic frequency control apparatus.
As shown in Figure 3, described automatic frequency control apparatus A comprises a phase-locked loop module P and a computing module C.Described phase-locked loop module comprises input frequency divider ref_div, feedback divider fb_div and a phase-locked loop pll.Input signal Clock_in is produced by the crystal oscillator (not shown) of a fixed frequency, and Clock_out represents the clock signal of required output.For described phase-locked loop module P, as shown in Equation (1), the output signal frequency of described phase-locked loop module P and the ratio of frequency input signal equal the ratio of feedback divider fb_div and the frequency division parameter of input frequency divider ref_div.Value in the integer range that described computing module C can allow at the frequency division parameter of described two frequency dividers, and the ratio that makes selected feedback divider fb_div and the frequency division parameter of input frequency divider ref_div according to the computational methods of the recurrence ratio of frequency and the frequency of input signal Clock_in of the signal Clock_out of approaching required output, thereby determine the frequency division parameter of described input and feedback divider, and obtain needed output signal at the output of automatic frequency control apparatus A.
As shown in Figure 4, adopted the clock recovery system T2 of described automatic frequency control apparatus A, when receiving new system-timing reference value SRC, system-timing reference value SRC and local clock signal STC are compared and obtain by low pass filter L the error frequency of system-timing reference value and local clock by subtracter S, described automatic frequency control apparatus A learns the local clock frequency of required output according to this error frequency, the input of computing module C among this automatic frequency control apparatus A phase-locked loop module P in calculating afterwards to described automatic frequency control apparatus A and the frequency division parameter of feedback divider are provided with, thereby obtain needed local clock signal frequency at the output of described clock recovery system T2.
As shown in Figure 5, the present invention has put down in writing a kind of digital multimedia system, and this digital multimedia system comprises a video/audio coding module E and a video/audio decoder module D2.In described video/audio decoder module D2, comprise aforesaid clock recovery system T2, described video/audio coding module E is transferred to described video/audio decoder module D2 with the system-timing reference value SCR of sampling instant, operation principle according to aforementioned clock recovery system T2, in described video/audio decoder module, obtain the local clock STC with the synchronous decoder module of SCR, thereby make video/audio signal be decoded accurately and reproduce.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement etc., all should be included within protection scope of the present invention.
Claims (7)
1. automatic frequency control apparatus, comprise a phase-locked loop module, this phase-locked loop module is by an input frequency divider, a feedback divider and a phase-locked loop constitute, one input signal is connected to the input of described phase-locked loop by described input frequency divider, and the output signal of this phase-locked loop turns back to the input of this phase-locked loop by described feedback divider; It is characterized in that,
This automatic frequency control apparatus also comprises a computing module, and described computing module is set the frequency division parameter of described feedback divider and described input frequency divider according to the ratio of needed output signal frequency and described frequency input signal.
2. automatic frequency control apparatus as claimed in claim 1, it is characterized in that described computing module is when setting the frequency division parameter of described input frequency divider and described feedback divider, value in the integer range that frequency division parameter allowed of these two frequency dividers makes described feedback divider frequency division parameter and the most approaching needed output signal frequency of ratio of described input frequency divider frequency division parameter and the ratio of described frequency input signal.
3. a clock recovery system that comprises automatic frequency control apparatus as claimed in claim 1 comprises the clock signal comparator of being made up of a subtracter and a low pass filter, and a local clock generator that is used to produce the local clock signal;
Described clock signal comparator compares and obtains a clock error frequency to the local clock signal with by the outside clock signal of system of importing of system; It is characterized in that,
Described local clock signal is as the input signal of described automatic frequency controller, this automatic frequency controller obtains the clock signal frequency of required output according to described clocking error frequency, and this automatic frequency controller is regulated the local clock signal itself and described system external clock are kept synchronously.
4. clock recovery system as claimed in claim 3, it is characterized in that described computing module is when setting the frequency division parameter of described input frequency divider and described feedback divider, value in the integer range that frequency division parameter allowed of these two frequency dividers, the ratio that makes described feedback divider frequency division parameter and described input frequency divider frequency division parameter be the ratio of local clock signal frequency and the described system external timing signal frequency of approaching required output.
5. a digital multimedia system that comprises clock recovery system as claimed in claim 3 comprises a CPU processor, and one is used to produce the systematic clock generator of system clock, and a video/audio coding module and a video/audio decoder module is characterized in that,
The described clock recovery system that is included in the described video/audio decoder module receives the clock signal of system that comes from described video/audio coded system, and the local clock signal of described clock signal of system and decoder module compared, obtain a clock error frequency;
The local clock of described decoder module is as the input signal of automatic frequency controller described in the described clock recovery system, this automatic frequency controller obtains the decoder module local clock signal frequency of required output according to described clocking error frequency, and this automatic frequency controller is regulated decoder module local clock signal itself and described system clock are kept synchronously.
6. digital multimedia system as claimed in claim 5, it is characterized in that described computing module is when setting the frequency division parameter of described input frequency divider and described feedback divider, value in the integer range that frequency division parameter allowed of these two frequency dividers, the ratio that makes described feedback divider frequency division parameter and described input frequency divider frequency division parameter be the ratio of decoder module local clock signal frequency and the described clock signal of system frequency of approaching required output.
7. an auto frequency control method is used for a kind of automatic frequency control apparatus, and this device comprises one by importing a phase-locked loop module and the computing module that frequency divider, phase-locked loop and feedback divider are formed, and described method comprises:
One input signal is connected to the step of the input of described phase-locked loop by described input frequency divider;
The output signal of described phase-locked loop is turned back to the step of the input of described phase-locked loop by described feedback divider;
It is characterized in that this auto frequency control method also comprises:
Described computing module is set the step of the frequency division parameter of described feedback divider and described input frequency divider according to the ratio of needed output signal frequency and described frequency input signal.
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| CNB2005101157839A CN100444641C (en) | 2005-11-11 | 2005-11-11 | System for clock recovery of multi media system |
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| CNB2005101157839A CN100444641C (en) | 2005-11-11 | 2005-11-11 | System for clock recovery of multi media system |
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| CN1787645A true CN1787645A (en) | 2006-06-14 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011023030A1 (en) * | 2009-08-28 | 2011-03-03 | 炬力集成电路设计有限公司 | Integrated circuit and method for acquiring reference clock in integrated circuit |
| CN101420510B (en) * | 2007-10-26 | 2014-06-11 | 瑞昱半导体股份有限公司 | Time clock generating device applicable to multimedia interface and related method thereof |
| CN106788421A (en) * | 2016-12-30 | 2017-05-31 | 陕西烽火电子股份有限公司 | A kind of frequency synthesizer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100209880B1 (en) * | 1995-10-30 | 1999-07-15 | 윤종용 | System clock recovery apparatus in mpeg-2 image data decoder |
| WO2002032148A1 (en) * | 2000-10-11 | 2002-04-18 | Sony Electronics Inc. | Adaptive clocking mechanism for digital video decoder |
| CN100353673C (en) * | 2002-08-14 | 2007-12-05 | 联发科技股份有限公司 | Lock phare cycle frequency synthesizer |
| US8189730B2 (en) * | 2002-09-30 | 2012-05-29 | Ati Technologies Ulc | Method and apparatus for system time clock recovery |
| GB2413043B (en) * | 2004-04-06 | 2006-11-15 | Wolfson Ltd | Clock synchroniser and clock and data recovery apparatus and method |
| TWI241776B (en) * | 2004-10-11 | 2005-10-11 | Realtek Semiconductor Corp | Clock generator and data recovery circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101420510B (en) * | 2007-10-26 | 2014-06-11 | 瑞昱半导体股份有限公司 | Time clock generating device applicable to multimedia interface and related method thereof |
| WO2011023030A1 (en) * | 2009-08-28 | 2011-03-03 | 炬力集成电路设计有限公司 | Integrated circuit and method for acquiring reference clock in integrated circuit |
| CN106788421A (en) * | 2016-12-30 | 2017-05-31 | 陕西烽火电子股份有限公司 | A kind of frequency synthesizer |
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