CN102201810A - Device and method for controlling clock recovery - Google Patents
Device and method for controlling clock recovery Download PDFInfo
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- CN102201810A CN102201810A CN2010101506192A CN201010150619A CN102201810A CN 102201810 A CN102201810 A CN 102201810A CN 2010101506192 A CN2010101506192 A CN 2010101506192A CN 201010150619 A CN201010150619 A CN 201010150619A CN 102201810 A CN102201810 A CN 102201810A
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Abstract
The invention discloses a device and method for controlling clock recovery. A clock recovery device comprises a phase-locked loop and a regulating circuit, wherein the phase-locked loop comprises a first frequency divider, a second frequency-divider and a clock recovery unit; the first frequency divider is used for dividing a first frequency of an input clock by using a first divisor to generate a reference signal; the second frequency divider is used for dividing a second frequency of an output clock by using a second divisor to generate a feedback signal; the clock recovery unit is coupled to the first and second frequency dividers and is used for rebuilding and providing an output clock according to the reference signal and the feedback signal; and the regulating circuit is coupled with the phase-locked circuit and is used for regulating at least one of the first divisor and the second divisor according to the buffer state information of a data buffer.
Description
Technical field
The invention relates to the method for a kind of clock recovery device and relevant control clock recovery thereof, especially refer to a kind of divisor (divisor) of in processing system for video, adjusting a phase-locked loop (PLL), with the apparatus and method of control clock recovery according to the buffer status information of a data buffer (data buffer).
Background technology
Please refer to Fig. 1, Fig. 1 is the schematic diagram of a traditional phase-locked loop 100 in the prior art.Tradition phase-locked loop 100 includes one first frequency divider 110, a clock recovery unit 120 and one second frequency divider 130, and phase-locked loop 100 is used for rebuilding and provide an output clock CKout according to an input clock CKin.First frequency divider 110 utilizes one first divisor N to come the first frequency f1 of input clock CKin is carried out frequency division, to produce reference signal S
REF, second frequency divider 130 then utilizes the second divisor M to come the second frequency f2 of output clock CKout is carried out frequency division, to produce feedback signal S
FBAt last, 120 of clock recovery units are coupled to first frequency divider 110, second frequency divider 120, are used for according to reference signal S
REFAnd feedback signal S
FBRebuild and provide output clock CKout.
Usually, phase-locked loop 100 can be used on and carries out the clock recovery action in the design of serializer/de-serializers (serializer/deserializer), yet for serializer/de-serializers, the data width of its needed M, N is greater much far beyond other application.For instance, the required data width of high picture quantity multimedia interface standard (HDMI) is 20, the required data width of DisplayPort interface standard then is 24, thus, can make the clock stable time of phase-locked loop 100 become very long, also can cause the size of phase-locked loop 100 to be greater many than other data width smaller applications design.
Therefore, how the less clock recovery device of size being provided and can shortening its clock stabilization time, also is one of important consideration in the design field, particularly is applied in the middle of the design of serializer/de-serializers.
Summary of the invention
Therefore, one of purpose of the present invention is to propose the method for a kind of clock recovery device, processing system for video and relevant control clock recovery thereof, to address the above problem.
In one embodiment of this invention, a kind of clock recovery device is disclosed.Clock recovery device comprises a phase-locked loop and and adjusts circuit.The phase-locked loop rebuilds and provides the output clock according to input clock, the phase-locked loop includes first frequency divider, second frequency divider and clock recovery unit.First frequency divider utilizes first divisor to come the first frequency of input clock is carried out frequency division, to produce reference signal.Second frequency divider utilizes second divisor to come the second frequency of output clock is carried out frequency division, to produce feedback signal.Clock recovery unit is coupled to first frequency divider and second frequency divider, is used for rebuilding and provide the output clock according to reference signal and feedback signal.Adjust circuit and be coupled to the phase-locked loop, be used for adjusting one at least in first divisor and second divisor according to the buffer status information of a data buffer.
In another embodiment of the present invention, other discloses a kind of processing system for video.Processing system for video includes a data buffer, a clock recovery device and a video processor.Data buffer receives an inputting video data to export output video data, and provide a buffer status information, wherein inputting video data writes among the data buffer according to input clock, and the data based output clock of output video reads from data buffer.Clock recovery device includes a phase-locked loop and and adjusts circuit.The phase-locked loop rebuilds and provides the output clock according to input clock, the phase-locked loop includes one first frequency divider, one second frequency divider and a clock recovery unit.First frequency divider utilizes first divisor to come the first frequency of input clock is carried out frequency division, to produce reference signal.Second frequency divider utilizes second divisor to come the second frequency of output clock is carried out frequency division, to produce feedback signal.Clock recovery unit is coupled to first frequency divider and second frequency divider, is used for rebuilding and provide the output clock according to reference signal and feedback signal.Adjust circuit and be coupled to the phase-locked loop, be used for adjusting one at least in first divisor and second divisor according to the buffer status information of a data buffer.Video processor is coupled to data buffer and clock recovery device, is used for handling the output video data, and wherein video processor operates under the output clock.
In another embodiment of the present invention, a kind of method of controlling clock recovery is disclosed again.The method includes the steps of: receive an input clock, and utilize first divisor to come the first frequency of input clock is carried out frequency division, to produce reference signal; Utilize second divisor to come the second frequency of output clock is carried out frequency division, to produce feedback signal; Adjust one at least in first divisor and second divisor according to the buffer status information of a data buffer; And rebuild and provide the output clock according to reference signal and feedback signal.
Description of drawings
Fig. 1 is the schematic diagram of a traditional phase-locked loop in the prior art.
Fig. 2 is the calcspar of an embodiment of the present invention's one clock recovery device.
Fig. 3 is the calcspar of an embodiment of the present invention's one processing system for video.
Fig. 4 is a key diagram 1 and the comparison diagram of the resultant curve of output clock shown in Figure 2.
Fig. 5 controls the flow chart of an example operation of the method for clock recovery for the present invention.
[main element symbol description]
100,250 phase-locked loops
300 processing system for video
200,400 clock recovery devices
110,210 first frequency dividers
120,220 clock recovery units
130,230 second frequency dividers
260 adjust circuit
310 data buffers
320 first in first out tandems
330 data buffer control units
340 video processors
M second divisor
N first divisor
Pw writes pointer
The Pr reading pointer
The Ckin input clock
Ckout exports clock
F1, f
Lane_clockFirst frequency
F2, f
Stream_clockSecond frequency
S
REFReference signal
S
FBFeedback signal
The BI buffer status information
EMPTY is close to blank signal
FULL is close to full signal
The Din inputting video data
Dout output video data
S1, S2 curve
T1, t2 clock stable time
502～532 steps
Embodiment
Please refer to Fig. 2, Fig. 2 is the calcspar of an embodiment of the present invention's one clock recovery device 200.In Fig. 2, clock recovery device 200 comprises phase-locked loop 250 and adjusts circuit 260, wherein phase-locked loop 250 includes first frequency divider 210, second frequency divider 230 and clock recovery unit 220, and phase-locked loop 250 rebuilds and provide an output clock CKout according to an input clock CKin.In the present embodiment, clock recovery device 200 is applied among the serializer/de-serializers (serializer/deserializer) of a processing system for video, therefore input clock CKin is as a data wire clock (lane clock), and output clock Ckout is then as a data flow clock (stream clock).But this is not a restrictive condition of the present invention, and those skilled in the art should understand, and clock recovery device 200 also can be applicable in other design, and this also should be under the jurisdiction of the scope that the present invention is contained.
As shown in Figure 2, first frequency divider 210 utilizes the first divisor N to come a first frequency f to input clock CKin
Lane_clockCarry out frequency division, to produce reference signal S
REFAnd second frequency divider 230 utilizes the second divisor M to come exporting the second frequency f of clock CKout
Stream_clockCarry out frequency division, to produce feedback signal S
FBThen, clock recovery unit 220 is coupled to first frequency divider 210 and second frequency divider 230, is used for according to reference signal S
REFAnd feedback signal S
FBRebuild and provide output clock CKout.In addition, adjust circuit 260 and be coupled to phase-locked loop 250, in the present embodiment, adjust circuit 260 and be coupled to first frequency divider 210 and second frequency divider 230.It should be noted that adjusting circuit 260 can adjust first divisor N of phase-locked loop 250 and the one at least among the second divisor M according to a buffer status information BI of a data buffer (please in the lump with reference to figure 3).
Can learn the first frequency f of above-mentioned input clock CKin by Fig. 2
Lane_clock, output clock CKout second frequency f
Sream_clock, the first divisor N and the second divisor M can meet following formula:
f
stream_clock/f
lane_clock＝M/N (1)。
In general, the first frequency f of input clock CKin
Lane_clockBe a definite value, and the second frequency f of output clock CKout
Stream_clockThen be one with the relevant change value of its resolution, and can (Consumer Electronics Association, CEA) defined standard obtains by Consumer Electronics Association.With the resolution 720P in the DisplayPort standard is example, the first frequency f of its input clock Ckin
Lane_clockEqual 162MHz, and the second frequency f of its output clock Ckout
Stream_clockThen equal 74MHz.Therefore, can learn the second frequency f of output clock Ckout by above-mentioned formula (1)
Stream_clockCan decide via the first divisor N and the second divisor M.
It should be noted that and dynamically to adjust the first divisor N and the second divisor M by adjusting circuit 260, and these two divisors can be adjusted simultaneously or can be adjusted at different time.That is to say, in one embodiment, adjust circuit 260 and can be used to adjust the first divisor N, further to adjust second frequency f
Stream_clockIn another embodiment, adjust circuit 260 and can be used to adjust the second divisor M, further to adjust second frequency f
Stream_clockAnd in another embodiment, adjust 260 in circuit can be used to adjust ratio between the second divisor M and the first divisor N (also promptly, M/N), further to adjust second frequency f
Stream_clockThose skilled in the art should understand, and under the situation of spirit of the present invention, all are feasible about the variation of all kinds of adjusting circuit 260, and this all should be under the jurisdiction of the scope that the present invention is contained.
Please refer to Fig. 3, Fig. 3 is the calcspar of an embodiment of the present invention's one processing system for video 300.As shown in Figure 3, processing system for video 300 includes a data buffer 310, a clock recovery device 400 and a video processor 340.Because the framework of the framework of clock recovery device 400 and clock recovery device 200 shown in Figure 2 is identical, for identical for purpose of brevity part just repeats no more.And data buffer 310 receives an inputting video data Din to export an output video data Dout to video processor 340; In addition, data buffer 310 can provide a buffer status information BI (include at least be close to blank signal EMPTY and be close to full signal FULL) to give the adjustment circuit 260 of clock recovery device 400.In the present embodiment, output clock CKout reads clock as one of data buffer 310, and input clock Ckin then writes clock as one of data buffer 310; That is to say that inputting video data Din writes to according to input clock CKin among the data buffer 310, output video data Dout then comes to read from data buffer 310 according to output clock CKout.Generally speaking, the inputting video data Din speed that writes data buffer 310 can't surpass the first frequency f of input clock Ckin
Lane_clock, this is because the virtual data (dummy data) that inputting video data Din filled up can be dropped and can not write among the data buffer 310.Afterwards, video processor 340 is coupled to data buffer 310 and clock recovery device 400, to be used for handling output video data Dout.Please note that video processor 340 operates under the output clock CKout.
Note that above-mentioned buffer status information BI is used to refer to the second frequency f of output clock CKout
Stream_clockWhether slower or very fast than a normal frequency of a normal output clock, for example inputting video data Din writes to the frequency (for example, be example with the resolution 720P in the DisplayPort standard, it equals 74MHz) among the data buffer 310.In the present embodiment, data buffer 310 includes a first in first out tandem (FIFO) 320, and writes pointer (write pointer) Pw, a reading pointer Pr and a data buffer control unit 330, and wherein first in first out tandem 320 is used for noting down inputting video data Din to export these output video data Dout.Moreover what write that pointer Pw indication inputting video data Din noted down in first in first out tandem 320 one writes the address; What reading pointer was used to refer to then that output video data Dout exported in first in first out tandem 320 one reads the address.In addition, 330 of data buffer control units are coupled to first in first out tandem 320, are used for setting buffer status information BI (include at least be close to blank signal EMPTY and be close to full signal FULL) according to writing pointer Pw and reading pointer Pr.
For instance, when reading pointer Pr when writing pointer Pw, data buffer control unit 330 meeting triggerings this moment are close to blank signal EMPTY and are used as buffer status information BI, in this case, adjust the one at least among the circuit 260 meeting adjustment first divisor N and the second divisor M, reduce between the second divisor M and the first divisor N a ratio (also promptly, M/N); And when writing pointer Pw near reading pointer Pr, data buffer control unit 330 meeting triggerings this moment are close to full signal FULL and are used as buffer status information BI, in this case, adjust the one at least among the circuit 260 meeting adjustment first divisor N and the second divisor M, increase the ratio M/N between the second divisor M and the first divisor N.Except above-mentioned two kinds of mentioned situations, adjustment circuit 260 may trigger a normal signal NORMAL (figure does not show) or can not trigger any signal and be used as buffer status information BI, so that the first divisor N and the second divisor M remain unchanged.
Please refer to Fig. 4, Fig. 4 is a key diagram 1 and the comparison diagram of the resultant curve of output clock CKout shown in Figure 2.Wherein first curve S 1 is represented the output clock CKout of traditional phase-locked loop 100 shown in Figure 1, and second curve S 2 is then represented the output clock CKout of clock recovery device 200 shown in Figure 2.Can learn that by Fig. 4 the clock stable time t2 of second curve S 2 disclosed in this invention comes manyly soon than the clock stable time t1 of first curve S 1.
In brief, by above-mentioned buffer status information BI (include at least and be close to blank signal EMPTY and be close to full signal FULL), the user can learn easily whether the frequency of present output clock CKout is slower or very fast than the frequency of a normal output clock.And by utilizing buffer status information BI to adjust the first divisor N and/or the second divisor M, can design the M of a less data width of needs, the phase-locked loop of N numerical value, the phase-locked loop that replaces the M that originally needs the larger data width, N numerical value (for example, phase-locked loop 100 among Fig. 1), thus, just can design the less clock recovery device of size and can shorten its clock stabilization time, and and then save whole manufacturing cost.
Please refer to Fig. 5, Fig. 5 controls the flow chart of an example operation of the method for clock recovery for the present invention, and it comprises following step (if note that and can obtain roughly the same result, then the following step and non-limiting will the execution according to order shown in Figure 5):
Step 502: beginning.
Step 504: receive input clock, and utilize first divisor to come the first frequency of input clock is carried out frequency division, to produce reference signal.
Step 506: utilize second divisor to come the second frequency of output clock is carried out frequency division, to produce feedback signal.
Step 508: rebuild and provide the output clock according to reference signal and feedback signal.
Step 510: whether the second frequency of judging the output clock is slower or very fast than the normal frequency of normal output clock.When the normal frequency of second frequency is slow, execution in step 520; Otherwise, execution in step 530.
Step 520: when the normal frequency of second frequency is slow, triggers and be close to full signal with as buffer status information.
Step 522: adjust the one at least in first divisor and second divisor, increase the ratio between second divisor and first divisor.
Step 530: when the normal frequency of second frequency is fast, triggers and be close to blank signal with as buffer status information.
Step 532: adjust the one at least in first divisor and second divisor, reduce the ratio between second divisor and first divisor.
About each step shown in Figure 5 please arrange in pairs or groups Fig. 2 or each element shown in Figure 3, can understand between each element and how to operate, for not repeating them here for purpose of brevity.Please note, step 504 can be performed by first frequency divider 210, step 506 can be performed by second frequency divider 230, step 510 can be indicated by buffer status information BI, step 520,530 can be performed by data buffer control unit 330, step 522,532 can be performed by adjusting circuit 260, and step 508 then can be performed by clock recovery unit 220.
Please note, the step of above-mentioned flow chart only is the feasible embodiment of the present invention, it is not restrictive condition of the present invention, those skilled in the art should understand, under spirit of the present invention, the step of the flow process of Fig. 5 can increase other intermediate steps again or several steps can be merged into one step.
Above-described embodiment only is used for technical characterictic of the present invention is described, is not to be used for limiting to category of the present invention.As from the foregoing, the invention provides a kind of clock recovery device, processing system for video and relevant method thereof.By utilizing buffer status information BI, can be used to dynamically adjust the first divisor N and/or the second divisor M.Thus, just can design the M of a less data width of needs, the phase-locked loop of N numerical value, reaching the size of dwindling clock recovery device and to shorten its clock purpose of stabilization time, and can and then save whole manufacturing cost.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (18)
1. a clock recovery device (clock recovery device) includes:
One phase-locked loop (PLL), be used for according to an input clock rebuild and provide one output clock, this phase-locked loop includes:
One first frequency divider is used for utilizing one first divisor to come a first frequency of this input clock is carried out frequency division, to produce a reference signal;
One second frequency divider is used for utilizing one second divisor to come a second frequency of this output clock is carried out frequency division, to produce a feedback signal; And
One clock recovery unit is coupled to this first frequency divider and this second frequency divider, is used for rebuilding and provide this output clock according to this reference signal and this feedback signal; And
One adjusts circuit, is coupled to this phase-locked loop, is used for adjusting one at least in this first divisor and this second divisor according to a buffer status information of a data buffer.
2. clock recovery device as claimed in claim 1, wherein this second frequency of this first frequency of this input clock, this output clock, this first divisor and this second divisor meet following formula:
f
stream_clock/f
lane_clock＝M/N；
Wherein, f
Stream_clockRepresent this second frequency of this output clock, f
Lane_clockRepresent this first frequency of this input clock, M represents this second divisor, and N represents this first divisor.
3. clock recovery device as claimed in claim 1, wherein this input clock and this output clock are used for driving this data buffer.
4. clock recovery device as claimed in claim 3, whether wherein this buffer status information is used to refer to this second frequency of this output clock slower or very fast than a normal frequency of a normal output clock.
5. clock recovery device as claimed in claim 3, wherein this output clock reads clock as one of this data buffer; And this input clock writes clock as one of this data buffer.
6. clock recovery device as claimed in claim 1, wherein this clock recovery device is applied among the serializer/de-serializers (serializer/deserializer) of a processing system for video; This input clock is a data wire clock (lane clock); And this output clock is a data flow clock (streamclock).
7. processing system for video includes:
One data buffer, be used for receiving an inputting video data to export output video data, and be used to provide a buffer status information, wherein this inputting video data writes among this data buffer according to an input clock, and the data based output clock of this output video reads from this data buffer;
One clock recovery device includes:
One phase-locked loop is used for rebuilding and this output clock being provided according to this input clock, and this phase-locked loop includes:
One first frequency divider is used for utilizing one first divisor to come a first frequency of this input clock is carried out frequency division, to produce a reference signal;
One second frequency divider is used for utilizing one second divisor to come a second frequency of this output clock is carried out frequency division, to produce a feedback signal; And
One clock recovery unit is coupled to this first frequency divider and this second frequency divider, is used for rebuilding and provide this output clock according to this reference signal and this feedback signal; And
One adjusts circuit, is coupled to this phase-locked loop, is used for adjusting one at least in this first divisor and this second divisor according to this buffer status information; And
One video processor is coupled to this data buffer and this clock recovery device, is used for handling this output video data, and wherein this video processor operates under this output clock.
8. processing system for video as claimed in claim 7, wherein this second frequency of this first frequency of this input clock, this output clock, this first divisor and this second divisor meet following formula:
f
stream_clock/f
lane_clock＝M/N；
Wherein, f
Stream_clockRepresent this second frequency of this output clock, f
Lane_clockRepresent this first frequency of this input clock, M represents this second divisor, and N represents this first divisor.
9. processing system for video as claimed in claim 7, whether wherein this buffer status information is used to refer to this second frequency of this output clock slower or very fast than a normal frequency of a normal output clock.
10. processing system for video as claimed in claim 7, wherein this output clock reads clock as one of this data buffer; And this input clock writes clock as one of this data buffer.
11. processing system for video as claimed in claim 7, wherein this data buffer includes:
One first in first out tandem (FIFO) is used for noting down this inputting video data to export this output video data;
One writes pointer (write pointer), and what be used to refer to that this inputting video data noted down in this first in first out tandem one writes the address;
One reading pointer, what be used to refer to that these output video data are exported in this first in first out tandem one reads the address; And
One data buffer control unit is coupled to this first in first out tandem, is used for writing pointer and this reading pointer is set this buffer status information according to this.
12. processing system for video as claimed in claim 11, wherein when this reading pointer writes pointer near this, this data buffer control unit can trigger one and be close to blank signal (almost emptysignal) with as this buffer status information, and adjust one at least in this first divisor and this second divisor, reduce the ratio between this second divisor and this first divisor; And when this writes pointer near this reading pointer, this data buffer control unit can trigger one and be close to full signal (almost full signal) with as this buffer status information, and adjust one at least in this first divisor and this second divisor, increase this ratio between this second divisor and this first divisor.
13. a method of controlling clock recovery includes following steps;
Receive an input clock, and utilize one first divisor to come a first frequency of this input clock is carried out frequency division, to produce a reference signal;
Utilize one second divisor to come a second frequency of this output clock is carried out frequency division, to produce a feedback signal;
Adjust one at least in this first divisor and this second divisor according to a buffer status information of a data buffer; And
Rebuild and provide this output clock according to this reference signal and this feedback signal.
14. method as claimed in claim 13, wherein this second frequency of this first frequency of this input clock, this output clock, this first divisor and this second divisor meet following formula:
f
stream_clock/f
lane_clock＝M/N；
Wherein, f
Stream_clockRepresent this second frequency of this output clock, f
Lane_clockRepresent this first frequency of this input clock, M represents this second divisor, and N represents this first divisor.
15. method as claimed in claim 13, whether wherein this buffer status information is used to refer to this second frequency of this output clock slower or very fast than a normal frequency of a normal output clock.
16. method as claimed in claim 13, it comprises in addition:
Receive an inputting video data to export output video data, wherein this inputting video data writes among this data buffer according to this input clock, and data based this output clock of this output video reads from this data buffer.
17. method as claimed in claim 13, wherein this data buffer includes a first in first out tandem and writes pointer and one write the address with what be used to refer to that this inputting video data noted down in this first in first out tandem to export these output video data, one to be used for noting down this inputting video data, and a reading pointer one reads the address with what be used to refer to that these output video data are exported in this first in first out tandem; And this method comprises in addition:
Write pointer and this reading pointer is set this buffer status information according to this.
18. method as claimed in claim 17 wherein writes pointer and this reading pointer according to this and sets the step of this buffer status information and include:
When this reading pointer writes pointer near this, trigger one and be close to blank signal with as this buffer status information, and adjust the one at least in this first divisor and this second divisor, reduce the ratio between this second divisor and this first divisor; And
When this writes pointer near this reading pointer, trigger one and be close to full signal with as this buffer status information, and adjust the one at least in this first divisor and this second divisor, increase this ratio between this second divisor and this first divisor.
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|---|---|---|---|
| CN2010101506192A CN102201810A (en) | 2010-03-23 | 2010-03-23 | Device and method for controlling clock recovery |
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|---|---|---|---|
| CN2010101506192A CN102201810A (en) | 2010-03-23 | 2010-03-23 | Device and method for controlling clock recovery |
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| CN104854569A (en) * | 2012-11-06 | 2015-08-19 | 加利福尼亚大学董事会 | Self track scheme for multi frequency band serializer de-serializer i/o circuits |
| CN105634485A (en) * | 2015-12-22 | 2016-06-01 | 华为技术有限公司 | Spread spectrum clock generation device and spread spectrum clock signal generation method |
| CN107272822A (en) * | 2017-06-16 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of system clock monitoring method and device |
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| CN107272822A (en) * | 2017-06-16 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of system clock monitoring method and device |
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Application publication date: 20110928 |