CN107272822A - A kind of system clock monitoring method and device - Google Patents
A kind of system clock monitoring method and device Download PDFInfo
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- CN107272822A CN107272822A CN201710455971.9A CN201710455971A CN107272822A CN 107272822 A CN107272822 A CN 107272822A CN 201710455971 A CN201710455971 A CN 201710455971A CN 107272822 A CN107272822 A CN 107272822A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Abstract
The invention provides a kind of system clock monitoring method and device, this method includes：According to the target clock cycle set in advance, the clock cycle for treating monitoring clock carries out frequency modulation processing, obtained for the first clock cycle；According to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, the second clock cycle is obtained；In each first clock cycle, at least one verification data is stored into the memory space with preset capacity；In each second clock cycle, at least one verification data more first stored is read from memory space, and at least one verification data read is deleted from memory space；According at least two verification datas read in continuous two second clock cycles, judge whether clock to be monitored is abnormal.The invention provides a kind of system clock monitoring method and device, it can realize and system clock is monitored.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of system clock monitoring method and device.
Background technology
System clock is very important part in server system, in the server to be used for being CPU, integrated south more
Bridge (Platform Controller Hub, PCH), high speed serialization computer expansion bus standard (Peripheral
Component Interconnect Express, PCI-E) groove and baseboard management controller (Baseboard Management
Controller, BMC) equipment offer clock.
System clock needs to meet certain frequency requirement, when system clock frequency exceeds allowed band, server meeting
Occurs timing uncertainty or even machine of delaying because system clock is abnormal.Therefore, it is necessary to be monitored to system clock, to ensure service
Device can normally be run.
At present, general server can not be realized and system clock is monitored, and be merely able to the side by manual time-keeping
Formula verifies whether system clock is abnormal.
The content of the invention
The embodiments of the invention provide a kind of system clock monitoring method and device, it can realize and system clock is supervised
Control.
In a first aspect, the embodiments of the invention provide a kind of system clock monitoring method, including：
According to the target clock cycle set in advance, the clock cycle for treating monitoring clock carries out frequency modulation processing, obtains the
One clock cycle；
According to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, second clock week is obtained
Phase；
In each described first clock cycle, at least one check number is stored into the memory space with preset capacity
According to, wherein, in the off-capacity of the memory space, the data longer to storage time are covered；
In each described second clock cycle, read from the memory space compared with least one the described school first stored
Test data, and at least one described verification data described in reading is deleted from the memory space, wherein, deposited when described
Space is stored up when in the absence of the verification data, specific data is read and is used as the verification data；
The verification data according at least two read the continuous two second clock cycles, judge described in treat
Whether monitoring clock is abnormal.
Preferably, the basis read the continuous two second clock cycles at least two described in verification data
Judge whether the clock to be monitored is abnormal, including：
It is determined that being verified in continuous two the first clock cycle storages to described at least two in the memory space
Incidence relation between data；
Whether verification data described in judging read the continuous two second clock cycles at least two meets institute
State incidence relation；
If it is, determining that the clock to be monitored is normal, otherwise determine that the clock to be monitored is abnormal.
Preferably, the basis read the continuous two second clock cycles at least two described in verification data
Judge whether the clock to be monitored is abnormal, including：
It is determined that being verified in continuous two the first clock cycle storages to described at least two in the memory space
Incidence relation between data；
Whether verification data described in judging read the continuous two second clock cycles at least two meets institute
Incidence relation is stated, if not, verification data exception of record；
Judge between this verification data exception recorded and the last verification data exception recorded
Time interval whether be less than default duration threshold value, if it is, determine that the clock to be monitored is abnormal, otherwise determine described in treat
Monitoring clock is normal.
Preferably, after the record once the verification data exception, further comprise：
Pause perform described in read in each described second clock cycle from the memory space more first store to
A few verification data, and after pause duration reaches buffering duration set in advance, restart execution described every
One second clock cycle is read from the memory space compared with least one the described verification data first stored；
Wherein, the buffering duration is more than or equal to a second clock cycle.
Preferably, described according to the target clock cycle set in advance, the clock cycle for treating monitoring clock carries out frequency modulation
Processing, obtained for the first clock cycle, including：
According to target clock cycle set in advance and the ratio of the standard clock cycle of clock to be monitored, the first tune is determined
Frequency parameter, is zoomed in and out using first chirp parameter to the actual clock cycle of the clock to be monitored, when obtaining first
The clock cycle；
It is described according to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, when obtaining second
The clock cycle, including：
According to target period set in advance and the ratio of the clock cycle of reference clock, the second chirp parameter is determined, profit
The clock cycle of the reference clock is zoomed in and out with second chirp parameter, the second clock cycle is obtained.
Preferably, described in each described first clock cycle, stored into the memory space with preset capacity
Before at least one verification data, further comprise：
At least one buffered data for meeting the incidence relation is stored in the memory space successively.
Second aspect, the embodiments of the invention provide a kind of system clock supervising device, including：Frequency modulation processing unit, deposit
Storage unit, reading unit and judging unit；
The frequency modulation processing unit, for according to the target clock cycle set in advance, treating the clock week of monitoring clock
Phase carries out frequency modulation processing, obtained for the first clock cycle, is additionally operable to according to the target clock cycle, to the clock week of reference clock
Phase carries out frequency modulation processing, obtains the second clock cycle；
The memory cell, for each described first clock cycle obtained in the frequency modulation processing unit, to tool
At least one verification data is stored in the memory space for having preset capacity, wherein, in the off-capacity of the memory space pair
The longer data of storage time are covered；
The reading unit, for each the described second clock cycle obtained in the frequency modulation processing unit, from institute
State read in memory space the memory cell compared with least one the described verification data first stored, and described in reading
At least one described verification data is deleted from the memory space, wherein, when the memory space is in the absence of the verification
During data, read specific data and be used as the verification data；
The judging unit, for according to the reading unit read the continuous two second clock cycles to
Few two verification datas, judge whether the clock to be monitored is abnormal.
Preferably, the judging unit includes：First determination subelement and the first judgment sub-unit；
First determination subelement, it is empty to the storage in continuous two the first clock cycle storages for determining
Between at least two described in incidence relation between verification data；
First judgment sub-unit, for judge to read the continuous two second clock cycles at least two
Whether the verification data meets the incidence relation that first determination subelement is determined, if it is, waiting to supervise described in determining
Control clock normal, otherwise determine that the clock to be monitored is abnormal.
Preferably, the judging unit includes：Second determination subelement and the second judgment sub-unit；
Second determination subelement, it is determined that in continuous two the first clock cycle storages into the memory space
At least two described in incidence relation between verification data；
Second judgment sub-unit, for judge to read the continuous two second clock cycles at least two
Whether the verification data meets the incidence relation that second determination subelement is determined, if not, record is once verified
Data exception, is additionally operable to judge that the verification data that this is recorded is abnormal different with the last verification data recorded
Whether the time interval between often is less than default duration threshold value, if it is, determining that the clock to be monitored is abnormal, otherwise determines
The clock to be monitored is normal.
Preferably, second judgment sub-unit, is further used for recording once the verification data generation exception
Afterwards, the reading unit is triggered；
The reading unit, is further used for when receiving the triggering of second judgment sub-unit, and pause performs institute
At least one the described verification data read in each second clock cycle from the memory space compared with first storing is stated,
And after pause duration reaches buffering duration set in advance, restart execution described in each described second clock cycle
Read from the memory space compared with least one the described verification data first stored, wherein, the buffering duration is more than or waited
In a second clock cycle.
Preferably, the frequency modulation processing unit, for according to target clock cycle set in advance and clock to be monitored
The ratio of standard clock cycle, determines the first chirp parameter, utilizes reality of first chirp parameter to the clock to be monitored
The border clock cycle zooms in and out, and obtains for the first clock cycle, is additionally operable to according to target period set in advance and reference clock
The ratio of clock cycle, determines the second chirp parameter, utilizes clock cycle of second chirp parameter to the reference clock
Zoom in and out, obtain the second clock cycle.
Preferably, the memory cell, is further used for storing at least one in the memory space successively and meets institute
State the buffered data of incidence relation.
In embodiments of the present invention, in order to which there is comparativity the clock cycle of clock to be monitored and reference clock, so according to
The target clock cycle set in advance, by clock cycle frequency modulation to be monitored to the first clock cycle, and by reference clock
Clock cycle frequency modulation is stored at least one verification in each first clock cycle to the second clock cycle into memory space
Data, be in order to read at least one verification data more first stored from memory space in each second clock cycle, by
In the finite capacity of memory space, when the first clock cycle is different from the second clock cycle, the school in memory space can be caused
Test data spilling or verification data is not present so that the verification data read out from memory space produces corresponding change.
It therefore, it can the verification data by being read from memory space, to determine that the first clock cycle and second clock cycle are
It is no identical, it may thereby determine that whether clock to be monitored is abnormal, and realization is monitored to system clock.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is a kind of flow chart for system clock monitoring method that one embodiment of the invention is provided；
Fig. 2 is the flow chart for another system clock monitoring method that one embodiment of the invention is provided；
Fig. 3 is the flow chart for another system clock monitoring method that one embodiment of the invention is provided；
Fig. 4 is the flow chart for another system clock monitoring method that one embodiment of the invention is provided；
Fig. 5 is a kind of structural representation for system clock supervising device that one embodiment of the invention is provided；
Fig. 6 is the structural representation for another system clock supervising device that one embodiment of the invention is provided；
Fig. 7 is the structural representation for another system clock supervising device that one embodiment of the invention is provided.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments, based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained on the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in figure 1, the embodiments of the invention provide a kind of system clock monitoring method, this method can include following step
Suddenly：
Step 101：According to the target clock cycle set in advance, the clock cycle for treating monitoring clock is carried out at frequency modulation
Reason, obtained for the first clock cycle；
Step 102：According to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, the is obtained
Two clock cycle；
Step 103：In each described first clock cycle, at least one is stored into the memory space with preset capacity
Individual verification data, wherein, in the off-capacity of the memory space, the data longer to storage time are covered；
Step 104：In each described second clock cycle, at least one more first stored is read from the memory space
The individual verification data, and at least one described verification data described in reading deletes from the memory space, wherein,
When the memory space is when in the absence of the verification data, reads specific data and be used as the verification data；
Step 105：The verification data according at least two read the continuous two second clock cycles, sentences
Whether the clock to be monitored that breaks is abnormal.
In embodiments of the present invention, in order to which there is comparativity the clock cycle of clock to be monitored and reference clock, so according to
The target clock cycle set in advance, by clock cycle frequency modulation to be monitored to the first clock cycle, and by reference clock
Clock cycle frequency modulation is stored at least one verification in each first clock cycle to the second clock cycle into memory space
Data, be in order to read at least one verification data more first stored from memory space in each second clock cycle, by
In the finite capacity of memory space, when the period 1 is different from second round, the verification data in memory space can be caused to overflow
Go out or verification data is not present so that the verification data read out from memory space produces corresponding change.It therefore, it can
By the verification data read from memory space, to determine whether the first clock cycle and second clock cycle are identical, from
And can determine whether clock to be monitored is abnormal, realization is monitored to system clock.
It can be realized, specifically included by the following two kinds mode for step 105：
Mode one：Judge at continuous two second clock cycles, two verification datas read from memory space are
The no incidence relation for meeting two verification datas determined when being stored in continuous two the first clock cycle into memory space,
So that it is determined that whether clock to be monitored is abnormal.
Mode two：The abnormal time occurs for the verification data that record does not meet data correlation relation every time, judges per twice
Verification data occurs whether abnormal time interval is less than default duration threshold value, so as to judge whether clock to be monitored is abnormal.
Judge whether abnormal method is described in detail clock to be monitored below for above two：
For mode one, as shown in Fig. 2 judging whether clock to be monitored occurs abnormal method and can include following step
Suddenly：
Step 201：It is determined that in continuous two the first clock cycle storages at least two in the memory space
Incidence relation between the verification data；
Step 202：Verification data described in judging read the continuous two second clock cycles at least two is
It is no to meet the incidence relation, if it is, performing step 203, otherwise perform step 204.
Step 203：Determine that the clock to be monitored is normal, continue executing with step 202；
Step 204：Determine that the clock to be monitored is abnormal.
The whether abnormal method of the determination clock to be monitored that mode one is provided, is to be read in continuous two second clock cycles
Two verification datas got are object, when two verification datas continuously read do not meet the corresponding pass of two verification datas
Connection relation, may be more than the speed that verification data is read from memory space due to the speed to memory space storage verification data,
The verification data not being read in memory space is caused to be capped so that two verification datas continuously read are not met
Corresponding incidence relation, it is also possible to be less than due to storing the speed of verification data to memory space from memory space reading check number
According to speed, cause the verification data in memory space to be read empty and read specific data, so that continuously reading
Two verification datas do not meet corresponding incidence relation, and the speed of verification data is stored into memory space by clock to be monitored
The actual clock cycle determine, therefore, when two verification datas continuously read it is corresponding with two verification datas association pass
When system is not inconsistent, it is possible to determine that clock to be monitored occurs abnormal.
For mode two, as shown in figure 3, judge clock to be monitored whether occur abnormal method can specifically include it is following
Step：
Step 301：It is determined that in continuous two the first clock cycle storages at least two in the memory space
Incidence relation between the verification data；
Step 302：Verification data described in judging read the continuous two second clock cycles at least two is
It is no to meet the incidence relation, if it is, continuing executing with step 302, otherwise perform step 303；
Step 303：Determine that the verification data occurs abnormal, and record the verification data occur the abnormal time；
Step 304：Judge that the verification data occurs whether abnormal number of times is equal to 2, if it is, step 305 is performed, it is no
Then perform step 302；
Step 305：Judge the abnormal verification data recorded with the last time of the verification data that this is recorded
Whether the time interval between exception is less than default duration threshold value, if it is, performing step 306, otherwise performs step 307；
Step 306：Determine that the clock to be monitored is abnormal, and terminate current process；
Step 307：The frequency of abnormity recorded is reset, and performs step 302.
The whether abnormal method of the determination clock to be monitored that mode two is provided, is that verification data is not met twice with every generation
Corresponding incidence relation is object, when two verification datas that first time continuously reads do not meet corresponding incidence relation,
Do not immediately determine that clock to be monitored occurs abnormal but the abnormal time occurs for record verification data, be due in clock to be monitored
The speed for storing the speed of verification data to memory space and verification data being read from memory space has small deviation, when micro-
Small deviation necessarily occurs that the verification data once continuously read from memory space is not met after prolonged accumulation
The situation of corresponding incidence relation, this is probably the inherent variability of clock to be monitored；Continue to determine and record continuous reading next time
Two verification datas got do not meet the time of corresponding incidence relation, it is determined that twice verification data occur exception after,
It is determined that verification data occurs whether abnormal time interval is less than default duration threshold value twice, if it is abnormal twice occur when
Between interval be less than duration threshold value, there is larger difference in the actual clock cycle and standard clock cycle for illustrating clock to be monitored,
Determine that clock to be monitored is abnormal；If the time difference occurred abnormal twice is more than duration threshold value, illustrate clock to be monitored need through
Cross longer time and add up just to occur once exception, it is normal for now can be determined that clock to be monitored.
The whether abnormal method of the determination clock to be monitored of mode one is applied to require clock to be monitored very accurately feelings
Condition, and the whether abnormal method of determination clock to be monitored that mode two is provided, it is adaptable to which the precise degrees for treating monitoring clock will
Seek general situation.Therefore, mode one and mode two are applied to different application scenarios, can in practical business implementation process
Flexibly to be selected according to the actual requirements, so as to improve the applicability of the method for calibration.
In an embodiment of the present invention, the method for the determination clock exception to be monitored according to aforementioned manner two, in note
Record once after the verification data generation exception, further comprises：
Pause perform described in read in each described second clock cycle from the memory space more first store to
A few verification data, and after pause duration reaches buffering duration set in advance, restart execution described every
One second clock cycle is read from the memory space compared with least one the described verification data first stored；
Wherein, the buffering duration is more than or equal to a second clock cycle.
In an embodiment of the present invention, it is not directly to send after determining and recording that exception occurs for a verification data
Warning message, nor continue to determine and record that the abnormal time occurs for verification data next time, but pause is not less than second
The buffering duration of clock cycle reads verification data from memory space, and the purpose of this way is avoided because into memory space
Storing the speed of the speed of verification data and the reading verification data from memory space has a small deviation, it is caused once from
Two verification datas that memory space is continuously read do not meet corresponding incidence relation and determine clock to be monitored and occur exception
Situation.
In an embodiment of the present invention, it is described according to the target clock cycle set in advance, treat the clock of monitoring clock
Cycle carries out frequency modulation processing, obtains for the first clock cycle, including：
According to target clock cycle set in advance and the ratio of the standard clock cycle of clock to be monitored, the first tune is determined
Frequency parameter, is zoomed in and out using first chirp parameter to the actual clock cycle of the clock to be monitored, when obtaining first
The clock cycle；
It is described according to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, when obtaining second
The clock cycle, including：
According to target period set in advance and the ratio of the clock cycle of reference clock, the second chirp parameter is determined, profit
The clock cycle of the reference clock is zoomed in and out with second chirp parameter, the second clock cycle is obtained.
In embodiments of the present invention, when identified first chirp parameter is equal to the default target clock cycle and is to be monitored
The ratio of the standard clock cycle of clock, identified second chirp parameter is equal to default target clock cycle and reference clock
The ratio of clock cycle, the actual clock cycle for treating monitoring clock using the first chirp parameter zooms in and out, you can obtain the
One clock cycle, the second chirp parameter is recycled to zoom in and out the clock cycle of reference clock, you can to obtain second clock week
Phase, the first chirp parameter and the second chirp parameter are determined, be for acquisition after the actual clock cycle of clock to be monitored is scaled
The first clock cycle with second clock cycle for will being obtained after clock cycle of reference clock scaling by comparativity.
In an embodiment of the present invention, at least one described verification data is stored to described according to establishment order described
Before in memory space, further comprise：
At least one buffered data for meeting the data creation rule is stored in the memory space successively.
In embodiments of the present invention, before clockwise memory space stores at least one verification data when to be monitored, Xiang Cun
At least one buffered data for meeting data creation rule is stored in storage space, the operation of storage buffered data can avoid system
In firm start working, also it is not carried out just having performed from memory space to the operation that memory space stores verification data and reads school
Test the operation of data, caused by read from memory space and determine that abnormal feelings occur for clock to be monitored less than verification data
Condition.
With reference to aforementioned manner two, to a kind of system clock monitoring method provided in an embodiment of the present invention, make further
Describe in detail, as shown in figure 4, this method may comprise steps of：
Step 401：Create the memory space with preset capacity.
Specifically, the memory space with preset capacity is pre-created, is easy to produce at least one school in clock to be monitored
Test after data and store the verification data of generation.
For example, the memory space that a capacity is 1MB is created in the server.
Step 402：At least one buffered data for meeting data creation rule is stored in memory space successively.
Specifically, just started working to before memory space deposit verification data, be stored in into memory space in server
At least one meets the buffered data of data creation rule, prevents server from just starting working, is also not carried out depositing to memory space
The operation for entering verification data has just performed the operation that verification data is read from memory space, and causes to read less than verification data
The abnormal conditions of generation.
For example, each buffer number for being 0.2MB sizes and meeting data creation rule is stored in into memory space
According to A, B, C.
Step 403：Determine the first chirp parameter and the second chirp parameter.
Specifically, according to the clock cycle of the standard clock cycle of clock to be monitored and reference clock, the first frequency modulation is determined
Parameter and the second chirp parameter, wherein, the standard clock cycle of clock to be monitored is the theoretical clock cycle of clock to be monitored.
For example, the clock cycle of the clock source (be clock to be monitored) of server is 0.02s, reference clock when
Clock frequency is 0.05s, in order to which the clock cycle of clock to be monitored and reference clock is all adjusted into target clock cycle 0.1s, can be with
The first chirp parameter for determining clock to be monitored is 5, and the second chirp parameter of reference clock is 2.
Step 404：The actual clock cycle for treating monitoring clock using the first chirp parameter carries out frequency modulation, obtains to be monitored
First clock cycle of clock.
Specifically, in order to by the standard clock cycle of clock to be monitored (be theoretical clock cycle) and reference clock when
Clock cycle all frequency modulation is to the target clock cycle, it is necessary to using the first chirp parameter by the standard clock cycle frequency modulation of clock to be monitored
To the first clock cycle.
For example, using the first chirp parameter 5, by the clock cycle for 0.02s server clock source frequency modulation to clock
Cycle is 0.1s.
Step 405：Frequency modulation is carried out to clock cycle of reference clock using the second chirp parameter, the of reference clock is obtained
Two clock cycle.
Specifically, in order to by the standard clock cycle of the clock cycle of reference clock and clock to be monitored (when being theoretical
The clock cycle) all frequency modulation is to the target clock cycle, it is necessary to using the second chirp parameter by the clock cycle frequency modulation of reference clock to
Two clock cycle.
For example, using the second chirp parameter 2, by the clock cycle for 0.05s reference clock frequency modulation to 0.1s.
Step 406：According to default data creation rule, at least one school is created in each first clock cycle successively
Data are tested, and store at least one verification data into memory space according to establishment order.
Specifically, at least one verification data for meeting data creation rule is created in each first clock cycle, and
The verification data of establishment is stored in memory space successively, is easy to need to read from memory space during verification data, but by
In the finite capacity of memory space, so when the off-capacity of memory space, when the verification data created afterwards can cover storage
Between longer verification data, can be deposited into so as to the verification data that is created after ensuring in memory space.
For example, default data creation rule is to be stored under the 0.1s of first clock to be monitored clock cycle
One verification data a+1, is stored in second verification data a+2, the 3rd under the 0.1s of second clock to be monitored clock cycle
The 3rd verification data a+3 is stored under the 0.1s of individual clock to be monitored clock cycle, the 0.1s's of the 4th clock to be monitored
The 4th verification data a+1 is stored under clock cycle, these three verification datas of circulation deposit a+1, a+2, a+3 are in memory space
(verification data a+1, a+2, a+3 are the verification data for meeting data creation rule), the size of each verification data is
0.2MB.For example, under the 0.1s of first clock to be monitored clock cycle, verification data a+1 can be produced, a+1 is deposited
Store up in space, under the 0.1s of second clock to be monitored clock cycle, verification data a+2 can be produced, a+2 is stored in and stored
In space.Due to data cached, the remaining memory space that the capacity of memory space is existing 0.5MB in 1MB, and memory space
Capacity can only be stored in two verification datas of a+1 and a+2 for 0.5MB, if the clock of the 0.1s in the 3rd clock to be monitored
Under cycle, produce after verification data a+3, want that verification data a+3 is stored in into memory space stores, it is necessary to cover in memory space
Time longer verification data a+1.
Step 407：In each second clock cycle, at least one longer school of storage time is read from memory space
Data are tested, and the verification data being read in memory space is deleted.
Specifically, due to the finite capacity of memory space, so in each second clock cycle, when from memory space
The data are deleted after the longer verification data of reading storage time, are easy to the capacity of release memory space in time.Work as storage
When verification data is not present in space, specific data are read as verification data, such as specific data are b.
For example, in the 0.1s of first reference clock clock cycle, memory space is stored according to verification data
Order, the longer verification data a+1 of storage time is read in memory space, after reading verification data a+1, by check number
Deleted according to a+1 from memory space.In the 0.1s of second reference clock clock cycle, storage is read in memory space
Time longer verification data a+2, reads after verification data a+2, verification data a+2 is deleted from memory space.
Step 408：Judge whether meet number at least two verification datas that continuous two second clock cycles read
According to rule is created, if it is, performing step 409, step 410 is otherwise performed.
Specifically, according to the verification data read from memory space, two check numbers continuously read are judged successively
According to whether verification data rule is met, so that it is determined that to be monitored whether abnormal all the time.
For example, if in first 0.1s of reference clock clock cycle and second 0.1s clock cycle
When, the verification data a+1 and a+2 read out from memory space is clock to be monitored in first 0.1s and second 0.1s
Clock cycle when the verification data a+1 and a+2 that are stored in, it may be determined that clock to be monitored is normal.
If in first 0.1s and second 0.1s of reference clock clock cycle, read out from memory space
Verification data a+2 and a+3, verification data a+1 and a that not to be clock to be monitored be stored in first 0.1s clock cycle
+ 2, it may be determined that clock to be monitored occurs abnormal.
Step 409：It is determined that current verification data meets data creation rule, and continue executing with step 408.
Specifically, according to data creation rule and the verification data contrast currently read, confirm to meet data creation rule
After then, continue to confirm whether next verification data read out from memory space meets data creation rule.
For example, in first 0.1s of reference clock clock cycle, the verification read out from memory space
Verification data a+1 and a+2 that data a+1 and a+2 are clocks to be monitored to be stored in first 0.1s clock cycle, it is determined that
Meet data creation rule, continue to verify next verification data read out from memory space.
Step 410：Determine that verification data occurs abnormal, and record the verification data occur the abnormal time.
Specifically, it is determined that the verification data read out from memory space do not meet data creation rule after, determine the school
Test data and occur exception, and record once the verification data and occur the abnormal time, it is abnormal in verification data generation of record
Afterwards, it is not direct alert, nor continue to determine and record that the abnormal time occurs for verification data next time, but
Pause reads verification data not less than the buffering duration in second clock cycle from memory space, the purpose of this way be avoid because
The speed of verification data is read for the speed of storage verification data into memory space and from memory space small deviation,
Caused two verification datas once continuously read from memory space do not meet corresponding incidence relation and determine to wait to supervise
Control clock and occur abnormal situation, after pause duration is reached, continue to determine next verification for not meeting data creation rule
Data, and record the time that exception occurs for the verification data.
For example, because exception occurs for the actual clock cycle of clock to be monitored, 0.04s is become by original 0.02s,
After the frequency modulation of the first chirp parameter 5, the clock cycle of clock to be monitored is changed into 0.2s.
It is empty in storage that clock to be monitored has been stored in two verification datas of a+1 and a+2 in first 0.2s clock cycle
Between in, in first 0.1s of reference clock clock cycle, from memory space read verification data a+1, read after a+1
Verification data a+1 is deleted, now residue check data a+2 in memory space；
Clock to be monitored is stored in a+3 and a+1 again in second 0.2s clock cycle, in second 0.1s of reference clock
When, it should that read is a+2, but because the a+3 and a+1 of deposit cover a+2, so that read is a+3, according to even
A+1 and a+3 that continuous twi-read is arrived, it is determined that not in accordance with the a+1 and a+2 of order deposit, it is possible to determine that verification data is sent out
Raw abnormal, exception occurs for record verification data in second 0.1s of reference clock clock cycle, now in memory space
Remaining verification data is a+1, and one 0.1s of pause buffering duration reads verification data from memory space；
In the 0.1s of pause, clock to be monitored is stored in a being stored in before two verification datas of a+2 and a+3, and covering again
+ 1, in the 3rd 0.1s of reference clock, it should read out a+3 from memory space, but actually read out for a+2, root
According to upper one a+3 read the and a+2 currently read, determine that verification data occurs abnormal, record verification data is in reference
Second of exception occurs during the 3rd 0.1s of clock.
Step 411：Judge that verification data occurs whether abnormal number of times is equal to 2, if it is, performing step 412, otherwise holds
Row step 408.
Specifically, it not can determine that clock to be monitored occurs when first time verification data occurs abnormal abnormal, be because treating
Monitoring clock is possible to the clock cycle deviation because small, caused once abnormal after long term accumulation, but needs true
The fixed verification data twice abnormal time difference judges, so needing first to determine that verification data occurs whether abnormal number of times is equal to
2。
For example, if abnormal number of times, which occurs, for record verification data is equal to 2, when further determining abnormal twice
Between it is poor.
If recording verification data occurs abnormal number of times less than 2, continue to judge that exception occurs for next verification data
Whether number of times is equal to 2.
Step 412：Whether determine the abnormal time interval between first time generation exception of second of generation of verification data
Less than duration threshold value set in advance, if it is, performing step 414, step 413 is otherwise performed.
Specifically, it is determined that verification data occurs whether the abnormal time difference meets duration threshold value set in advance twice, from
And determine whether clock to be monitored is abnormal.
For example, duration threshold value set in advance is 0.5s, occurs data exception due to first time and occurs for the second time
The time difference of data exception is 0.1s, less than duration threshold value 0.5s, can be with so determining that clock to be monitored is abnormal.
If the time difference that data exception and second of generation data exception occur for the first time is 0.6s, not less than duration threshold
Value 0.5s, it may be determined that clock to be monitored is normal.
Step 413：Determine that clock to be monitored is normal, and continue executing with step 408.
Specifically, duration threshold value of the abnormal time difference not less than setting occurs for verification data twice, it may be determined that wait to supervise
Control clock normal.
For example, if the time difference that data exception and second of generation data exception occur for the first time is 0.1s, no
Less than duration threshold value, it may be determined that clock to be monitored is normal.
Step 414：Determine that clock to be monitored is abnormal, and alert.
Specifically, duration threshold value of the abnormal time difference less than setting is occurred according to verification data twice, it may be determined that treat
Exception occurs for monitoring clock, to server alert.
For example, it is small if the time difference that data exception and second of generation data exception occur for the first time is 0.1s
The 0.5s set in duration threshold value, it may be determined that clock to be monitored is abnormal, sends clock speed to be monitored to server too fast
Warning message.
As shown in figure 5, the embodiments of the invention provide a kind of system clock supervising device, including：
Frequency modulation processing unit 501, memory cell 502, reading unit 503 and judging unit 504；
The frequency modulation processing unit 501, for according to the target clock cycle set in advance, treating the clock of monitoring clock
Cycle carries out frequency modulation processing, obtained for the first clock cycle, is additionally operable to according to the target clock cycle, to the clock of reference clock
Cycle carries out frequency modulation processing, obtains the second clock cycle；
The memory cell 502, for each the described first clock week obtained in the frequency modulation processing unit 501
Phase, at least one verification data is stored into the memory space with preset capacity, wherein, the memory space capacity not
The data longer to storage time are covered when sufficient；
The reading unit 503, for each the described second clock week obtained in the frequency modulation processing unit 501
Phase, read from the memory space memory cell 502 compared with least one the described verification data first stored, and will read
At least one the described described verification data got is deleted from the memory space, wherein, when the memory space is not being deposited
In the verification data, read specific data and be used as the verification data；
The judging unit 504, for being read according to the reading unit 503 the continuous two second clock cycles
Verification data described at least two arrived, judges whether the clock to be monitored is abnormal.
Based on a kind of system clock supervising device shown in Fig. 5, in one embodiment of the invention, as shown in fig. 6, described judge
Unit 504 includes：First determination subelement 5041 and the first judgment sub-unit 5042；
First determination subelement 5041, for determining to deposit described in continuous two the first clock cycle storages
Store up the incidence relation between verification data described at least two in space；
First judgment sub-unit 5042, for judging to read at least the continuous two second clock cycles
Whether two verification datas meet the incidence relation that first determination subelement 5041 is determined, if it is, determining
The clock to be monitored is normal, otherwise determines that the clock to be monitored is abnormal.
Based on a kind of system clock supervising device shown in Fig. 5, in one embodiment of the invention, as shown in fig. 7, described
Judging unit 504 includes：Second determination subelement 5043 and the second judgment sub-unit 5044；
Second determination subelement 5043, it is determined that empty to the storage in continuous two the first clock cycle storages
Between at least two described in incidence relation between verification data；
Second judgment sub-unit 5044, for judging to read at least the continuous two second clock cycles
Whether two verification datas meet the incidence relation that second determination subelement 5043 is determined, if not, record
Verification data exception, is additionally operable to judge the abnormal school recorded with the last time of the verification data that this is recorded
Whether the time interval tested between data exception is less than default duration threshold value, if it is, determine that the clock to be monitored is abnormal,
Otherwise determine that the clock to be monitored is normal.
In an embodiment of the present invention,
The frequency modulation processing unit, for the standard time clock according to target clock cycle set in advance and clock to be monitored
The ratio in cycle, determines the first chirp parameter, utilizes actual clock week of first chirp parameter to the clock to be monitored
Phase zooms in and out, and obtained for the first clock cycle, is additionally operable to the clock cycle according to target period set in advance and reference clock
Ratio, determine the second chirp parameter, the clock cycle of the reference clock zoomed in and out using second chirp parameter,
Obtain the second clock cycle；
In an embodiment of the present invention, second judgment sub-unit, for the verification data to be sent out for the first time in record
After raw exception, the reading unit is triggered；
The reading unit, is further used for when receiving the triggering of the record subelement, pause perform it is described
Each described second clock cycle is read from the memory space compared with least one the described verification data first stored, and
Pause duration reached after buffering duration set in advance, restart to perform it is described in each described second clock cycle from institute
At least one the described verification data read in memory space compared with first storing is stated, wherein, the buffering duration is more than or equal to one
The individual second clock cycle.
In an embodiment of the present invention, the memory cell, be further used for storing in the memory space successively to
Lack a buffered data for meeting the incidence relation.
In embodiments of the present invention, in order to which there is comparativity the clock cycle of clock to be monitored and reference clock, so frequency modulation
Processing unit is according to the target clock cycle set in advance, by clock cycle frequency modulation to be monitored to the first clock cycle, and
By the clock cycle frequency modulation of reference clock to second clock cycle, memory cell obtained in each frequency modulation processing unit first
At least one verification data is stored in during the clock cycle into memory space, is in order to which reading unit is in each frequency modulation processing unit
The second clock cycle of acquisition reads at least one verification data more first stored from memory space, due to the appearance of memory space
Amount is limited, when the first clock cycle is different from the second clock cycle, and the verification data in memory space can be caused to overflow or school
Test data to be not present so that the verification data read out from memory space produces corresponding change.Therefore, judging unit can
With the verification data read by reading unit from memory space, to determine that the first clock cycle and second clock cycle are
It is no identical, it may thereby determine that whether clock to be monitored is abnormal, and realization is monitored to system clock.
Each embodiment of the invention at least has the advantages that：
1st, in embodiments of the present invention, in order to which there is comparativity the clock cycle of clock to be monitored and reference clock, so root
According to the target clock cycle set in advance, by clock cycle frequency modulation to be monitored to the first clock cycle, and by reference clock
Clock cycle frequency modulation to the second clock cycle, at least one school is stored in into memory space in each first clock cycle
Test data, be in order to read at least one verification data more first stored from memory space in each second clock cycle,
Due to the finite capacity of memory space, when the first clock cycle is different from the second clock cycle, it can cause in memory space
Verification data is overflowed or verification data is not present so that the verification data read out from memory space produces corresponding change
Change.It therefore, it can the verification data by being read from memory space, to determine the first clock cycle and second clock cycle
It is whether identical, it may thereby determine that whether clock to be monitored is abnormal, and realization is monitored to system clock.
2nd, in the embodiment of the present invention, the whether abnormal method of the determination clock to be monitored that mode one is provided, is with continuous
Two verification datas that two second clock cycles read are object, when two verification datas continuously read do not meet two
The corresponding incidence relation of individual verification data, may be more than from memory space due to storing the speed of verification data to memory space and read
The speed of verification data is taken, causes the verification data not being read in memory space to be capped so that continuously to read
Two verification datas do not meet corresponding incidence relation, it is also possible to due to memory space store verification data speed be less than from
Memory space reads the speed of verification data, causes the verification data in memory space to be read empty and read specific data, from
And make it that two verification datas continuously read do not meet corresponding incidence relation, and verification data is stored into memory space
Speed determined by the actual clock cycle of clock to be monitored, therefore, when two verification datas continuously reading and two schools
When testing the corresponding incidence relation of data and not being inconsistent, it is possible to determine that clock to be monitored occurs abnormal.
3rd, in embodiments of the present invention, the whether abnormal method of mode two is provided determination clock to be monitored, is with every hair
Raw verification data twice does not meet corresponding incidence relation for object, when two verification datas that first time continuously reads are not inconsistent
When closing corresponding incidence relation, when not immediately determining that clock to be monitored occurs abnormal but record verification data and occurs abnormal
Between, it is due to the speed of the clockwise memory space storage verification data when to be monitored with reading verification data from memory space
Speed has small deviation, when small deviation is after prolonged accumulation, necessarily occurs once continuous from memory space
The verification data read does not meet the situation of corresponding incidence relation, and this is probably the inherent variability of clock to be monitored；Continue
Determine and record that two verification datas continuously read next time do not meet the time of corresponding incidence relation, it is determined that twice
Verification data occurs after exception, it is determined that verification data occurs whether abnormal time interval is less than default duration threshold twice
Value, if the time interval occurred abnormal twice is less than duration threshold value, illustrates actual clock cycle and the standard of clock to be monitored
There is larger difference in the clock cycle, determine that clock to be monitored is abnormal；If the time difference occurred abnormal twice is more than duration threshold
Value, illustrates that clock to be monitored needs that once exception just occurs by longer time is accumulative, when now can be determined that to be monitored
Clock is normal.
4th, in embodiments of the present invention, in an embodiment of the present invention, determining and recording that it is different that a verification data occurs
It is not direct alert after often, nor continue to determine and record that the abnormal time occurs for verification data next time,
But pause reads verification data not less than the buffering duration in second clock cycle from memory space, the purpose of this way is to keep away
Exempt from because the speed of verification data is stored into memory space has small with reading the speed of verification data from memory space
Deviation, caused two verification datas once continuously read from memory space do not meet corresponding incidence relation and determined
Abnormal situation occurs for clock to be monitored.
5th, in embodiments of the present invention, identified first chirp parameter is equal to the default target clock cycle and to be monitored
The ratio of the standard clock cycle of clock, identified second chirp parameter is equal to default target clock cycle and reference clock
Clock cycle ratio, the actual clock cycle for treating monitoring clock using the first chirp parameter zooms in and out, you can obtain
First clock cycle, the second chirp parameter is recycled to zoom in and out the clock cycle of reference clock, you can to obtain second clock
In the cycle, determine the first chirp parameter and the second chirp parameter, be in order to will the actual clock cycle of clock to be monitored scale after obtain
The first clock cycle with second clock cycle for will being obtained after clock cycle of reference clock scaling by comparativity.
6th, in embodiments of the present invention, in embodiments of the present invention, the clockwise memory space storage at least one when to be monitored
Before individual verification data, at least one buffered data for meeting data creation rule is stored in into memory space, buffer number is stored
According to operation can avoid system in firm start working, be also not carried out having stored the operation of verification data just to memory space
Perform the operation that verification data is read from memory space, caused by read from memory space and determine to wait to supervise less than verification data
Control clock and occur abnormal situation.
It should be noted that herein, such as first and second etc relational terms are used merely to an entity
Or operation makes a distinction with another entity or operation, and not necessarily require or imply exist between these entities or operation
Any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant be intended to it is non-
It is exclusive to include, so that process, method, article or equipment including a series of key elements not only include those key elements,
But also other key elements including being not expressly set out, or also include solid by this process, method, article or equipment
Some key elements.In the absence of more restrictions, by sentence " including the key element that a 〃 〃 " is limited, it is not excluded that
Also there is other identical factor in the process including the key element, method, article or equipment.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
Programmed instruction related hardware is completed, and foregoing program can be stored in the storage medium of embodied on computer readable, the program
Upon execution, the step of including above method embodiment is performed；And foregoing storage medium includes：ROM, RAM, magnetic disc or light
Disk etc. is various can be with the medium of store program codes.
It is last it should be noted that：Presently preferred embodiments of the present invention is the foregoing is only, the skill of the present invention is merely to illustrate
Art scheme, is not intended to limit the scope of the present invention.Any modification for being made within the spirit and principles of the invention,
Equivalent substitution, improvement etc., are all contained in protection scope of the present invention.
Claims (10)
1. a kind of system clock monitoring method, it is characterised in that including：
According to the target clock cycle set in advance, the clock cycle for treating monitoring clock carries out frequency modulation processing, when obtaining first
The clock cycle；
According to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, the second clock cycle is obtained；
In each described first clock cycle, at least one verification data is stored into the memory space with preset capacity,
Wherein, the data longer to storage time in the off-capacity of the memory space are covered；
In each described second clock cycle, read from the memory space compared with least one the described check number first stored
According to, and at least one described verification data described in reading deletes from the memory space, wherein, when the storage is empty
Between when in the absence of the verification data, read specific data and be used as the verification data；
The verification data according at least two read the continuous two second clock cycles, judges described to be monitored
Whether clock is abnormal.
2. according to the method described in claim 1, it is characterised in that
The basis read the continuous two second clock cycles at least two described in verification data judge described in treat
Whether monitoring clock is abnormal, including：
It is determined that in continuous two the first clock cycle storages to verification data described at least two in the memory space
Between incidence relation；
Whether verification data described in judging read the continuous two second clock cycles at least two meets the pass
Connection relation；
If it is, determining that the clock to be monitored is normal, otherwise determine that the clock to be monitored is abnormal；
And/or
The basis read the continuous two second clock cycles at least two described in verification data judge described in treat
Whether monitoring clock is abnormal, including：
It is determined that in continuous two the first clock cycle storages to verification data described at least two in the memory space
Between incidence relation；
Whether verification data described in judging read the continuous two second clock cycles at least two meets the pass
Connection relation, if not, verification data exception of record；
Judge between the abnormal verification data exception recorded the last time of described verification data that this is recorded when
Between be spaced whether be less than default duration threshold value, if it is, determining that the clock to be monitored is abnormal, otherwise determine described to be monitored
Clock is normal.
3. method according to claim 2, it is characterised in that
After the record once the verification data exception, further comprise：
Pause reads at least one more first stored in each described second clock cycle described in performing from the memory space
The individual verification data, and after pause duration reaches buffering duration set in advance, restart execution described at each
The second clock cycle is read from the memory space compared with least one the described verification data first stored；
Wherein, the buffering duration is more than or equal to a second clock cycle.
4. according to the method described in claim 1, it is characterised in that
Described the clock cycle for treating monitoring clock carries out frequency modulation processing according to the target clock cycle set in advance, obtains the
One clock cycle, including：
According to target clock cycle set in advance and the ratio of the standard clock cycle of clock to be monitored, determine that the first frequency modulation is joined
Number, is zoomed in and out using first chirp parameter to the actual clock cycle of the clock to be monitored, obtains the first clock week
Phase；
It is described that frequency modulation processing is carried out to the clock cycle of reference clock according to the target clock cycle, obtain second clock week
Phase, including：
According to target period set in advance and the ratio of the clock cycle of reference clock, the second chirp parameter is determined, institute is utilized
State the second chirp parameter to zoom in and out the clock cycle of the reference clock, obtain the second clock cycle.
5. according to any described method in claim 2 to 3, it is characterised in that
Described in each described first clock cycle, at least one verification is stored into the memory space with preset capacity
Before data, further comprise：
At least one buffered data for meeting the incidence relation is stored in the memory space successively.
6. a kind of system clock supervising device, it is characterised in that including：Frequency modulation processing unit, memory cell, reading unit and sentence
Disconnected unit；
The frequency modulation processing unit, for according to the target clock cycle set in advance, the clock cycle for treating monitoring clock to enter
The processing of row frequency modulation, obtained for the first clock cycle, is additionally operable to, according to the target clock cycle, enter the clock cycle of reference clock
The processing of row frequency modulation, obtains the second clock cycle；
The memory cell, for each described first clock cycle obtained in the frequency modulation processing unit, to pre-
If storing at least one verification data in the memory space of capacity, wherein, in the off-capacity of the memory space to storage
Time longer data are covered；
The reading unit, for each the described second clock cycle obtained in the frequency modulation processing unit, is deposited from described
Read in storage space the memory cell compared with least one the described verification data first stored, and described in reading at least
One verification data is deleted from the memory space, wherein, when the memory space is in the absence of the verification data
When, read specific data and be used as the verification data；
The judging unit, for read according to the reading unit the continuous two second clock cycles at least two
The individual verification data, judges whether the clock to be monitored is abnormal.
7. device according to claim 6, it is characterised in that
The judging unit includes：First determination subelement and the first judgment sub-unit；
First determination subelement, for determining in continuous two the first clock cycle storages into the memory space
At least two described in incidence relation between verification data；
First judgment sub-unit, for judge to read the continuous two second clock cycles at least two described in
Whether verification data meets the incidence relation that first determination subelement is determined, if it is, when determining described to be monitored
Clock is normal, otherwise determines that the clock to be monitored is abnormal；
And/or
The judging unit includes：Second determination subelement and the second judgment sub-unit；
Second determination subelement, it is determined that being stored in continuous two first clock cycle into the memory space extremely
Incidence relation between few two verification datas；
Second judgment sub-unit, for judge to read the continuous two second clock cycles at least two described in
Whether verification data meets the incidence relation that second determination subelement is determined, if not, verification data of record
It is abnormal, it is additionally operable to judge the verification data exception and the last verification data exception recorded that this is recorded
Between time interval whether be less than default duration threshold value, if it is, determining that the clock to be monitored is abnormal, otherwise determine described
Clock to be monitored is normal.
8. device according to claim 7, it is characterised in that
Second judgment sub-unit, is further used for after record once the verification data generation exception, reads described
Unit is taken to be triggered；
The reading unit, is further used for when receiving the triggering of second judgment sub-unit, pause perform it is described
Each described second clock cycle is read from the memory space compared with least one the described verification data first stored, and
Pause duration reached after buffering duration set in advance, restart to perform it is described in each described second clock cycle from institute
At least one the described verification data read in memory space compared with first storing is stated, wherein, the buffering duration is more than or equal to one
The individual second clock cycle.
9. device according to claim 6, it is characterised in that
The frequency modulation processing unit, for the standard clock cycle according to target clock cycle set in advance and clock to be monitored
Ratio, determine the first chirp parameter, the actual clock cycle of the clock to be monitored entered using first chirp parameter
Row scaling, obtained for the first clock cycle, is additionally operable to the ratio of the clock cycle according to target period set in advance and reference clock
Value, is determined the second chirp parameter, the clock cycle of the reference clock is zoomed in and out using second chirp parameter, is obtained
The second clock cycle.
10. according to any described device in claim 7 to 8, it is characterised in that
The memory cell, is further used for storing at least one in the memory space successively and meets the incidence relation
Buffered data.
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| CN201710455971.9A CN107272822A (en) | 2017-06-16 | 2017-06-16 | A kind of system clock monitoring method and device |
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Cited By (1)
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| CN111061802A (en) * | 2019-12-26 | 2020-04-24 | 宁波三星医疗电气股份有限公司 | Power data management processing method and device and storage medium |
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