CN105718413A - Channel alignment method, device and system - Google Patents
Channel alignment method, device and system Download PDFInfo
- Publication number
- CN105718413A CN105718413A CN201610025318.4A CN201610025318A CN105718413A CN 105718413 A CN105718413 A CN 105718413A CN 201610025318 A CN201610025318 A CN 201610025318A CN 105718413 A CN105718413 A CN 105718413A
- Authority
- CN
- China
- Prior art keywords
- alignment
- secondary channels
- data
- data cached
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a channel alignment method, device and system. The method comprises the following steps: determining a main channel in a channel set to be aligned as a main channel and other channels as auxiliary channels; configuring the same alignment clock for each channel, and converting the data received by each channel to the clock of the alignment clock, and storing into a cache; if an alignment field is detected in the data received by the main channel, configuring the alignment field search range of each piece of auxiliary channel cache data according to the detected alignment field, and detecting whether each auxiliary channel cache data contains the alignment field in the corresponding alignment field search range or not; and for main channel cache data and the auxiliary channel cache data which is detected to have the alignment field, according to the detected alignment field and a current read cache data address, regulating the read cache data address, and starting to read the cache data on the position corresponding to the alignment field according to the regulated read cache data address. Through the above technical scheme, the method solves the problem that a traditional channel alignment scheme is not perfect.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of passage alignment schemes, Apparatus and system.
Background technology
In high speed serialization receive-transmit system, Physical Coding Sublayer (physicalcodingsub-layer, PCS) completes the transmitting-receiving of data stream, it is provided that the functions such as the coding of data stream of one or more passage, decoding, alignment.It is generally required to support popular serial protocol, such as 1 gigabit Ethernet, 10 gigabit Ethernets (XAUI), PCIExpress, Serial, RapidIO, SMPTE (TheSocietyofMotionPictureandTelevisionEngineers), support wireless protocols, such as CPRI, OBSAI etc., for single passage, it is easier to realize supporting various protocols, but for two or more passages, owing to the clock phase of each routing restoration is inconsistent, the alignment characters of different agreement, the regions of search of protocol requirement etc. are all inconsistent, add stone working clock frequency higher, it is bigger that passage alignment realizes difficulty.
Prior art, including below step: the data that detecting multichannel arrives, controls the buffer memory of each channel data according to the alignment field detected;Start to read data from the original position of each channel data of buffer memory simultaneously.This scheme just can start write data after alignment field have to being detected, and need the extra data controlling to remove each passage again to align when aliging unsuccessfully, data form is all had particular requirement by these, and needs extra control, realizes underaction from hardware.
Summary of the invention
The present invention provides a kind of passage alignment schemes, Apparatus and system, solves the problem that existing passage alignment scheme is perfect not.
For solving above-mentioned technical problem, the present invention by the following technical solutions:
A kind of passage alignment schemes, including:
Determining a main channel from channel set to be aligned, other are secondary channels;And configure identical alignment clock to each passage, each channel reception data are transformed into the clock of described alignment clock and are stored in buffer memory;
If main channel receives in data alignment field detected, then according to the alignment field searches scope that each secondary channels of alignment field configuration detected is data cached, and detect each secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field;
Secondary channels that is data cached for main channel and that alignment field detected is data cached, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.
In certain embodiments, each channel reception data are stored in the process of buffer memory, also include: detect the alignment field in each channel reception data, testing result is stored in buffer memory together with each channel reception data;
Within the scope of corresponding alignment field searches, whether have alignment field during each secondary channels of described detection is data cached particularly as follows: detect according to the testing result in buffer memory each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
In certain embodiments, the alignment clock of each passage, particularly as follows: receive, from main channel, the recovered clock obtaining main channel data, is configured to the recovered clock of main channel by the described alignment clock identical to the configuration of each passage.
In certain embodiments, if described main channel receives in data and alignment field detected, then according to the alignment field searches scope that each secondary channels of alignment field configuration that detects is data cached, and detect each secondary channels data cached in whether have within the scope of corresponding alignment field searches align field particularly as follows:
If main channel receives in data and alignment field detected, then main channel notice neighboring later stage secondary channels, after described rear stage secondary channels receives notice, continues to notify rear stage secondary channels again, until each secondary channels is all notified in described channel set to be aligned;And notified each secondary channels receives, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected in data is data cached, in the same time, each secondary channels detect this secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
In certain embodiments, above-mentioned passage alignment schemes also includes preserving following information: the position of the alignment field of each alignment channel, and the data cached address of reading after adjustment;Or read the side-play amount of data cached address.
In certain embodiments, above-mentioned passage alignment schemes, before preserving above-mentioned information, also includes: judge in described channel set to be aligned, whether each passage all completes to read the adjustment of data cached address;If so, the step preserving above-mentioned information is then entered.
A kind of passage alignment means, including:
Determining module, for determining a main channel from channel set to be aligned, other are secondary channels;
Clock configuration module, for the alignment clock identical to the configuration of each passage;
Modular converter, for being transformed into the clock zone of described alignment clock by each channel reception data;
Buffer memory writing module, for being stored in buffer memory by each channel reception data after clock domain is changed;
Main channel alignment field detection module, receives the alignment field in data for detecting main channel;
Scope configuration module, detects alignment field if receiving in data for main channel, then according to the alignment field searches scope that each secondary channels of alignment field configuration detected is data cached;
Secondary channels alignment field detection module, for detect each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field;
Buffer memory read module, data cached for secondary channels that is data cached for main channel and that alignment field detected, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.
In certain embodiments, secondary channels alignment field detection module includes:
First detection sub-module, receives each secondary channels in the process that data write buffer memory for described buffer memory writing module, detects each secondary channels and receives the alignment field in data, obtains testing result;
Second detection sub-module, for according to the described testing result in buffer memory detect corresponding secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field;
Described buffer memory writing module is stored in buffer memory for described testing result being received with each secondary channels together with data.
In certain embodiments, the alignment clock of each passage, specifically for receiving the recovered clock obtaining main channel in data from main channel, is configured to the recovered clock of main channel by described clock configuration module.
In certain embodiments, above-mentioned passage alignment means, also include preserving module, for preserving the position of the alignment field of each alignment channel, and the data cached address of reading after adjustment;Or preserve the side-play amount reading data cached address.
In certain embodiments, above-mentioned passage alignment means, also include judge module, for judging in described channel set to be aligned, whether each passage all completes to read the adjustment of data cached address;If so, then notify that described preservation module carries out above-mentioned information preservation.
A kind of passage alignment, including:
Determining unit, for determining a main channel from channel set to be aligned, other are secondary channels;
Clock dispensing unit, for the alignment clock identical to the configuration of each passage;
Converting unit, for being transformed into the clock zone of described alignment clock by each channel reception data;
Main channel processing unit, is stored in buffer memory for the main channel after clock domain is changed receives data, and detection main channel receives the alignment field in data, if main channel receives in data alignment field detected, then and notice neighboring later stage secondary channels;It is additionally operable to according to the alignment field that detects and current reads data cached address, adjusting and read data cached address, according to the data cached address of reading after adjusting, starting to read data cached from the align position of field of correspondence;
At least one secondary channels processing unit, each secondary channels processing unit is stored in buffer memory for this secondary channels after clock domain is changed is received data, after receiving notice, to rear stage secondary channels transmission notice again until afterbody secondary channels;Receive in data, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected is data cached, detect this secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field;It is additionally operable to according to the alignment field that detects and current reads data cached address, adjusting and read data cached address, according to the data cached address of reading after adjusting, starting to read data cached from the align position of field of correspondence.
In certain embodiments, each secondary channels processing unit is specifically for receiving in the process that data write buffer memory by this secondary channels, detect each secondary channels and receive the alignment field in data, obtain testing result, described testing result is received with this secondary channels and together with data, is stored in buffer memory;And according to the described testing result in buffer memory detect this secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
In certain embodiments, main channel processing unit, each secondary channels processing unit are additionally operable to preserve the position of the alignment field detected and the data cached address of reading after adjustment;Or preserve the side-play amount reading data cached address.
In certain embodiments, main channel processing unit is additionally operable to receive the feedback information that each secondary channels processing unit is transmitted by interchannel cascade signal, judges in described channel set to be aligned, whether all passages complete alignment according to the feedback information of described each secondary channels processing unit.
The present invention is by distinguishing main channel and secondary channels, secondary channels is only after main channel receives and alignment field detected in data, just begin within the scope of the alignment field searches of correspondence and detected whether alignment field, finally, each passage (including main channel) finding alignment field adjusts reads data cached address by alignment of data.As long as secondary channels receives data and receives the skew that data existence is corresponding with main channel, when losing alignment or data packet format change etc., need not additionally empty buffer memory, can realize constantly aliging with main channel, while not increasing design complexities, add the motility of design.
Further, in the process that each channel reception data are carried out buffer memory, alignment field in each channel reception data of synchronous detecting, for each secondary channels, then testing result is received with each secondary channels and be stored in buffer memory together with data, after main channel receives and alignment field detected in data, for each secondary channels, then within the scope of corresponding alignment field searches, detect whether alignment field by this testing result in buffer memory, further increased the detection efficiency of alignment field, improve alignment efficiency.
Further, each passage (including main channel) finding alignment field adjust read data cached address by alignment of data after, preserve the data cached address of reading after the position of corresponding alignment field and adjustment;Or preserve the side-play amount reading data cached address.Therefore if owing to channel failure or other reason lose alignment, it is not required to remove channel data, it is only necessary to recalculate side-play amount.
Furthermore, it is possible to adopt the cascade signal in interchannel transmission, it is achieved multichannel alignment.Concrete: main channel detects after having alignment field in this main channel reception data, main channel notice rear stage secondary channels, after this rear stage secondary channels receives notice, continue to notify rear stage secondary channels again, until each secondary channels is all notified in channel set to be aligned;Notified each secondary channels is while notified or postpones certain time and receives, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected in data is data cached, and detect this secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field, finally, each passage can simultaneously according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence, it is achieved passage aligns.
Accompanying drawing explanation
The flow chart of the passage alignment schemes that Fig. 1 provides for one embodiment of the invention;
The flow chart of the passage alignment schemes that Fig. 2 provides for another embodiment of the present invention;
The schematic diagram of the passage alignment means that Fig. 3 provides for one embodiment of the invention;
The schematic diagram of the passage alignment that Fig. 4 provides for one embodiment of the invention.
Detailed description of the invention
Channel set to be aligned in the present invention can be all passages in system, or passage portion, at least includes two passages.Before alignment of data, data cannot form correct packet; in order to realize alignment; the data of each passage would generally embed special alignment field at certain intervals; there is skew in the interchannel owing to receiving, data generally advanced row cache adjusts the data cached reading address of reading again and realizes going skew.
Below by specific embodiment, the design of the present invention is further described.
As it is shown in figure 1, the flow chart of the passage alignment schemes provided for one embodiment of the invention, mainly comprise the steps that
S101, determining a main channel from channel set to be aligned, other are secondary channels;And configure identical alignment clock to each passage, each channel reception data are transformed into the clock of described alignment clock and are stored in buffer memory.
Preferably, the mode of identical alignment clock is configured, it is possible to for: receive, from main channel, the recovered clock obtaining main channel data, the alignment clock of each passage is configured to the recovered clock of main channel.Configuring identical alignment clock can allow all passages in channel set to be aligned under same alignment clock, it is simple to by the detection of the alignment field of main channel controls the alignment of each passage.The mode receiving the recovered clock obtaining main channel data from main channel can be receive, from main channel, the recovered clock recovering main channel data.
Each channel reception data are transformed into the clock of described alignment clock and are stored in buffer memory and are specifically as follows: by each channel reception data through asynchronous buffer module, the clock of write is the recovered clock of this passage, read data and then adopt the alignment clock after step S101 configures, so just can completing clock zone conversion, the reception data of each passage are under alignment clock.Afterwards, then by each channel reception data after clock domain is changed it is stored in buffer memory.
Asynchronous buffer module can be such as asynchronous FIFO (First Input First Output) or asynchronous address autoincrement type random access memory (RAM).
If S102 main channel receives in data and alignment field detected, then according to the alignment field searches scope that each secondary channels of alignment field configuration that detects is data cached, and detect each secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field.
In step S101, each channel reception data are being stored in the process of buffer memory, can alignment field in each channel reception data of synchronous detecting, for secondary channels, then testing result is stored in buffer memory together with receiving data, like this, in step s 102, can according to the testing result in buffer memory, detect each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field, owing to having be carried out the detection of alignment field in step s 102, therefore step S102 detects according to testing result and can improve efficiency.
The alignment field searches scope that each secondary channels is data cached, it is possible to receive the scope of the front and back certain amplitude of the alignment field detected in data for main channel, front and back amplitude can be manually set.Ensure that secondary channels is search alignment field in the front and back certain limit of the alignment field of main channel, front and back amplitude configures in combinations with the situation of channel offset.
Preferably, in the substantially same time, detect each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
S103, data cached for main channel and detect alignment field secondary channels data cached, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.Preferably, data cached address is read in each passage adjustment, data cached action is read substantially in the same time in the position of field of aliging from correspondence.
In this step, detect that the secondary channels of alignment field achieves and the aliging of main channel.Preferably, to the secondary channels and the main channel that have detected that alignment field, also include preserving following information: the data cached address of reading behind the position of corresponding alignment field and adjustment;Or read the side-play amount of data cached address.This step, for alignment channel, has locked reading data cached address or reading the side-play amount of data cached address after adjusting.Therefore if owing to channel failure or other reason lose alignment, it is not required to remove channel data, it is only necessary to recalculate side-play amount.
Preferably, before preserving above-mentioned information, also include: judge in channel set to be aligned, whether each passage all completes to read the adjustment of data cached address;If so, all passages then illustrated in channel set to be aligned are completed alignment, enter back into the step preserving above-mentioned information.This step is after determining that all passages all realize alignment, relocks reading data cached address or reading the side-play amount of data cached address after each passage adjustment.
The present embodiment, by distinguishing main channel and secondary channels, is just searched for alignment field after the secondary channels only alignment field in main channel reception data being detected, is adjusted and read data cached address by data and main channel alignment.As long as secondary channels receives data and receives the skew that data existence is corresponding with main channel, when losing alignment or data packet format change etc., it is not necessary to additionally empty buffer memory, can realize constantly aliging with main channel.The motility of design is added while not increasing design complexities.
In another embodiment, it is possible to adopt the cascade signal in interchannel transmission, it is achieved multichannel alignment.As in figure 2 it is shown, mainly comprise the steps that
S201, determining a main channel from channel set to be aligned, other are secondary channels.
S202, receive data from main channel and recover recovered clock, the alignment clock of main channel is configured to its recovered clock;By interchannel cascade signal, the alignment clock of main channel is passed to neighboring later stage secondary channels, the alignment clock of this secondary channels is configured to the alignment clock of main channel by rear stage secondary channels, by that analogy, the alignment clock of this secondary channels is configured to the alignment clock of previous stage secondary channels by rear stage secondary channels again, until all passages all complete the configuration of alignment clock.So just the alignment clock of each passage is achieved unification.
S203, each channel reception data are transformed into this passage alignment clock clock zone, again each channel reception data after clock domain is changed are stored in buffer memory, and synchronously, detect the alignment field in each channel reception data, for secondary channels, then testing result is stored in buffer memory together with this channel reception data.
S204, main channel detect after having alignment field in this main channel reception data, then put the successful marking signal of detection, and this marking signal is being transferred to rear stage secondary channels, after this rear stage secondary channels receives notice, continue to transmit this marking signal to rear stage secondary channels again, until each secondary channels all receives this marking signal in channel set to be aligned.
S205, etc. after all secondary channels all receive this marking signal, in the substantially same time, each secondary channels receives in data, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected is data cached, and according to the testing result in buffer memory detect this secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field.In order to ensure that each passage adjusts the data cached address of reading simultaneously.
The alignment field searches scope of configuration, it is ensured that secondary channels is search alignment field in the front and back certain limit of the alignment field of main channel, and the scope of search configures in combinations with the situation of channel offset.
S206, main channel and detect alignment field secondary channels, in the substantially same time, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.
Additionally, secondary channels and the main channel of alignment field, the data cached address of reading behind the position of the alignment field that record is corresponding and adjustment detected;Or read the side-play amount of data cached address.
The alignment of data of each secondary channels and main channel alignment field being detected is achieved to this.Can also pass into step S207.
S207, according to interchannel cascade signal, all secondary channels are to main channel feedback information, according to the feedback information of all secondary channels, main channel judges whether all passages are completed alignment, if, the all passages then thought in channel set to be aligned align successfully, notify that each secondary channels locks the information of record in step S206, maintain multichannel alignment.
The schematic diagram of the passage alignment means that Fig. 3 provides for one embodiment of the invention, passage alignment means includes:
Determining module 31, for determining a main channel from channel set to be aligned, other are secondary channels;
Clock configuration module 32, for the alignment clock identical to the configuration of each passage;
Modular converter 34, for being transformed into the clock zone of described alignment clock by each channel reception data;
Buffer memory writing module 33, for being stored in buffer memory by each channel reception data after clock domain is changed;
Main channel alignment field detection module 35, receives the alignment field in data for detecting main channel;
Scope configuration module 36, detects alignment field if receiving in data for main channel, then according to the alignment field searches scope that each secondary channels of alignment field configuration detected is data cached;
Secondary channels alignment field detection module 37, for detect each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field;
Buffer memory read module 38, data cached for secondary channels that is data cached for main channel and that alignment field detected, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.
In certain embodiments, secondary channels alignment field detection module 37 includes:
First detection sub-module, receives each secondary channels in the process that data write buffer memory for buffer memory writing module 33, detects each secondary channels and receives the alignment field in data, obtains testing result;
Second detection sub-module, for according to the described testing result in buffer memory detect corresponding secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field;
Buffer memory writing module 33 is stored in buffer memory for described testing result being received with each secondary channels together with data.
In certain embodiments, the alignment clock of each passage, specifically for receiving the recovered clock obtaining main channel in data from main channel, is configured to the recovered clock of main channel by clock configuration module 32.
In certain embodiments, above-mentioned passage alignment means also includes preserving module, for preserving the position of the alignment field of each alignment channel, and the data cached address of reading after adjustment;Or preserve the side-play amount reading data cached address.
In certain embodiments, above-mentioned passage alignment means also includes judge module, for judging in described channel set to be aligned, whether each passage all completes to read the adjustment of data cached address;If so, then notify that above-mentioned preservation module carries out above-mentioned information preservation.
Passage alignment means provided by the invention can be independently of the entity arranged outside each passage, to the data buffer storage of each passage, the detection of alignment field, the configuration of alignment clock, alignment field searches scope configuration, read the adjustment of data cached address, data cached reading etc. is uniformly controlled.Or, the modules in passage alignment means provided by the invention is separately positioned in different entities;Or wherein part of module associates with passage, arrange with passage one_to_one corresponding.
The schematic diagram of the passage alignment that Fig. 4 provides for one embodiment of the invention, passage alignment includes:
Determining unit 41, for determining a main channel from channel set to be aligned, other are secondary channels;
Clock dispensing unit 42, for the alignment clock identical to the configuration of each passage;
Converting unit 43, for being transformed into the clock zone of described alignment clock by each channel reception data;
Main channel processing unit 44, is stored in buffer memory for the main channel after clock domain is changed receives data, and detection main channel receives the alignment field in data, if main channel receives in data alignment field detected, then and notice neighboring later stage secondary channels;It is additionally operable to according to the alignment field that detects and current reads data cached address, adjusting and read data cached address, according to the data cached address of reading after adjusting, starting to read data cached from the align position of field of correspondence;
At least one secondary channels processing unit (451 to 45n), each secondary channels processing unit is stored in buffer memory for this secondary channels after clock domain is changed is received data, after receiving notice, to rear stage secondary channels transmission notice again until afterbody secondary channels;Receive in data, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected is data cached, detect this secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field;It is additionally operable to according to the alignment field that detects and current reads data cached address, adjusting and read data cached address, according to the data cached address of reading after adjusting, starting to read data cached from the align position of field of correspondence.
In certain embodiments, each secondary channels processing unit is specifically for receiving in the process that data write buffer memory by this secondary channels, detect each secondary channels and receive the alignment field in data, obtain testing result, described testing result is received with this secondary channels and together with data, is stored in buffer memory;And according to the described testing result in buffer memory detect this secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
In certain embodiments, main channel processing unit, each secondary channels processing unit are additionally operable to preserve the position of the alignment field detected and the data cached address of reading after adjustment;Or preserve the side-play amount reading data cached address.
In certain embodiments, main channel processing unit is additionally operable to receive the feedback information that each secondary channels processing unit is transmitted by interchannel cascade signal, judges in described channel set to be aligned, whether all passages complete alignment according to the feedback information of each secondary channels processing unit.
Passage alignment provided by the invention, main channel processing unit 44 can associate setting with main channel, and other functional units such as associated with main channel are set together, and are arranged in same entity.Each secondary channels processing unit (451 to 45n) can also associate setting with secondary channels, secondary channels processing unit is arranged with secondary channels one_to_one corresponding, such as corresponding with certain secondary channels secondary channels processing unit, can be set together with other functional units associated with this secondary channels, be arranged in same entity.Determine that unit 41, clock dispensing unit 42, converting unit 43 can be arranged independent of outside each passage.Passage alignment provided by the invention adopts the cascade signal in interchannel transmission, it is achieved multichannel alignment.
Above content is in conjunction with specific embodiment further description made for the present invention, it is impossible to assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, it is also possible to make some simple deduction or replace, protection scope of the present invention all should be considered as belonging to.
Claims (15)
1. a passage alignment schemes, it is characterised in that including:
Determining a main channel from channel set to be aligned, other are secondary channels;And configure identical alignment clock to each passage, each channel reception data are transformed into the clock of described alignment clock and are stored in buffer memory;
If main channel receives in data alignment field detected, then according to the alignment field searches scope that each secondary channels of alignment field configuration detected is data cached, and detect each secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field;
Secondary channels that is data cached for main channel and that alignment field detected is data cached, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.
2. passage alignment schemes as claimed in claim 1, it is characterised in that each channel reception data are stored in the process of buffer memory, also include: detect the alignment field in each channel reception data, testing result is stored in buffer memory together with each channel reception data;
Within the scope of corresponding alignment field searches, whether have alignment field during each secondary channels of described detection is data cached particularly as follows: detect according to the testing result in buffer memory each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
3. passage alignment schemes as claimed in claim 1, it is characterized in that, the alignment clock of each passage, particularly as follows: receive, from main channel, the recovered clock obtaining main channel data, is configured to the recovered clock of main channel by the described alignment clock identical to the configuration of each passage.
4. passage alignment schemes as claimed in claim 1, it is characterized in that, if described main channel receives in data and alignment field detected, then according to the alignment field searches scope that each secondary channels of alignment field configuration that detects is data cached, and detect each secondary channels data cached in whether have within the scope of corresponding alignment field searches align field particularly as follows:
If main channel receives in data and alignment field detected, then main channel notice neighboring later stage secondary channels, after described rear stage secondary channels receives notice, continues to notify rear stage secondary channels again, until each secondary channels is all notified in described channel set to be aligned;And notified each secondary channels receives, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected in data is data cached, in the same time, each secondary channels detect this secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
5. passage alignment schemes according to any one of claims 1 to 4, it is characterised in that also include preserving following information: the position of the alignment field of each alignment channel, and the data cached address of reading after adjustment;Or read the side-play amount of data cached address.
6. passage alignment schemes as claimed in claim 5, it is characterised in that before preserving above-mentioned information, also include: judge in described channel set to be aligned, whether each passage all completes to read the adjustment of data cached address;If so, the step preserving above-mentioned information is then entered.
7. a passage alignment means, it is characterised in that including:
Determining module, for determining a main channel from channel set to be aligned, other are secondary channels;
Clock configuration module, for the alignment clock identical to the configuration of each passage;
Modular converter, for being transformed into the clock zone of described alignment clock by each channel reception data;
Buffer memory writing module, for being stored in buffer memory by each channel reception data after clock domain is changed;
Main channel alignment field detection module, receives the alignment field in data for detecting main channel;
Scope configuration module, detects alignment field if receiving in data for main channel, then according to the alignment field searches scope that each secondary channels of alignment field configuration detected is data cached;
Secondary channels alignment field detection module, for detect each secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field;
Buffer memory read module, data cached for secondary channels that is data cached for main channel and that alignment field detected, according to the alignment field detected and the data cached address of current reading, adjust and read data cached address, according to the data cached address of reading after adjusting, start to read data cached from the align position of field of correspondence.
8. passage alignment means as claimed in claim 7, it is characterised in that secondary channels alignment field detection module includes:
First detection sub-module, receives each secondary channels in the process that data write buffer memory for described buffer memory writing module, detects each secondary channels and receives the alignment field in data, obtains testing result;
Second detection sub-module, for according to the described testing result in buffer memory detect corresponding secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field;
Described buffer memory writing module is stored in buffer memory for described testing result being received with each secondary channels together with data.
9. passage alignment means as claimed in claim 7, it is characterised in that the alignment clock of each passage, specifically for receiving the recovered clock obtaining main channel in data from main channel, is configured to the recovered clock of main channel by described clock configuration module.
10. the passage alignment means as described in claim 7 to 9 any one, it is characterised in that also include preserving module, for preserving the position of the alignment field of each alignment channel, and the data cached address of reading after adjustment;Or preserve the side-play amount reading data cached address.
11. passage alignment means as claimed in claim 10, it is characterised in that also include judge module, for judging in described channel set to be aligned, whether each passage all completes to read the adjustment of data cached address;If so, then notify that described preservation module carries out above-mentioned information preservation.
12. a passage alignment, it is characterised in that including:
Determining unit, for determining a main channel from channel set to be aligned, other are secondary channels;
Clock dispensing unit, for the alignment clock identical to the configuration of each passage;
Converting unit, for being transformed into the clock zone of described alignment clock by each channel reception data;
Main channel processing unit, is stored in buffer memory for the main channel after clock domain is changed receives data, and detection main channel receives the alignment field in data, if main channel receives in data alignment field detected, then and notice neighboring later stage secondary channels;It is additionally operable to according to the alignment field that detects and current reads data cached address, adjusting and read data cached address, according to the data cached address of reading after adjusting, starting to read data cached from the align position of field of correspondence;
At least one secondary channels processing unit, each secondary channels processing unit is stored in buffer memory for this secondary channels after clock domain is changed is received data, after receiving notice, to rear stage secondary channels transmission notice again until afterbody secondary channels;Receive in data, according to main channel, the alignment field searches scope that alignment this secondary channels of field configuration detected is data cached, detect this secondary channels data cached within the scope of the alignment field searches of correspondence, whether have alignment field;It is additionally operable to according to the alignment field that detects and current reads data cached address, adjusting and read data cached address, according to the data cached address of reading after adjusting, starting to read data cached from the align position of field of correspondence.
13. passage alignment as claimed in claim 12, it is characterized in that, each secondary channels processing unit is specifically for receiving in the process that data write buffer memory by this secondary channels, detect each secondary channels and receive the alignment field in data, obtain testing result, described testing result is received with this secondary channels and together with data, is stored in buffer memory;And according to the described testing result in buffer memory detect this secondary channels data cached within the scope of corresponding alignment field searches, whether have alignment field.
14. the passage alignment as described in claim 12 or 13, it is characterised in that main channel processing unit, each secondary channels processing unit are additionally operable to preserve the position of the alignment field detected and the data cached address of reading after adjustment;Or preserve the side-play amount reading data cached address.
15. passage alignment as claimed in claim 14, it is characterized in that, main channel processing unit is additionally operable to receive the feedback information that each secondary channels processing unit is transmitted by interchannel cascade signal, judges in described channel set to be aligned, whether all passages complete alignment according to the feedback information of described each secondary channels processing unit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610025318.4A CN105718413B (en) | 2016-01-14 | 2016-01-14 | A kind of channel alignment schemes, apparatus and system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610025318.4A CN105718413B (en) | 2016-01-14 | 2016-01-14 | A kind of channel alignment schemes, apparatus and system |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105718413A true CN105718413A (en) | 2016-06-29 |
CN105718413B CN105718413B (en) | 2018-08-21 |
Family
ID=56147207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610025318.4A Active CN105718413B (en) | 2016-01-14 | 2016-01-14 | A kind of channel alignment schemes, apparatus and system |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105718413B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107272822A (en) * | 2017-06-16 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of system clock monitoring method and device |
CN108155964A (en) * | 2017-12-21 | 2018-06-12 | 南京理工大学 | FPGA multi-channel serial data dynamic alignment methods based on training sequence |
CN109861807A (en) * | 2019-02-28 | 2019-06-07 | 烽火通信科技股份有限公司 | Logical channel alignment schemes and system under multi-channel mode |
CN112671526A (en) * | 2020-12-23 | 2021-04-16 | 宸芯科技有限公司 | Method, device and equipment for aligning wire pairs of physical coding sublayer PCS of Ethernet |
CN113922876A (en) * | 2021-09-30 | 2022-01-11 | 中国船舶重工集团公司第七二四研究所 | Method for realizing multichannel optical fiber data alignment by utilizing multiple judgments |
WO2022126892A1 (en) * | 2020-12-17 | 2022-06-23 | 深圳市紫光同创电子有限公司 | Serdes interface circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101296217A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Elastic buffering mechanism and method for compensating clock diversity |
CN101299647A (en) * | 2008-06-27 | 2008-11-05 | 中兴通讯股份有限公司 | Apparatus and method for implementing nondestructive switch of SDH service |
CN101496367A (en) * | 2005-11-04 | 2009-07-29 | Nxp股份有限公司 | Alignment and deskew for multiple lanes of serial interconnect |
EP2139160A1 (en) * | 2007-04-13 | 2009-12-30 | Huawei Technologies Co., Ltd. | Method and device for controlling main-backup inversion |
CN102394823A (en) * | 2011-11-03 | 2012-03-28 | 中兴通讯股份有限公司 | Multi-channel aligning de-bias method and device |
-
2016
- 2016-01-14 CN CN201610025318.4A patent/CN105718413B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101496367A (en) * | 2005-11-04 | 2009-07-29 | Nxp股份有限公司 | Alignment and deskew for multiple lanes of serial interconnect |
EP2139160A1 (en) * | 2007-04-13 | 2009-12-30 | Huawei Technologies Co., Ltd. | Method and device for controlling main-backup inversion |
CN101296217A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Elastic buffering mechanism and method for compensating clock diversity |
CN101299647A (en) * | 2008-06-27 | 2008-11-05 | 中兴通讯股份有限公司 | Apparatus and method for implementing nondestructive switch of SDH service |
CN102394823A (en) * | 2011-11-03 | 2012-03-28 | 中兴通讯股份有限公司 | Multi-channel aligning de-bias method and device |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107272822A (en) * | 2017-06-16 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of system clock monitoring method and device |
CN108155964A (en) * | 2017-12-21 | 2018-06-12 | 南京理工大学 | FPGA multi-channel serial data dynamic alignment methods based on training sequence |
CN109861807A (en) * | 2019-02-28 | 2019-06-07 | 烽火通信科技股份有限公司 | Logical channel alignment schemes and system under multi-channel mode |
WO2022126892A1 (en) * | 2020-12-17 | 2022-06-23 | 深圳市紫光同创电子有限公司 | Serdes interface circuit |
CN112671526A (en) * | 2020-12-23 | 2021-04-16 | 宸芯科技有限公司 | Method, device and equipment for aligning wire pairs of physical coding sublayer PCS of Ethernet |
CN112671526B (en) * | 2020-12-23 | 2021-09-17 | 宸芯科技有限公司 | Method, device and equipment for aligning wire pairs of physical coding sublayer PCS of Ethernet |
CN113922876A (en) * | 2021-09-30 | 2022-01-11 | 中国船舶重工集团公司第七二四研究所 | Method for realizing multichannel optical fiber data alignment by utilizing multiple judgments |
Also Published As
Publication number | Publication date |
---|---|
CN105718413B (en) | 2018-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105718413A (en) | Channel alignment method, device and system | |
US8159887B2 (en) | Clock synchronization in a memory system | |
US7489756B2 (en) | Slave device with calibration signal generator for synchronous memory system | |
US10025345B2 (en) | System on chip and integrated circuit for performing skew calibration using dual edge and mobile device including the same | |
US8194652B2 (en) | Serializer for generating serial clock based on independent clock source and method for serial data transmission | |
CN101877633B (en) | Signal synchronizing method and system, signal receiving device and signal sending device | |
JP2006202281A (en) | Byte skew compensation method for pci express and pci express physical hierarchy receiver for it | |
CN1747376A (en) | Synchronization device and semiconductor device | |
CN101669318B (en) | Bias and random delay cancellation | |
JPH08507668A (en) | Deskew device for serial data bus | |
CN101432762A (en) | Signal transmission method, transmission/reception device, and communication system | |
CN102708074B (en) | Synchrodata processes system and method | |
US7007115B2 (en) | Removing lane-to-lane skew | |
US8995596B1 (en) | Techniques for calibrating a clock signal | |
US7792232B2 (en) | Method and system for link jitter compensation including a fast data recovery circuit | |
GB2336075A (en) | Phase alignment of data in high speed parallel data buses using adjustable high frequency sampling clocks | |
JP2023547185A (en) | Serdes interface circuit | |
US9094911B2 (en) | Data communication system, method of optimizing preamble length, and communication apparatus | |
CN106850178A (en) | The Transmission system of multipath high-speed serial image data | |
CN101950278A (en) | Framework of high speed and low power consumption serial communication data receiving interface | |
CN105718412A (en) | Channel frequency difference compensation method, and channel control method, device and system | |
JP4723554B2 (en) | Interface conversion method and apparatus between high-speed data having various data amounts | |
US20130241751A1 (en) | Providing a feedback loop in a low latency serial interconnect architecture | |
CN105718401A (en) | Multiplexing method and system for converting multi-path SMII signal to one-path MII signal | |
US20180188364A1 (en) | Method for determining sampling phase of sampling clock signal and associated electronic device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Applicant after: Shenzhen Pango Microsystems Co., Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Applicant before: SHENZHEN PANGO MICROSYSTEMS CO., LTD. |
|
COR | Change of bibliographic data | ||
GR01 | Patent grant | ||
GR01 | Patent grant |